Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.reqfifo

Module Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	832422	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	832422	0	0
T1	30773	164	0	0
T2	253077	32	0	0
T3	170782	7	0	0
T7	595894	453	0	0
T8	447015	125	0	0
T9	9335	61	0	0
T10	797180	51	0	0
T11	7686	106	0	0
T12	9549	113	0	0
T13	915814	2996	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	681774	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	681774	0	0
T1	30773	38	0	0
T2	253077	5	0	0
T3	170782	1067	0	0
T7	595894	607	0	0
T8	447015	9	0	0
T9	9335	46	0	0
T10	797180	2962	0	0
T11	7686	50	0	0
T12	9549	74	0	0
T13	915814	860	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	853436	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	853436	0	0
T1	30773	49	0	0
T2	253077	2	0	0
T3	170782	2	0	0
T7	595894	484	0	0
T8	447015	3	0	0
T9	9335	125	0	0
T10	797180	87	0	0
T11	7686	38	0	0
T12	9549	141	0	0
T13	915814	2277	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	780927	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	780927	0	0
T1	30773	172	0	0
T2	253077	2	0	0
T3	170782	2	0	0
T7	595894	723	0	0
T8	447015	133	0	0
T9	9335	51	0	0
T10	797180	16013	0	0
T11	7686	32	0	0
T12	9549	71	0	0
T13	915814	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	805858	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	805858	0	0
T1	30773	40	0	0
T2	253077	3	0	0
T3	170782	457	0	0
T7	595894	1821	0	0
T8	447015	7	0	0
T9	9335	161	0	0
T10	797180	73	0	0
T11	7686	29	0	0
T12	9549	121	0	0
T13	915814	183	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	923755	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	923755	0	0
T1	30773	44	0	0
T2	253077	3	0	0
T3	170782	190	0	0
T7	595894	2291	0	0
T8	447015	222	0	0
T9	9335	56	0	0
T10	797180	15773	0	0
T11	7686	28	0	0
T12	9549	62	0	0
T13	915814	138	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	787215	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	787215	0	0
T1	30773	115	0	0
T2	253077	3	0	0
T3	170782	5	0	0
T7	595894	6120	0	0
T8	447015	4	0	0
T9	9335	63	0	0
T10	797180	68	0	0
T11	7686	37	0	0
T12	9549	215	0	0
T13	915814	4797	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	836372	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	836372	0	0
T1	30773	54	0	0
T2	253077	3	0	0
T3	170782	5	0	0
T7	595894	776	0	0
T8	447015	4	0	0
T9	9335	39	0	0
T10	797180	16105	0	0
T11	7686	30	0	0
T12	9549	90	0	0
T13	915814	822	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	398960	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	398960	0	0
T1	30773	96	0	0
T2	253077	5	0	0
T3	170782	6	0	0
T7	595894	6869	0	0
T8	447015	12	0	0
T9	9335	50	0	0
T10	797180	80	0	0
T11	7686	27	0	0
T12	9549	79	0	0
T13	915814	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	733691	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	733691	0	0
T1	30773	88	0	0
T2	253077	5	0	0
T3	170782	6	0	0
T7	595894	1327	0	0
T8	447015	3066	0	0
T9	9335	50	0	0
T10	797180	14320	0	0
T11	7686	27	0	0
T12	9549	76	0	0
T13	915814	912	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	439123	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	439123	0	0
T1	30773	71	0	0
T2	253077	15	0	0
T3	170782	264	0	0
T7	595894	3968	0	0
T8	447015	26	0	0
T9	9335	59	0	0
T10	797180	47	0	0
T11	7686	33	0	0
T12	9549	77	0	0
T13	915814	753	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	722002	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	722002	0	0
T1	30773	68	0	0
T2	253077	6	0	0
T3	170782	6	0	0
T7	595894	1207	0	0
T8	447015	2166	0	0
T9	9335	59	0	0
T10	797180	5905	0	0
T11	7686	32	0	0
T12	9549	76	0	0
T13	915814	1001	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	611280	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	611280	0	0
T1	30773	65	0	0
T2	253077	3	0	0
T3	170782	1102	0	0
T7	595894	14056	0	0
T8	447015	9	0	0
T9	9335	34	0	0
T10	797180	51	0	0
T11	7686	38	0	0
T12	9549	73	0	0
T13	915814	3010	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	436808	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	436808	0	0
T1	30773	70	0	0
T2	253077	3	0	0
T3	170782	11	0	0
T7	595894	1201	0	0
T8	447015	808	0	0
T9	9335	31	0	0
T10	797180	6201	0	0
T11	7686	36	0	0
T12	9549	70	0	0
T13	915814	1287	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0