Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.reqfifo

Module Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	778708	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	778708	0	0
T1	30773	45	0	0
T2	253077	4	0	0
T3	170782	4	0	0
T7	595894	418	0	0
T8	447015	9	0	0
T9	9335	60	0	0
T10	797180	65	0	0
T11	7686	46	0	0
T12	9549	204	0	0
T13	915814	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	3486735	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3486735	0	0
T1	30773	315	0	0
T2	253077	1261	0	0
T3	170782	4	0	0
T7	595894	2617	0	0
T8	447015	2350	0	0
T9	9335	45	0	0
T10	797180	57	0	0
T11	7686	41	0	0
T12	9549	78	0	0
T13	915814	859	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	700121	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	700121	0	0
T1	30773	68	0	0
T2	253077	1	0	0
T3	170782	4	0	0
T7	595894	1557	0	0
T8	447015	7	0	0
T9	9335	134	0	0
T10	797180	60	0	0
T11	7686	35	0	0
T12	9549	142	0	0
T13	915814	2393	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	3623857	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3623857	0	0
T1	30773	452	0	0
T2	253077	764	0	0
T3	170782	311	0	0
T7	595894	6889	0	0
T8	447015	2854	0	0
T9	9335	50	0	0
T10	797180	247	0	0
T11	7686	34	0	0
T12	9549	70	0	0
T13	915814	1247	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	670103	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	670103	0	0
T1	30773	53	0	0
T2	253077	5	0	0
T3	170782	6	0	0
T7	595894	4724	0	0
T8	447015	5	0	0
T9	9335	81	0	0
T10	797180	59	0	0
T11	7686	35	0	0
T12	9549	190	0	0
T13	915814	413	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	3653896	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3653896	0	0
T1	30773	293	0	0
T2	253077	2669	0	0
T3	170782	400	0	0
T7	595894	5216	0	0
T8	447015	2487	0	0
T9	9335	47	0	0
T10	797180	634	0	0
T11	7686	34	0	0
T12	9549	89	0	0
T13	915814	2087	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	315467	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	315467	0	0
T1	30773	50	0	0
T2	253077	4	0	0
T3	170782	660	0	0
T7	595894	4886	0	0
T8	447015	8	0	0
T9	9335	54	0	0
T10	797180	74	0	0
T11	7686	29	0	0
T12	9549	88	0	0
T13	915814	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	3554546	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3554546	0	0
T1	30773	314	0	0
T2	253077	2098	0	0
T3	170782	812	0	0
T7	595894	6498	0	0
T8	447015	1704	0	0
T9	9335	49	0	0
T10	797180	70	0	0
T11	7686	26	0	0
T12	9549	76	0	0
T13	915814	651	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	335155	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	335155	0	0
T1	30773	46	0	0
T2	253077	6	0	0
T3	170782	12	0	0
T7	595894	2642	0	0
T8	447015	7	0	0
T9	9335	49	0	0
T10	797180	51	0	0
T11	7686	61	0	0
T12	9549	67	0	0
T13	915814	336	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	3716784	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3716784	0	0
T1	30773	326	0	0
T2	253077	1555	0	0
T3	170782	498	0	0
T7	595894	6781	0	0
T8	447015	2203	0	0
T9	9335	46	0	0
T10	797180	53	0	0
T11	7686	55	0	0
T12	9549	62	0	0
T13	915814	2387	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	480511	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	480511	0	0
T1	30773	52	0	0
T2	253077	5	0	0
T3	170782	608	0	0
T7	595894	10790	0	0
T8	447015	7	0	0
T9	9335	62	0	0
T10	797180	42	0	0
T11	7686	56	0	0
T12	9549	81	0	0
T13	915814	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	2750315	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	2750315	0	0
T1	30773	380	0	0
T2	253077	1517	0	0
T3	170782	243	0	0
T7	595894	6542	0	0
T8	447015	2489	0	0
T9	9335	55	0	0
T10	797180	42	0	0
T11	7686	49	0	0
T12	9549	66	0	0
T13	915814	1210	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	278587	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	278587	0	0
T1	30773	73	0	0
T2	253077	6	0	0
T3	170782	168	0	0
T7	595894	501	0	0
T8	447015	3	0	0
T9	9335	48	0	0
T10	797180	39	0	0
T11	7686	44	0	0
T12	9549	69	0	0
T13	915814	185	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396906024	3342775	0	0
DepthKnown_A	396906024	396790949	0	0
RvalidKnown_A	396906024	396790949	0	0
WreadyKnown_A	396906024	396790949	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	3342775	0	0
T1	30773	335	0	0
T2	253077	3106	0	0
T3	170782	824	0	0
T7	595894	3194	0	0
T8	447015	542	0	0
T9	9335	45	0	0
T10	797180	39	0	0
T11	7686	43	0	0
T12	9549	64	0	0
T13	915814	2304	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396906024	396790949	0	0
T1	30773	30753	0	0
T2	253077	253035	0	0
T3	170782	170738	0	0
T7	595894	595871	0	0
T8	447015	446967	0	0
T9	9335	9268	0	0
T10	797180	797169	0	0
T11	7686	7366	0	0
T12	9549	9507	0	0
T13	915814	915736	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0