SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.31 | 100.00 | 81.25 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
91.57 | 97.50 | 80.56 | 88.24 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 85.94 | 96.00 | 80.00 | 81.82 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
93.75 | 100.00 | 75.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
90.88 | 97.50 | 77.78 | 88.24 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 85.94 | 96.00 | 80.00 | 81.82 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[0].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[0].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[0].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[0].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_host_fifo[1].u_hostfifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_devicefifo |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 6 | 6 | 100.00 | |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 1 | 1 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Excluded | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 2984274 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 396906024 | 2984274 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 2984274 | 0 | 0 |
T1 | 30773 | 773 | 0 | 0 |
T2 | 253077 | 86 | 0 | 0 |
T3 | 170782 | 8937 | 0 | 0 |
T7 | 595894 | 11182 | 0 | 0 |
T8 | 447015 | 68 | 0 | 0 |
T9 | 9335 | 80 | 0 | 0 |
T10 | 797180 | 413 | 0 | 0 |
T11 | 7686 | 587 | 0 | 0 |
T12 | 9549 | 152 | 0 | 0 |
T13 | 915814 | 20642 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 2984274 | 0 | 0 |
T1 | 30773 | 773 | 0 | 0 |
T2 | 253077 | 86 | 0 | 0 |
T3 | 170782 | 8937 | 0 | 0 |
T7 | 595894 | 11182 | 0 | 0 |
T8 | 447015 | 68 | 0 | 0 |
T9 | 9335 | 80 | 0 | 0 |
T10 | 797180 | 413 | 0 | 0 |
T11 | 7686 | 587 | 0 | 0 |
T12 | 9549 | 152 | 0 | 0 |
T13 | 915814 | 20642 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 6 | 6 | 100.00 | |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 1 | 1 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Excluded | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 3684870 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 396906024 | 3684870 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 3684870 | 0 | 0 |
T1 | 30773 | 485 | 0 | 0 |
T2 | 253077 | 4439 | 0 | 0 |
T3 | 170782 | 658 | 0 | 0 |
T7 | 595894 | 5499 | 0 | 0 |
T8 | 447015 | 4829 | 0 | 0 |
T9 | 9335 | 80 | 0 | 0 |
T10 | 797180 | 7983 | 0 | 0 |
T11 | 7686 | 587 | 0 | 0 |
T12 | 9549 | 152 | 0 | 0 |
T13 | 915814 | 4433 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 3684870 | 0 | 0 |
T1 | 30773 | 485 | 0 | 0 |
T2 | 253077 | 4439 | 0 | 0 |
T3 | 170782 | 658 | 0 | 0 |
T7 | 595894 | 5499 | 0 | 0 |
T8 | 447015 | 4829 | 0 | 0 |
T9 | 9335 | 80 | 0 | 0 |
T10 | 797180 | 7983 | 0 | 0 |
T11 | 7686 | 587 | 0 | 0 |
T12 | 9549 | 152 | 0 | 0 |
T13 | 915814 | 4433 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 304485 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 304485 | 0 | 0 |
T1 | 30773 | 80 | 0 | 0 |
T2 | 253077 | 10 | 0 | 0 |
T3 | 170782 | 11 | 0 | 0 |
T7 | 595894 | 2198 | 0 | 0 |
T8 | 447015 | 8 | 0 | 0 |
T9 | 9335 | 37 | 0 | 0 |
T10 | 797180 | 53 | 0 | 0 |
T11 | 7686 | 507 | 0 | 0 |
T12 | 9549 | 74 | 0 | 0 |
T13 | 915814 | 489 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 3068912 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 3068912 | 0 | 0 |
T1 | 30773 | 426 | 0 | 0 |
T2 | 253077 | 4431 | 0 | 0 |
T3 | 170782 | 637 | 0 | 0 |
T7 | 595894 | 4580 | 0 | 0 |
T8 | 447015 | 3408 | 0 | 0 |
T9 | 9335 | 36 | 0 | 0 |
T10 | 797180 | 54 | 0 | 0 |
T11 | 7686 | 300 | 0 | 0 |
T12 | 9549 | 67 | 0 | 0 |
T13 | 915814 | 3501 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 389636 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 389636 | 0 | 0 |
T1 | 30773 | 67 | 0 | 0 |
T2 | 253077 | 8 | 0 | 0 |
T3 | 170782 | 1086 | 0 | 0 |
T7 | 595894 | 3252 | 0 | 0 |
T8 | 447015 | 15 | 0 | 0 |
T9 | 9335 | 46 | 0 | 0 |
T10 | 797180 | 63 | 0 | 0 |
T11 | 7686 | 458 | 0 | 0 |
T12 | 9549 | 85 | 0 | 0 |
T13 | 915814 | 1189 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 615958 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 615958 | 0 | 0 |
T1 | 30773 | 59 | 0 | 0 |
T2 | 253077 | 8 | 0 | 0 |
T3 | 170782 | 21 | 0 | 0 |
T7 | 595894 | 919 | 0 | 0 |
T8 | 447015 | 1421 | 0 | 0 |
T9 | 9335 | 44 | 0 | 0 |
T10 | 797180 | 7929 | 0 | 0 |
T11 | 7686 | 287 | 0 | 0 |
T12 | 9549 | 85 | 0 | 0 |
T13 | 915814 | 932 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 1214392 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 1214392 | 0 | 0 |
T1 | 30773 | 236 | 0 | 0 |
T2 | 253077 | 59 | 0 | 0 |
T3 | 170782 | 74 | 0 | 0 |
T7 | 595894 | 858 | 0 | 0 |
T8 | 447015 | 152 | 0 | 0 |
T9 | 9335 | 140 | 0 | 0 |
T10 | 797180 | 103 | 0 | 0 |
T11 | 7686 | 154 | 0 | 0 |
T12 | 9549 | 245 | 0 | 0 |
T13 | 915814 | 3558 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 3769867 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 3769867 | 0 | 0 |
T1 | 30773 | 427 | 0 | 0 |
T2 | 253077 | 3504 | 0 | 0 |
T3 | 170782 | 1293 | 0 | 0 |
T7 | 595894 | 3114 | 0 | 0 |
T8 | 447015 | 3413 | 0 | 0 |
T9 | 9335 | 86 | 0 | 0 |
T10 | 797180 | 2999 | 0 | 0 |
T11 | 7686 | 88 | 0 | 0 |
T12 | 9549 | 154 | 0 | 0 |
T13 | 915814 | 4627 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 708637 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 708637 | 0 | 0 |
T1 | 30773 | 85 | 0 | 0 |
T2 | 253077 | 27 | 0 | 0 |
T3 | 170782 | 67 | 0 | 0 |
T7 | 595894 | 406 | 0 | 0 |
T8 | 447015 | 27 | 0 | 0 |
T9 | 9335 | 79 | 0 | 0 |
T10 | 797180 | 52 | 0 | 0 |
T11 | 7686 | 110 | 0 | 0 |
T12 | 9549 | 139 | 0 | 0 |
T13 | 915814 | 562 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 3088093 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 3088093 | 0 | 0 |
T1 | 30773 | 389 | 0 | 0 |
T2 | 253077 | 3499 | 0 | 0 |
T3 | 170782 | 226 | 0 | 0 |
T7 | 595894 | 2507 | 0 | 0 |
T8 | 447015 | 3404 | 0 | 0 |
T9 | 9335 | 40 | 0 | 0 |
T10 | 797180 | 37 | 0 | 0 |
T11 | 7686 | 38 | 0 | 0 |
T12 | 9549 | 80 | 0 | 0 |
T13 | 915814 | 3767 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 832422 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 832422 | 0 | 0 |
T1 | 30773 | 164 | 0 | 0 |
T2 | 253077 | 32 | 0 | 0 |
T3 | 170782 | 7 | 0 | 0 |
T7 | 595894 | 453 | 0 | 0 |
T8 | 447015 | 125 | 0 | 0 |
T9 | 9335 | 61 | 0 | 0 |
T10 | 797180 | 51 | 0 | 0 |
T11 | 7686 | 106 | 0 | 0 |
T12 | 9549 | 113 | 0 | 0 |
T13 | 915814 | 2996 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 681774 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 681774 | 0 | 0 |
T1 | 30773 | 38 | 0 | 0 |
T2 | 253077 | 5 | 0 | 0 |
T3 | 170782 | 1067 | 0 | 0 |
T7 | 595894 | 607 | 0 | 0 |
T8 | 447015 | 9 | 0 | 0 |
T9 | 9335 | 46 | 0 | 0 |
T10 | 797180 | 2962 | 0 | 0 |
T11 | 7686 | 50 | 0 | 0 |
T12 | 9549 | 74 | 0 | 0 |
T13 | 915814 | 860 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 1225502 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 1225502 | 0 | 0 |
T1 | 30773 | 94 | 0 | 0 |
T2 | 253077 | 6 | 0 | 0 |
T3 | 170782 | 6 | 0 | 0 |
T7 | 595894 | 902 | 0 | 0 |
T8 | 447015 | 12 | 0 | 0 |
T9 | 9335 | 185 | 0 | 0 |
T10 | 797180 | 152 | 0 | 0 |
T11 | 7686 | 83 | 0 | 0 |
T12 | 9549 | 345 | 0 | 0 |
T13 | 915814 | 2292 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 396906024 | 4267662 | 0 | 0 |
DepthKnown_A | 396906024 | 396790949 | 0 | 0 |
RvalidKnown_A | 396906024 | 396790949 | 0 | 0 |
WreadyKnown_A | 396906024 | 396790949 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 900 | 900 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 4267662 | 0 | 0 |
T1 | 30773 | 487 | 0 | 0 |
T2 | 253077 | 1263 | 0 | 0 |
T3 | 170782 | 6 | 0 | 0 |
T7 | 595894 | 3340 | 0 | 0 |
T8 | 447015 | 2483 | 0 | 0 |
T9 | 9335 | 96 | 0 | 0 |
T10 | 797180 | 16070 | 0 | 0 |
T11 | 7686 | 73 | 0 | 0 |
T12 | 9549 | 149 | 0 | 0 |
T13 | 915814 | 885 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 396906024 | 396790949 | 0 | 0 |
T1 | 30773 | 30753 | 0 | 0 |
T2 | 253077 | 253035 | 0 | 0 |
T3 | 170782 | 170738 | 0 | 0 |
T7 | 595894 | 595871 | 0 | 0 |
T8 | 447015 | 446967 | 0 | 0 |
T9 | 9335 | 9268 | 0 | 0 |
T10 | 797180 | 797169 | 0 | 0 |
T11 | 7686 | 7366 | 0 | 0 |
T12 | 9549 | 9507 | 0 | 0 |
T13 | 915814 | 915736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 900 | 900 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |