Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1721160 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 273604 1 T1 540 T2 297 T3 29


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 677955 1 T1 1246 T2 674 T3 60
values[0x0] 640396 1 T1 1242 T2 668 T3 61
values[0x1] 676413 1 T1 1253 T2 640 T3 66


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1328794 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 665970 1 T1 1300 T2 644 T3 64


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 31351 1 T1 73 T2 42 T3 11
valid_sources[0x01] 30549 1 T1 62 T2 45 T3 6
valid_sources[0x02] 30740 1 T1 52 T2 6 T3 4
valid_sources[0x03] 32216 1 T1 68 T2 64 T3 2
valid_sources[0x04] 31512 1 T1 67 T2 62 T3 3
valid_sources[0x05] 31487 1 T1 61 T3 4 T8 25
valid_sources[0x06] 30751 1 T1 63 T2 21 T3 3
valid_sources[0x07] 30249 1 T1 54 T2 53 T3 4
valid_sources[0x08] 31371 1 T1 67 T2 32 T3 1
valid_sources[0x09] 31420 1 T1 57 T2 53 T3 2
valid_sources[0x0a] 30013 1 T1 62 T2 13 T3 1
valid_sources[0x0b] 30391 1 T1 48 T2 29 T3 3
valid_sources[0x0c] 31718 1 T1 49 T2 21 T3 6
valid_sources[0x0d] 32507 1 T1 63 T2 51 T3 4
valid_sources[0x0e] 32188 1 T1 56 T2 23 T3 4
valid_sources[0x0f] 31267 1 T1 54 T2 25 T3 4
valid_sources[0x10] 31867 1 T1 68 T2 66 T7 2
valid_sources[0x11] 31214 1 T1 49 T2 18 T3 1
valid_sources[0x12] 31973 1 T1 46 T2 24 T3 1
valid_sources[0x13] 31715 1 T1 69 T2 7 T3 3
valid_sources[0x14] 31444 1 T1 66 T2 21 T3 8
valid_sources[0x15] 31208 1 T1 71 T2 35 T3 2
valid_sources[0x16] 30202 1 T1 55 T2 21 T3 2
valid_sources[0x17] 31867 1 T1 59 T2 21 T3 1
valid_sources[0x18] 30486 1 T1 57 T2 36 T3 3
valid_sources[0x19] 31889 1 T1 46 T2 24 T3 4
valid_sources[0x1a] 30487 1 T1 60 T2 28 T3 2
valid_sources[0x1b] 31815 1 T1 60 T2 25 T8 35
valid_sources[0x1c] 31183 1 T1 59 T2 67 T3 1
valid_sources[0x1d] 31592 1 T1 56 T2 14 T3 3
valid_sources[0x1e] 31656 1 T1 68 T2 63 T3 9
valid_sources[0x1f] 30462 1 T1 49 T2 46 T3 3
valid_sources[0x20] 30399 1 T1 63 T3 1 T8 19


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 28953 1 T1 47 T2 34 T3 1
values[0x0] all_enables biggest_size 215977 1 T1 436 T2 239 T3 25
values[0x1] all_enables biggest_size 28674 1 T1 57 T2 24 T3 3


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1739308 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 283096 1 T1 485 T2 285 T3 19


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 693393 1 T1 1232 T2 757 T3 47
values[0x0] 635879 1 T1 1178 T2 608 T3 54
values[0x1] 693132 1 T1 1230 T2 710 T3 66


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1334346 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 688058 1 T1 1232 T2 699 T3 57


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 32248 1 T1 61 T2 34 T3 4
valid_sources[0x01] 32153 1 T1 64 T2 24 T3 4
valid_sources[0x02] 31021 1 T1 43 T2 33 T3 3
valid_sources[0x03] 31801 1 T1 83 T2 34 T8 29
valid_sources[0x04] 32468 1 T1 42 T2 27 T3 1
valid_sources[0x05] 32239 1 T1 110 T2 32 T3 2
valid_sources[0x06] 31815 1 T1 73 T2 41 T3 3
valid_sources[0x07] 31775 1 T1 94 T2 36 T3 8
valid_sources[0x08] 32058 1 T1 37 T2 35 T3 1
valid_sources[0x09] 31254 1 T1 48 T2 34 T3 1
valid_sources[0x0a] 31235 1 T1 40 T2 34 T8 25
valid_sources[0x0b] 30869 1 T1 31 T2 28 T3 4
valid_sources[0x0c] 31281 1 T1 38 T2 39 T3 2
valid_sources[0x0d] 32226 1 T1 39 T2 35 T3 5
valid_sources[0x0e] 31434 1 T1 67 T2 33 T3 2
valid_sources[0x0f] 31731 1 T1 52 T2 23 T8 16
valid_sources[0x10] 31826 1 T1 57 T2 38 T3 4
valid_sources[0x11] 30673 1 T1 34 T2 21 T8 33
valid_sources[0x12] 31778 1 T1 15 T2 32 T7 1
valid_sources[0x13] 32654 1 T1 71 T2 33 T3 2
valid_sources[0x14] 31575 1 T1 64 T2 31 T3 1
valid_sources[0x15] 31426 1 T1 64 T2 39 T3 5
valid_sources[0x16] 31445 1 T1 74 T2 35 T3 1
valid_sources[0x17] 31517 1 T1 56 T2 31 T3 1
valid_sources[0x18] 31180 1 T1 47 T2 37 T3 2
valid_sources[0x19] 31270 1 T1 78 T2 25 T3 7
valid_sources[0x1a] 31509 1 T1 70 T2 25 T3 2
valid_sources[0x1b] 32121 1 T1 65 T2 37 T3 5
valid_sources[0x1c] 31231 1 T1 55 T2 28 T3 8
valid_sources[0x1d] 31450 1 T1 42 T2 32 T8 22
valid_sources[0x1e] 31420 1 T1 44 T2 24 T3 3
valid_sources[0x1f] 31888 1 T1 71 T2 45 T3 3
valid_sources[0x20] 31138 1 T1 60 T2 32 T3 1


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 29921 1 T1 45 T2 32 T3 3
values[0x0] all_enables biggest_size 223623 1 T1 395 T2 214 T3 13
values[0x1] all_enables biggest_size 29552 1 T1 45 T2 39 T3 3


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1737774 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 276259 1 T1 496 T2 284 T3 23


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 683742 1 T1 1220 T2 643 T3 48
values[0x0] 646284 1 T1 1220 T2 658 T3 51
values[0x1] 684007 1 T1 1322 T2 624 T3 61


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1342278 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 671755 1 T1 1292 T2 667 T3 53


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 32357 1 T1 60 T2 37 T3 3
valid_sources[0x01] 30660 1 T1 62 T2 93 T3 2
valid_sources[0x02] 30630 1 T1 58 T2 27 T3 7
valid_sources[0x03] 32677 1 T1 59 T2 14 T3 10
valid_sources[0x04] 32091 1 T1 61 T3 2 T8 41
valid_sources[0x05] 31723 1 T1 68 T2 27 T3 5
valid_sources[0x06] 31162 1 T1 64 T2 26 T3 1
valid_sources[0x07] 32336 1 T1 61 T2 42 T3 1
valid_sources[0x08] 31245 1 T1 70 T2 33 T3 3
valid_sources[0x09] 30986 1 T1 55 T2 34 T3 5
valid_sources[0x0a] 30546 1 T1 54 T2 19 T3 3
valid_sources[0x0b] 31398 1 T1 62 T2 40 T3 2
valid_sources[0x0c] 31107 1 T1 61 T2 21 T3 3
valid_sources[0x0d] 32054 1 T1 58 T2 33 T3 1
valid_sources[0x0e] 31232 1 T1 54 T2 33 T8 25
valid_sources[0x0f] 32183 1 T1 52 T2 12 T3 1
valid_sources[0x10] 31526 1 T1 48 T2 1 T3 3
valid_sources[0x11] 30949 1 T1 69 T2 7 T3 3
valid_sources[0x12] 31110 1 T1 69 T2 23 T3 4
valid_sources[0x13] 31671 1 T1 61 T2 53 T7 1
valid_sources[0x14] 32387 1 T1 53 T2 51 T3 2
valid_sources[0x15] 31979 1 T1 69 T2 22 T3 2
valid_sources[0x16] 32055 1 T1 67 T2 19 T3 9
valid_sources[0x17] 32302 1 T1 64 T2 38 T8 2
valid_sources[0x18] 31418 1 T1 59 T2 22 T3 1
valid_sources[0x19] 30579 1 T1 55 T2 10 T3 1
valid_sources[0x1a] 31547 1 T1 65 T2 14 T3 1
valid_sources[0x1b] 32185 1 T1 63 T2 17 T3 3
valid_sources[0x1c] 31475 1 T1 48 T2 32 T3 1
valid_sources[0x1d] 31075 1 T1 53 T2 7 T3 4
valid_sources[0x1e] 30509 1 T1 56 T2 12 T3 3
valid_sources[0x1f] 31485 1 T1 56 T2 24 T8 19
valid_sources[0x20] 30873 1 T1 45 T2 19 T3 2


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 29094 1 T1 38 T2 34 T8 16
values[0x0] all_enables biggest_size 218006 1 T1 406 T2 223 T3 18
values[0x1] all_enables biggest_size 29159 1 T1 52 T2 27 T3 5

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%