Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_27.fifo_h.reqfifo

Module Instance : tb.dut.u_s1n_27.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.62	97.50	84.09			88.89	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.88	97.50	77.78			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_27.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	185840214	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	185840214	0	0
T1	548539	215017	0	0
T2	156058	106240	0	0
T3	579139	115063	0	0
T7	14425	2822	0	0
T8	153351	944851	0	0
T9	21337	10146	0	0
T10	3692	1087	0	0
T11	3416	488	0	0
T12	541477	122797	0	0
T13	55351	28258	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	68845528	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	68845528	0	0
T1	548539	132959	0	0
T2	156058	12276	0	0
T3	579139	63205	0	0
T7	14425	1032	0	0
T8	153351	9213	0	0
T9	21337	6113	0	0
T10	3692	340	0	0
T11	3416	177	0	0
T12	541477	222606	0	0
T13	55351	15505	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	2016249	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	2016249	0	0
T1	548539	1920	0	0
T2	156058	664	0	0
T3	579139	434	0	0
T7	14425	92	0	0
T8	153351	679	0	0
T9	21337	341	0	0
T10	3692	24	0	0
T11	3416	55	0	0
T12	541477	1732	0	0
T13	55351	947	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	17331304	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	17331304	0	0
T1	548539	324895	0	0
T2	156058	1868	0	0
T3	579139	12585	0	0
T7	14425	235	0	0
T8	153351	2355	0	0
T9	21337	1566	0	0
T10	3692	58	0	0
T11	3416	55	0	0
T12	541477	64687	0	0
T13	55351	4097	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	2041328	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	2041328	0	0
T1	548539	3176	0	0
T2	156058	697	0	0
T3	579139	1507	0	0
T7	14425	84	0	0
T8	153351	621	0	0
T9	21337	300	0	0
T10	3692	22	0	0
T11	3416	33	0	0
T12	541477	893	0	0
T13	55351	791	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	17422731	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	17422731	0	0
T1	548539	449636	0	0
T2	156058	2141	0	0
T3	579139	14839	0	0
T7	14425	136	0	0
T8	153351	1787	0	0
T9	21337	1699	0	0
T10	3692	53	0	0
T11	3416	30	0	0
T12	541477	3376	0	0
T13	55351	3893	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	11366503	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	11366503	0	0
T1	548539	4349	0	0
T2	156058	2412	0	0
T3	579139	15714	0	0
T7	14425	589	0	0
T8	153351	1940	0	0
T9	21337	1405	0	0
T10	3692	208	0	0
T11	3416	53	0	0
T12	541477	5435	0	0
T13	55351	3864	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	17483179	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	17483179	0	0
T1	548539	300795	0	0
T2	156058	3478	0	0
T3	579139	17551	0	0
T7	14425	255	0	0
T8	153351	2240	0	0
T9	21337	1515	0	0
T10	3692	98	0	0
T11	3416	53	0	0
T12	541477	152211	0	0
T13	55351	3572	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	2133763	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	2133763	0	0
T1	548539	972	0	0
T2	156058	826	0	0
T3	579139	617	0	0
T7	14425	53	0	0
T8	153351	576	0	0
T9	21337	282	0	0
T10	3692	28	0	0
T11	3416	45	0	0
T12	541477	878	0	0
T13	55351	1023	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	15597451	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	15597451	0	0
T1	548539	253870	0	0
T2	156058	4789	0	0
T3	579139	18230	0	0
T7	14425	133	0	0
T8	153351	2830	0	0
T9	21337	1330	0	0
T10	3692	59	0	0
T11	3416	39	0	0
T12	541477	2331	0	0
T13	55351	3943	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Total	Covered	Percent
Conditions	24	21	87.50
Logical	24	21	87.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	2	2	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Excluded	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	15598393	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	442452457	15598393	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	15598393	0	0
T1	548539	6807	0	0
T2	156058	3006	0	0
T3	579139	16234	0	0
T7	14425	923	0	0
T8	153351	2922	0	0
T9	21337	1713	0	0
T10	3692	304	0	0
T11	3416	69	0	0
T12	541477	5961	0	0
T13	55351	5321	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	15598393	0	0
T1	548539	6807	0	0
T2	156058	3006	0	0
T3	579139	16234	0	0
T7	14425	923	0	0
T8	153351	2922	0	0
T9	21337	1713	0	0
T10	3692	304	0	0
T11	3416	69	0	0
T12	541477	5961	0	0
T13	55351	5321	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	21700836	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	442452457	21700836	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	21700836	0	0
T1	548539	422223	0	0
T2	156058	13345	0	0
T3	579139	12636	0	0
T7	14425	411	0	0
T8	153351	28159	0	0
T9	21337	1566	0	0
T10	3692	75	0	0
T11	3416	69	0	0
T12	541477	152575	0	0
T13	55351	4458	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	21700836	0	0
T1	548539	422223	0	0
T2	156058	13345	0	0
T3	579139	12636	0	0
T7	14425	411	0	0
T8	153351	28159	0	0
T9	21337	1566	0	0
T10	3692	75	0	0
T11	3416	69	0	0
T12	541477	152575	0	0
T13	55351	4458	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	2016249	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	2016249	0	0
T1	548539	1920	0	0
T2	156058	664	0	0
T3	579139	434	0	0
T7	14425	92	0	0
T8	153351	679	0	0
T9	21337	341	0	0
T10	3692	24	0	0
T11	3416	55	0	0
T12	541477	1732	0	0
T13	55351	947	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	17331304	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	17331304	0	0
T1	548539	324895	0	0
T2	156058	1868	0	0
T3	579139	12585	0	0
T7	14425	235	0	0
T8	153351	2355	0	0
T9	21337	1566	0	0
T10	3692	58	0	0
T11	3416	55	0	0
T12	541477	64687	0	0
T13	55351	4097	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0