Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
301329 |
0 |
0 |
T1 |
548539 |
773 |
0 |
0 |
T2 |
156058 |
87 |
0 |
0 |
T3 |
579139 |
10 |
0 |
0 |
T7 |
14425 |
21 |
0 |
0 |
T8 |
153351 |
86 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
2 |
0 |
0 |
T11 |
3416 |
9 |
0 |
0 |
T12 |
541477 |
744 |
0 |
0 |
T13 |
55351 |
215 |
0 |
0 |
T14 |
0 |
1608 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3158873 |
0 |
0 |
T1 |
548539 |
78354 |
0 |
0 |
T2 |
156058 |
81 |
0 |
0 |
T3 |
579139 |
10 |
0 |
0 |
T7 |
14425 |
86 |
0 |
0 |
T8 |
153351 |
29324 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
2 |
0 |
0 |
T11 |
3416 |
8 |
0 |
0 |
T12 |
541477 |
75708 |
0 |
0 |
T13 |
55351 |
181 |
0 |
0 |
T14 |
0 |
778 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
415502 |
0 |
0 |
T1 |
548539 |
868 |
0 |
0 |
T2 |
156058 |
98 |
0 |
0 |
T3 |
579139 |
4 |
0 |
0 |
T7 |
14425 |
17 |
0 |
0 |
T8 |
153351 |
70 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
2 |
0 |
0 |
T11 |
3416 |
13 |
0 |
0 |
T12 |
541477 |
953 |
0 |
0 |
T13 |
55351 |
166 |
0 |
0 |
T14 |
0 |
1285 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
730644 |
0 |
0 |
T1 |
548539 |
14086 |
0 |
0 |
T2 |
156058 |
8741 |
0 |
0 |
T3 |
579139 |
4 |
0 |
0 |
T7 |
14425 |
27 |
0 |
0 |
T8 |
153351 |
1105 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
8 |
0 |
0 |
T11 |
3416 |
13 |
0 |
0 |
T12 |
541477 |
16073 |
0 |
0 |
T13 |
55351 |
103 |
0 |
0 |
T14 |
0 |
806 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T2,T3,T7 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3737368 |
0 |
0 |
T2 |
156058 |
869 |
0 |
0 |
T3 |
579139 |
4522 |
0 |
0 |
T7 |
14425 |
189 |
0 |
0 |
T8 |
153351 |
664 |
0 |
0 |
T9 |
21337 |
2376 |
0 |
0 |
T10 |
3692 |
50 |
0 |
0 |
T11 |
3416 |
11 |
0 |
0 |
T12 |
541477 |
2442 |
0 |
0 |
T13 |
55351 |
1330 |
0 |
0 |
T14 |
93068 |
1603 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3737368 |
0 |
0 |
T2 |
156058 |
869 |
0 |
0 |
T3 |
579139 |
4522 |
0 |
0 |
T7 |
14425 |
189 |
0 |
0 |
T8 |
153351 |
664 |
0 |
0 |
T9 |
21337 |
2376 |
0 |
0 |
T10 |
3692 |
50 |
0 |
0 |
T11 |
3416 |
11 |
0 |
0 |
T12 |
541477 |
2442 |
0 |
0 |
T13 |
55351 |
1330 |
0 |
0 |
T14 |
93068 |
1603 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T2,T3,T7 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
4220830 |
0 |
0 |
T2 |
156058 |
13004 |
0 |
0 |
T3 |
579139 |
2050 |
0 |
0 |
T7 |
14425 |
97 |
0 |
0 |
T8 |
153351 |
34099 |
0 |
0 |
T9 |
21337 |
2378 |
0 |
0 |
T10 |
3692 |
11 |
0 |
0 |
T11 |
3416 |
11 |
0 |
0 |
T12 |
541477 |
124864 |
0 |
0 |
T13 |
55351 |
294 |
0 |
0 |
T14 |
93068 |
1603 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
4220830 |
0 |
0 |
T2 |
156058 |
13004 |
0 |
0 |
T3 |
579139 |
2050 |
0 |
0 |
T7 |
14425 |
97 |
0 |
0 |
T8 |
153351 |
34099 |
0 |
0 |
T9 |
21337 |
2378 |
0 |
0 |
T10 |
3692 |
11 |
0 |
0 |
T11 |
3416 |
11 |
0 |
0 |
T12 |
541477 |
124864 |
0 |
0 |
T13 |
55351 |
294 |
0 |
0 |
T14 |
93068 |
1603 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
341444 |
0 |
0 |
T2 |
156058 |
109 |
0 |
0 |
T3 |
579139 |
9 |
0 |
0 |
T7 |
14425 |
11 |
0 |
0 |
T8 |
153351 |
101 |
0 |
0 |
T9 |
21337 |
1167 |
0 |
0 |
T10 |
3692 |
6 |
0 |
0 |
T11 |
3416 |
7 |
0 |
0 |
T12 |
541477 |
739 |
0 |
0 |
T13 |
55351 |
123 |
0 |
0 |
T14 |
93068 |
1808 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3509613 |
0 |
0 |
T2 |
156058 |
350 |
0 |
0 |
T3 |
579139 |
2043 |
0 |
0 |
T7 |
14425 |
73 |
0 |
0 |
T8 |
153351 |
29978 |
0 |
0 |
T9 |
21337 |
1784 |
0 |
0 |
T10 |
3692 |
8 |
0 |
0 |
T11 |
3416 |
6 |
0 |
0 |
T12 |
541477 |
113915 |
0 |
0 |
T13 |
55351 |
175 |
0 |
0 |
T14 |
93068 |
791 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
423611 |
0 |
0 |
T2 |
156058 |
148 |
0 |
0 |
T3 |
579139 |
7 |
0 |
0 |
T7 |
14425 |
13 |
0 |
0 |
T8 |
153351 |
92 |
0 |
0 |
T9 |
21337 |
1144 |
0 |
0 |
T10 |
3692 |
2 |
0 |
0 |
T11 |
3416 |
5 |
0 |
0 |
T12 |
541477 |
850 |
0 |
0 |
T13 |
55351 |
147 |
0 |
0 |
T14 |
93068 |
1328 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
711217 |
0 |
0 |
T2 |
156058 |
12654 |
0 |
0 |
T3 |
579139 |
7 |
0 |
0 |
T7 |
14425 |
24 |
0 |
0 |
T8 |
153351 |
4121 |
0 |
0 |
T9 |
21337 |
594 |
0 |
0 |
T10 |
3692 |
3 |
0 |
0 |
T11 |
3416 |
5 |
0 |
0 |
T12 |
541477 |
10949 |
0 |
0 |
T13 |
55351 |
119 |
0 |
0 |
T14 |
93068 |
812 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T2,T3,T7 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3878387 |
0 |
0 |
T2 |
156058 |
664 |
0 |
0 |
T3 |
579139 |
3562 |
0 |
0 |
T7 |
14425 |
128 |
0 |
0 |
T8 |
153351 |
643 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
92 |
0 |
0 |
T11 |
3416 |
9 |
0 |
0 |
T12 |
541477 |
6504 |
0 |
0 |
T13 |
55351 |
1316 |
0 |
0 |
T14 |
93068 |
1100 |
0 |
0 |
T16 |
0 |
1706 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3878387 |
0 |
0 |
T2 |
156058 |
664 |
0 |
0 |
T3 |
579139 |
3562 |
0 |
0 |
T7 |
14425 |
128 |
0 |
0 |
T8 |
153351 |
643 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
92 |
0 |
0 |
T11 |
3416 |
9 |
0 |
0 |
T12 |
541477 |
6504 |
0 |
0 |
T13 |
55351 |
1316 |
0 |
0 |
T14 |
93068 |
1100 |
0 |
0 |
T16 |
0 |
1706 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T2,T3,T7 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
4595442 |
0 |
0 |
T2 |
156058 |
9720 |
0 |
0 |
T3 |
579139 |
473 |
0 |
0 |
T7 |
14425 |
58 |
0 |
0 |
T8 |
153351 |
24958 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
41 |
0 |
0 |
T11 |
3416 |
9 |
0 |
0 |
T12 |
541477 |
298435 |
0 |
0 |
T13 |
55351 |
314 |
0 |
0 |
T14 |
93068 |
1100 |
0 |
0 |
T16 |
0 |
951 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
4595442 |
0 |
0 |
T2 |
156058 |
9720 |
0 |
0 |
T3 |
579139 |
473 |
0 |
0 |
T7 |
14425 |
58 |
0 |
0 |
T8 |
153351 |
24958 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
41 |
0 |
0 |
T11 |
3416 |
9 |
0 |
0 |
T12 |
541477 |
298435 |
0 |
0 |
T13 |
55351 |
314 |
0 |
0 |
T14 |
93068 |
1100 |
0 |
0 |
T16 |
0 |
951 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
364821 |
0 |
0 |
T2 |
156058 |
102 |
0 |
0 |
T3 |
579139 |
6 |
0 |
0 |
T7 |
14425 |
5 |
0 |
0 |
T8 |
153351 |
84 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
6 |
0 |
0 |
T11 |
3416 |
8 |
0 |
0 |
T12 |
541477 |
2061 |
0 |
0 |
T13 |
55351 |
102 |
0 |
0 |
T14 |
93068 |
1322 |
0 |
0 |
T16 |
0 |
162 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3831835 |
0 |
0 |
T2 |
156058 |
295 |
0 |
0 |
T3 |
579139 |
469 |
0 |
0 |
T7 |
14425 |
37 |
0 |
0 |
T8 |
153351 |
23514 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
17 |
0 |
0 |
T11 |
3416 |
7 |
0 |
0 |
T12 |
541477 |
254440 |
0 |
0 |
T13 |
55351 |
175 |
0 |
0 |
T14 |
93068 |
544 |
0 |
0 |
T16 |
0 |
748 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |