Line Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
456426 |
0 |
0 |
T2 |
156058 |
99 |
0 |
0 |
T3 |
579139 |
4 |
0 |
0 |
T7 |
14425 |
24 |
0 |
0 |
T8 |
153351 |
90 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
10 |
0 |
0 |
T11 |
3416 |
2 |
0 |
0 |
T12 |
541477 |
2525 |
0 |
0 |
T13 |
55351 |
191 |
0 |
0 |
T14 |
93068 |
1055 |
0 |
0 |
T16 |
0 |
318 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
763607 |
0 |
0 |
T2 |
156058 |
9425 |
0 |
0 |
T3 |
579139 |
4 |
0 |
0 |
T7 |
14425 |
21 |
0 |
0 |
T8 |
153351 |
1444 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
24 |
0 |
0 |
T11 |
3416 |
2 |
0 |
0 |
T12 |
541477 |
43995 |
0 |
0 |
T13 |
55351 |
139 |
0 |
0 |
T14 |
93068 |
556 |
0 |
0 |
T16 |
0 |
203 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T2,T3,T7 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3811278 |
0 |
0 |
T2 |
156058 |
701 |
0 |
0 |
T3 |
579139 |
3368 |
0 |
0 |
T7 |
14425 |
221 |
0 |
0 |
T8 |
153351 |
576 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
90 |
0 |
0 |
T11 |
3416 |
16 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
1535 |
0 |
0 |
T14 |
93068 |
2109 |
0 |
0 |
T15 |
0 |
4282 |
0 |
0 |
T16 |
0 |
1051 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3811278 |
0 |
0 |
T2 |
156058 |
701 |
0 |
0 |
T3 |
579139 |
3368 |
0 |
0 |
T7 |
14425 |
221 |
0 |
0 |
T8 |
153351 |
576 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
90 |
0 |
0 |
T11 |
3416 |
16 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
1535 |
0 |
0 |
T14 |
93068 |
2109 |
0 |
0 |
T15 |
0 |
4282 |
0 |
0 |
T16 |
0 |
1051 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T2,T3,T7 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
4120172 |
0 |
0 |
T2 |
156058 |
12466 |
0 |
0 |
T3 |
579139 |
145 |
0 |
0 |
T7 |
14425 |
94 |
0 |
0 |
T8 |
153351 |
26718 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
13 |
0 |
0 |
T11 |
3416 |
16 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
280 |
0 |
0 |
T14 |
93068 |
2109 |
0 |
0 |
T15 |
0 |
182454 |
0 |
0 |
T16 |
0 |
541 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
4120172 |
0 |
0 |
T2 |
156058 |
12466 |
0 |
0 |
T3 |
579139 |
145 |
0 |
0 |
T7 |
14425 |
94 |
0 |
0 |
T8 |
153351 |
26718 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
13 |
0 |
0 |
T11 |
3416 |
16 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
280 |
0 |
0 |
T14 |
93068 |
2109 |
0 |
0 |
T15 |
0 |
182454 |
0 |
0 |
T16 |
0 |
541 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
344428 |
0 |
0 |
T2 |
156058 |
75 |
0 |
0 |
T3 |
579139 |
6 |
0 |
0 |
T7 |
14425 |
11 |
0 |
0 |
T8 |
153351 |
79 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
3 |
0 |
0 |
T11 |
3416 |
8 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
107 |
0 |
0 |
T14 |
93068 |
1940 |
0 |
0 |
T15 |
0 |
1436 |
0 |
0 |
T16 |
0 |
117 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3337884 |
0 |
0 |
T2 |
156058 |
70 |
0 |
0 |
T3 |
579139 |
141 |
0 |
0 |
T7 |
14425 |
79 |
0 |
0 |
T8 |
153351 |
24548 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
5 |
0 |
0 |
T11 |
3416 |
8 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
184 |
0 |
0 |
T14 |
93068 |
1018 |
0 |
0 |
T15 |
0 |
153104 |
0 |
0 |
T16 |
0 |
455 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
446273 |
0 |
0 |
T2 |
156058 |
104 |
0 |
0 |
T3 |
579139 |
4 |
0 |
0 |
T7 |
14425 |
27 |
0 |
0 |
T8 |
153351 |
79 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
6 |
0 |
0 |
T11 |
3416 |
8 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
129 |
0 |
0 |
T14 |
93068 |
1602 |
0 |
0 |
T15 |
0 |
1801 |
0 |
0 |
T16 |
0 |
166 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
782288 |
0 |
0 |
T2 |
156058 |
12396 |
0 |
0 |
T3 |
579139 |
4 |
0 |
0 |
T7 |
14425 |
15 |
0 |
0 |
T8 |
153351 |
2170 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
8 |
0 |
0 |
T11 |
3416 |
8 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
96 |
0 |
0 |
T14 |
93068 |
1091 |
0 |
0 |
T15 |
0 |
29350 |
0 |
0 |
T16 |
0 |
86 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T2,T3,T7 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3860475 |
0 |
0 |
T2 |
156058 |
700 |
0 |
0 |
T3 |
579139 |
5411 |
0 |
0 |
T7 |
14425 |
297 |
0 |
0 |
T8 |
153351 |
557 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
142 |
0 |
0 |
T11 |
3416 |
13 |
0 |
0 |
T12 |
541477 |
2556 |
0 |
0 |
T13 |
55351 |
1462 |
0 |
0 |
T14 |
93068 |
654 |
0 |
0 |
T15 |
0 |
5001 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3860475 |
0 |
0 |
T2 |
156058 |
700 |
0 |
0 |
T3 |
579139 |
5411 |
0 |
0 |
T7 |
14425 |
297 |
0 |
0 |
T8 |
153351 |
557 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
142 |
0 |
0 |
T11 |
3416 |
13 |
0 |
0 |
T12 |
541477 |
2556 |
0 |
0 |
T13 |
55351 |
1462 |
0 |
0 |
T14 |
93068 |
654 |
0 |
0 |
T15 |
0 |
5001 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T2,T3,T7 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
4105746 |
0 |
0 |
T2 |
156058 |
10936 |
0 |
0 |
T3 |
579139 |
194 |
0 |
0 |
T7 |
14425 |
197 |
0 |
0 |
T8 |
153351 |
25715 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
26 |
0 |
0 |
T11 |
3416 |
13 |
0 |
0 |
T12 |
541477 |
130620 |
0 |
0 |
T13 |
55351 |
331 |
0 |
0 |
T14 |
93068 |
654 |
0 |
0 |
T15 |
0 |
230507 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
4105746 |
0 |
0 |
T2 |
156058 |
10936 |
0 |
0 |
T3 |
579139 |
194 |
0 |
0 |
T7 |
14425 |
197 |
0 |
0 |
T8 |
153351 |
25715 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
26 |
0 |
0 |
T11 |
3416 |
13 |
0 |
0 |
T12 |
541477 |
130620 |
0 |
0 |
T13 |
55351 |
331 |
0 |
0 |
T14 |
93068 |
654 |
0 |
0 |
T15 |
0 |
230507 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
357100 |
0 |
0 |
T2 |
156058 |
77 |
0 |
0 |
T3 |
579139 |
4 |
0 |
0 |
T7 |
14425 |
36 |
0 |
0 |
T8 |
153351 |
68 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
4 |
0 |
0 |
T11 |
3416 |
5 |
0 |
0 |
T12 |
541477 |
763 |
0 |
0 |
T13 |
55351 |
133 |
0 |
0 |
T14 |
93068 |
331 |
0 |
0 |
T15 |
0 |
1450 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3346356 |
0 |
0 |
T2 |
156058 |
330 |
0 |
0 |
T3 |
579139 |
186 |
0 |
0 |
T7 |
14425 |
164 |
0 |
0 |
T8 |
153351 |
23269 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
8 |
0 |
0 |
T11 |
3416 |
5 |
0 |
0 |
T12 |
541477 |
117299 |
0 |
0 |
T13 |
55351 |
208 |
0 |
0 |
T14 |
93068 |
315 |
0 |
0 |
T15 |
0 |
182823 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
465065 |
0 |
0 |
T2 |
156058 |
110 |
0 |
0 |
T3 |
579139 |
771 |
0 |
0 |
T7 |
14425 |
25 |
0 |
0 |
T8 |
153351 |
78 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
22 |
0 |
0 |
T11 |
3416 |
8 |
0 |
0 |
T12 |
541477 |
891 |
0 |
0 |
T13 |
55351 |
170 |
0 |
0 |
T14 |
93068 |
342 |
0 |
0 |
T15 |
0 |
1910 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
759390 |
0 |
0 |
T2 |
156058 |
10606 |
0 |
0 |
T3 |
579139 |
8 |
0 |
0 |
T7 |
14425 |
33 |
0 |
0 |
T8 |
153351 |
2446 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
18 |
0 |
0 |
T11 |
3416 |
8 |
0 |
0 |
T12 |
541477 |
13321 |
0 |
0 |
T13 |
55351 |
123 |
0 |
0 |
T14 |
93068 |
339 |
0 |
0 |
T15 |
0 |
47684 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |