Line Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T2,T3,T7 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3782956 |
0 |
0 |
T2 |
156058 |
734 |
0 |
0 |
T3 |
579139 |
7022 |
0 |
0 |
T7 |
14425 |
201 |
0 |
0 |
T8 |
153351 |
654 |
0 |
0 |
T9 |
21337 |
4804 |
0 |
0 |
T10 |
3692 |
68 |
0 |
0 |
T11 |
3416 |
17 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
1634 |
0 |
0 |
T14 |
93068 |
2596 |
0 |
0 |
T15 |
0 |
2065 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3782956 |
0 |
0 |
T2 |
156058 |
734 |
0 |
0 |
T3 |
579139 |
7022 |
0 |
0 |
T7 |
14425 |
201 |
0 |
0 |
T8 |
153351 |
654 |
0 |
0 |
T9 |
21337 |
4804 |
0 |
0 |
T10 |
3692 |
68 |
0 |
0 |
T11 |
3416 |
17 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
1634 |
0 |
0 |
T14 |
93068 |
2596 |
0 |
0 |
T15 |
0 |
2065 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T2,T3,T7 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3715107 |
0 |
0 |
T2 |
156058 |
10223 |
0 |
0 |
T3 |
579139 |
501 |
0 |
0 |
T7 |
14425 |
48 |
0 |
0 |
T8 |
153351 |
28459 |
0 |
0 |
T9 |
21337 |
1887 |
0 |
0 |
T10 |
3692 |
9 |
0 |
0 |
T11 |
3416 |
17 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
349 |
0 |
0 |
T14 |
93068 |
2596 |
0 |
0 |
T15 |
0 |
103139 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3715107 |
0 |
0 |
T2 |
156058 |
10223 |
0 |
0 |
T3 |
579139 |
501 |
0 |
0 |
T7 |
14425 |
48 |
0 |
0 |
T8 |
153351 |
28459 |
0 |
0 |
T9 |
21337 |
1887 |
0 |
0 |
T10 |
3692 |
9 |
0 |
0 |
T11 |
3416 |
17 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
349 |
0 |
0 |
T14 |
93068 |
2596 |
0 |
0 |
T15 |
0 |
103139 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
332382 |
0 |
0 |
T2 |
156058 |
98 |
0 |
0 |
T3 |
579139 |
6 |
0 |
0 |
T7 |
14425 |
6 |
0 |
0 |
T8 |
153351 |
90 |
0 |
0 |
T9 |
21337 |
2699 |
0 |
0 |
T10 |
3692 |
5 |
0 |
0 |
T11 |
3416 |
10 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
129 |
0 |
0 |
T14 |
93068 |
3235 |
0 |
0 |
T15 |
0 |
707 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3072527 |
0 |
0 |
T2 |
156058 |
1411 |
0 |
0 |
T3 |
579139 |
492 |
0 |
0 |
T7 |
14425 |
30 |
0 |
0 |
T8 |
153351 |
26708 |
0 |
0 |
T9 |
21337 |
924 |
0 |
0 |
T10 |
3692 |
6 |
0 |
0 |
T11 |
3416 |
10 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
239 |
0 |
0 |
T14 |
93068 |
1164 |
0 |
0 |
T15 |
0 |
89073 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
406922 |
0 |
0 |
T2 |
156058 |
108 |
0 |
0 |
T3 |
579139 |
214 |
0 |
0 |
T7 |
14425 |
38 |
0 |
0 |
T8 |
153351 |
85 |
0 |
0 |
T9 |
21337 |
3148 |
0 |
0 |
T10 |
3692 |
3 |
0 |
0 |
T11 |
3416 |
7 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
191 |
0 |
0 |
T14 |
93068 |
2885 |
0 |
0 |
T15 |
0 |
864 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
642580 |
0 |
0 |
T2 |
156058 |
8812 |
0 |
0 |
T3 |
579139 |
9 |
0 |
0 |
T7 |
14425 |
18 |
0 |
0 |
T8 |
153351 |
1751 |
0 |
0 |
T9 |
21337 |
963 |
0 |
0 |
T10 |
3692 |
3 |
0 |
0 |
T11 |
3416 |
7 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
110 |
0 |
0 |
T14 |
93068 |
1432 |
0 |
0 |
T15 |
0 |
14066 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3705690 |
0 |
0 |
T1 |
548539 |
2199 |
0 |
0 |
T2 |
156058 |
751 |
0 |
0 |
T3 |
579139 |
8500 |
0 |
0 |
T7 |
14425 |
225 |
0 |
0 |
T8 |
153351 |
633 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
30 |
0 |
0 |
T11 |
3416 |
16 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
1480 |
0 |
0 |
T14 |
0 |
616 |
0 |
0 |
T15 |
0 |
1952 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3705690 |
0 |
0 |
T1 |
548539 |
2199 |
0 |
0 |
T2 |
156058 |
751 |
0 |
0 |
T3 |
579139 |
8500 |
0 |
0 |
T7 |
14425 |
225 |
0 |
0 |
T8 |
153351 |
633 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
30 |
0 |
0 |
T11 |
3416 |
16 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
1480 |
0 |
0 |
T14 |
0 |
616 |
0 |
0 |
T15 |
0 |
1952 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3858460 |
0 |
0 |
T1 |
548539 |
87821 |
0 |
0 |
T2 |
156058 |
15423 |
0 |
0 |
T3 |
579139 |
395 |
0 |
0 |
T7 |
14425 |
130 |
0 |
0 |
T8 |
153351 |
31996 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
16 |
0 |
0 |
T11 |
3416 |
16 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
378 |
0 |
0 |
T14 |
0 |
616 |
0 |
0 |
T15 |
0 |
102834 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3858460 |
0 |
0 |
T1 |
548539 |
87821 |
0 |
0 |
T2 |
156058 |
15423 |
0 |
0 |
T3 |
579139 |
395 |
0 |
0 |
T7 |
14425 |
130 |
0 |
0 |
T8 |
153351 |
31996 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
16 |
0 |
0 |
T11 |
3416 |
16 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
378 |
0 |
0 |
T14 |
0 |
616 |
0 |
0 |
T15 |
0 |
102834 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
332499 |
0 |
0 |
T1 |
548539 |
767 |
0 |
0 |
T2 |
156058 |
83 |
0 |
0 |
T3 |
579139 |
8 |
0 |
0 |
T7 |
14425 |
30 |
0 |
0 |
T8 |
153351 |
80 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
2 |
0 |
0 |
T11 |
3416 |
4 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
128 |
0 |
0 |
T14 |
0 |
319 |
0 |
0 |
T15 |
0 |
696 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3173761 |
0 |
0 |
T1 |
548539 |
65283 |
0 |
0 |
T2 |
156058 |
1363 |
0 |
0 |
T3 |
579139 |
383 |
0 |
0 |
T7 |
14425 |
105 |
0 |
0 |
T8 |
153351 |
27795 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
14 |
0 |
0 |
T11 |
3416 |
4 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
242 |
0 |
0 |
T14 |
0 |
308 |
0 |
0 |
T15 |
0 |
86043 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
438642 |
0 |
0 |
T1 |
548539 |
1045 |
0 |
0 |
T2 |
156058 |
105 |
0 |
0 |
T3 |
579139 |
1067 |
0 |
0 |
T7 |
14425 |
9 |
0 |
0 |
T8 |
153351 |
75 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
2 |
0 |
0 |
T11 |
3416 |
12 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
158 |
0 |
0 |
T14 |
0 |
309 |
0 |
0 |
T15 |
0 |
853 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
684699 |
0 |
0 |
T1 |
548539 |
22538 |
0 |
0 |
T2 |
156058 |
14060 |
0 |
0 |
T3 |
579139 |
12 |
0 |
0 |
T7 |
14425 |
25 |
0 |
0 |
T8 |
153351 |
4201 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
2 |
0 |
0 |
T11 |
3416 |
12 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
136 |
0 |
0 |
T14 |
0 |
308 |
0 |
0 |
T15 |
0 |
16791 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T2,T3,T7 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3807625 |
0 |
0 |
T2 |
156058 |
745 |
0 |
0 |
T3 |
579139 |
5672 |
0 |
0 |
T7 |
14425 |
208 |
0 |
0 |
T8 |
153351 |
647 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
30 |
0 |
0 |
T11 |
3416 |
16 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
1350 |
0 |
0 |
T14 |
93068 |
1098 |
0 |
0 |
T16 |
0 |
512 |
0 |
0 |
T17 |
0 |
297 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3807625 |
0 |
0 |
T2 |
156058 |
745 |
0 |
0 |
T3 |
579139 |
5672 |
0 |
0 |
T7 |
14425 |
208 |
0 |
0 |
T8 |
153351 |
647 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
30 |
0 |
0 |
T11 |
3416 |
16 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
1350 |
0 |
0 |
T14 |
93068 |
1098 |
0 |
0 |
T16 |
0 |
512 |
0 |
0 |
T17 |
0 |
297 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T2,T3,T7 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
4125421 |
0 |
0 |
T2 |
156058 |
11331 |
0 |
0 |
T3 |
579139 |
389 |
0 |
0 |
T7 |
14425 |
109 |
0 |
0 |
T8 |
153351 |
29198 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
10 |
0 |
0 |
T11 |
3416 |
16 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
367 |
0 |
0 |
T14 |
93068 |
1098 |
0 |
0 |
T16 |
0 |
242 |
0 |
0 |
T17 |
0 |
82 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
4125421 |
0 |
0 |
T2 |
156058 |
11331 |
0 |
0 |
T3 |
579139 |
389 |
0 |
0 |
T7 |
14425 |
109 |
0 |
0 |
T8 |
153351 |
29198 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
10 |
0 |
0 |
T11 |
3416 |
16 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
367 |
0 |
0 |
T14 |
93068 |
1098 |
0 |
0 |
T16 |
0 |
242 |
0 |
0 |
T17 |
0 |
82 |
0 |
0 |