Line Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
351673 |
0 |
0 |
T2 |
156058 |
85 |
0 |
0 |
T3 |
579139 |
6 |
0 |
0 |
T7 |
14425 |
12 |
0 |
0 |
T8 |
153351 |
83 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
1 |
0 |
0 |
T11 |
3416 |
8 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
109 |
0 |
0 |
T14 |
93068 |
559 |
0 |
0 |
T16 |
0 |
37 |
0 |
0 |
T17 |
0 |
23 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3357443 |
0 |
0 |
T2 |
156058 |
84 |
0 |
0 |
T3 |
579139 |
382 |
0 |
0 |
T7 |
14425 |
95 |
0 |
0 |
T8 |
153351 |
26009 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
1 |
0 |
0 |
T11 |
3416 |
8 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
227 |
0 |
0 |
T14 |
93068 |
483 |
0 |
0 |
T16 |
0 |
199 |
0 |
0 |
T17 |
0 |
52 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
465049 |
0 |
0 |
T2 |
156058 |
96 |
0 |
0 |
T3 |
579139 |
471 |
0 |
0 |
T7 |
14425 |
18 |
0 |
0 |
T8 |
153351 |
93 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
3 |
0 |
0 |
T11 |
3416 |
8 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
187 |
0 |
0 |
T14 |
93068 |
648 |
0 |
0 |
T16 |
0 |
30 |
0 |
0 |
T17 |
0 |
25 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
767978 |
0 |
0 |
T2 |
156058 |
11247 |
0 |
0 |
T3 |
579139 |
7 |
0 |
0 |
T7 |
14425 |
14 |
0 |
0 |
T8 |
153351 |
3189 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
9 |
0 |
0 |
T11 |
3416 |
8 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
140 |
0 |
0 |
T14 |
93068 |
615 |
0 |
0 |
T16 |
0 |
43 |
0 |
0 |
T17 |
0 |
30 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3722596 |
0 |
0 |
T1 |
548539 |
2416 |
0 |
0 |
T2 |
156058 |
726 |
0 |
0 |
T3 |
579139 |
3702 |
0 |
0 |
T7 |
14425 |
244 |
0 |
0 |
T8 |
153351 |
659 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
75 |
0 |
0 |
T11 |
3416 |
18 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
1494 |
0 |
0 |
T14 |
0 |
1113 |
0 |
0 |
T15 |
0 |
2102 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3722596 |
0 |
0 |
T1 |
548539 |
2416 |
0 |
0 |
T2 |
156058 |
726 |
0 |
0 |
T3 |
579139 |
3702 |
0 |
0 |
T7 |
14425 |
244 |
0 |
0 |
T8 |
153351 |
659 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
75 |
0 |
0 |
T11 |
3416 |
18 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
1494 |
0 |
0 |
T14 |
0 |
1113 |
0 |
0 |
T15 |
0 |
2102 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3565447 |
0 |
0 |
T1 |
548539 |
99219 |
0 |
0 |
T2 |
156058 |
10549 |
0 |
0 |
T3 |
579139 |
461 |
0 |
0 |
T7 |
14425 |
149 |
0 |
0 |
T8 |
153351 |
35459 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
17 |
0 |
0 |
T11 |
3416 |
18 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
297 |
0 |
0 |
T14 |
0 |
1113 |
0 |
0 |
T15 |
0 |
97076 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3565447 |
0 |
0 |
T1 |
548539 |
99219 |
0 |
0 |
T2 |
156058 |
10549 |
0 |
0 |
T3 |
579139 |
461 |
0 |
0 |
T7 |
14425 |
149 |
0 |
0 |
T8 |
153351 |
35459 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
17 |
0 |
0 |
T11 |
3416 |
18 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
297 |
0 |
0 |
T14 |
0 |
1113 |
0 |
0 |
T15 |
0 |
97076 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
309227 |
0 |
0 |
T1 |
548539 |
756 |
0 |
0 |
T2 |
156058 |
95 |
0 |
0 |
T3 |
579139 |
10 |
0 |
0 |
T7 |
14425 |
26 |
0 |
0 |
T8 |
153351 |
80 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
5 |
0 |
0 |
T11 |
3416 |
13 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
101 |
0 |
0 |
T14 |
0 |
646 |
0 |
0 |
T15 |
0 |
699 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
2946300 |
0 |
0 |
T1 |
548539 |
89830 |
0 |
0 |
T2 |
156058 |
88 |
0 |
0 |
T3 |
579139 |
414 |
0 |
0 |
T7 |
14425 |
130 |
0 |
0 |
T8 |
153351 |
29707 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
12 |
0 |
0 |
T11 |
3416 |
11 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
150 |
0 |
0 |
T14 |
0 |
575 |
0 |
0 |
T15 |
0 |
87886 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
412620 |
0 |
0 |
T1 |
548539 |
867 |
0 |
0 |
T2 |
156058 |
102 |
0 |
0 |
T3 |
579139 |
8 |
0 |
0 |
T7 |
14425 |
17 |
0 |
0 |
T8 |
153351 |
99 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
11 |
0 |
0 |
T11 |
3416 |
7 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
142 |
0 |
0 |
T14 |
0 |
567 |
0 |
0 |
T15 |
0 |
814 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
619147 |
0 |
0 |
T1 |
548539 |
9389 |
0 |
0 |
T2 |
156058 |
10461 |
0 |
0 |
T3 |
579139 |
47 |
0 |
0 |
T7 |
14425 |
19 |
0 |
0 |
T8 |
153351 |
5752 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
5 |
0 |
0 |
T11 |
3416 |
7 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
147 |
0 |
0 |
T14 |
0 |
538 |
0 |
0 |
T15 |
0 |
9190 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3826446 |
0 |
0 |
T1 |
548539 |
2068 |
0 |
0 |
T2 |
156058 |
774 |
0 |
0 |
T3 |
579139 |
5469 |
0 |
0 |
T7 |
14425 |
159 |
0 |
0 |
T8 |
153351 |
692 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
88 |
0 |
0 |
T11 |
3416 |
16 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
1546 |
0 |
0 |
T14 |
0 |
1121 |
0 |
0 |
T16 |
0 |
582 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3826446 |
0 |
0 |
T1 |
548539 |
2068 |
0 |
0 |
T2 |
156058 |
774 |
0 |
0 |
T3 |
579139 |
5469 |
0 |
0 |
T7 |
14425 |
159 |
0 |
0 |
T8 |
153351 |
692 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
88 |
0 |
0 |
T11 |
3416 |
16 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
1546 |
0 |
0 |
T14 |
0 |
1121 |
0 |
0 |
T16 |
0 |
582 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3857646 |
0 |
0 |
T1 |
548539 |
81059 |
0 |
0 |
T2 |
156058 |
10102 |
0 |
0 |
T3 |
579139 |
213 |
0 |
0 |
T7 |
14425 |
76 |
0 |
0 |
T8 |
153351 |
34362 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
64 |
0 |
0 |
T11 |
3416 |
16 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
300 |
0 |
0 |
T14 |
0 |
1121 |
0 |
0 |
T16 |
0 |
324 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3857646 |
0 |
0 |
T1 |
548539 |
81059 |
0 |
0 |
T2 |
156058 |
10102 |
0 |
0 |
T3 |
579139 |
213 |
0 |
0 |
T7 |
14425 |
76 |
0 |
0 |
T8 |
153351 |
34362 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
64 |
0 |
0 |
T11 |
3416 |
16 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
300 |
0 |
0 |
T14 |
0 |
1121 |
0 |
0 |
T16 |
0 |
324 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_56.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_56.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
368785 |
0 |
0 |
T1 |
548539 |
719 |
0 |
0 |
T2 |
156058 |
95 |
0 |
0 |
T3 |
579139 |
10 |
0 |
0 |
T7 |
14425 |
13 |
0 |
0 |
T8 |
153351 |
88 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
7 |
0 |
0 |
T11 |
3416 |
11 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
165 |
0 |
0 |
T14 |
0 |
1293 |
0 |
0 |
T16 |
0 |
45 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_56.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_56.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3130229 |
0 |
0 |
T1 |
548539 |
70100 |
0 |
0 |
T2 |
156058 |
87 |
0 |
0 |
T3 |
579139 |
204 |
0 |
0 |
T7 |
14425 |
65 |
0 |
0 |
T8 |
153351 |
32908 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
51 |
0 |
0 |
T11 |
3416 |
10 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
175 |
0 |
0 |
T14 |
0 |
565 |
0 |
0 |
T16 |
0 |
250 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |