Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.reqfifo

Module Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	869083	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	869083	0	0
T1	548539	1400	0	0
T2	156058	108	0	0
T3	579139	7	0	0
T7	14425	24	0	0
T8	153351	103	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	34	0	0
T12	541477	7143	0	0
T13	55351	99	0	0
T14	0	1335	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	1046541	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	1046541	0	0
T1	548539	11269	0	0
T2	156058	9575	0	0
T3	579139	7	0	0
T7	14425	11	0	0
T8	153351	1075	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	7	0	0
T12	541477	1458	0	0
T13	55351	274	0	0
T14	0	562	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	766635	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	766635	0	0
T1	548539	4134	0	0
T2	156058	225	0	0
T3	579139	1514	0	0
T7	14425	8	0	0
T8	153351	83	0	0
T9	21337	0	0	0
T10	3692	3	0	0
T11	3416	19	0	0
T12	541477	0	0	0
T13	55351	115	0	0
T14	0	7914	0	0
T16	0	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	919357	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	919357	0	0
T1	548539	34691	0	0
T2	156058	423	0	0
T3	579139	14	0	0
T7	14425	8	0	0
T8	153351	5295	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	12	0	0
T12	541477	0	0	0
T13	55351	264	0	0
T14	0	1076	0	0
T16	0	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	873884	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	873884	0	0
T2	156058	160	0	0
T3	579139	5	0	0
T7	14425	6	0	0
T8	153351	84	0	0
T9	21337	1762	0	0
T10	3692	1	0	0
T11	3416	5	0	0
T12	541477	0	0	0
T13	55351	125	0	0
T14	93068	497	0	0
T15	0	1437	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	1039079	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	1039079	0	0
T2	156058	2958	0	0
T3	579139	93	0	0
T7	14425	6	0	0
T8	153351	5800	0	0
T9	21337	835	0	0
T10	3692	1	0	0
T11	3416	5	0	0
T12	541477	0	0	0
T13	55351	189	0	0
T14	93068	337	0	0
T15	0	10435	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	875055	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	875055	0	0
T1	548539	6206	0	0
T2	156058	147	0	0
T3	579139	3	0	0
T7	14425	74	0	0
T8	153351	87	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	6	0	0
T12	541477	1287	0	0
T13	55351	163	0	0
T14	0	4363	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	702476	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	702476	0	0
T1	548539	10387	0	0
T2	156058	6562	0	0
T3	579139	3	0	0
T7	14425	20	0	0
T8	153351	4855	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	6	0	0
T12	541477	16350	0	0
T13	55351	221	0	0
T14	0	1002	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	451516	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	451516	0	0
T2	156058	91	0	0
T3	579139	3	0	0
T7	14425	11	0	0
T8	153351	64	0	0
T9	21337	0	0	0
T10	3692	12	0	0
T11	3416	13	0	0
T12	541477	0	0	0
T13	55351	117	0	0
T14	93068	895	0	0
T16	0	38	0	0
T17	0	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	803414	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	803414	0	0
T2	156058	7641	0	0
T3	579139	3	0	0
T7	14425	11	0	0
T8	153351	952	0	0
T9	21337	0	0	0
T10	3692	20	0	0
T11	3416	13	0	0
T12	541477	0	0	0
T13	55351	115	0	0
T14	93068	770	0	0
T16	0	56	0	0
T17	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	439548	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	439548	0	0
T2	156058	114	0	0
T3	579139	1138	0	0
T7	14425	26	0	0
T8	153351	100	0	0
T9	21337	0	0	0
T10	3692	2	0	0
T11	3416	14	0	0
T12	541477	865	0	0
T13	55351	152	0	0
T14	93068	1386	0	0
T15	0	851	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	738691	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	738691	0	0
T2	156058	10173	0	0
T3	579139	8	0	0
T7	14425	24	0	0
T8	153351	3195	0	0
T9	21337	0	0	0
T10	3692	6	0	0
T11	3416	14	0	0
T12	541477	14668	0	0
T13	55351	123	0	0
T14	93068	777	0	0
T15	0	12253	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	664780	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	664780	0	0
T2	156058	108	0	0
T3	579139	3	0	0
T7	14425	8	0	0
T8	153351	76	0	0
T9	21337	0	0	0
T10	3692	3	0	0
T11	3416	0	0	0
T12	541477	0	0	0
T13	55351	180	0	0
T14	93068	345	0	0
T15	0	2623	0	0
T16	0	64	0	0
T17	0	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	453484	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	453484	0	0
T2	156058	8875	0	0
T3	579139	3	0	0
T7	14425	13	0	0
T8	153351	1905	0	0
T9	21337	0	0	0
T10	3692	12	0	0
T11	3416	0	0	0
T12	541477	0	0	0
T13	55351	102	0	0
T14	93068	319	0	0
T15	0	20002	0	0
T16	0	66	0	0
T17	0	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0