Unified Coverage Report :: Module Instance :: tb.dut.u_s1n_32.gen_dfifo[20].fifo_d.reqfifo

Module Instance : tb.dut.u_s1n_32.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_32.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_33.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.57	97.50	80.56			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_33.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.88	97.50	77.78			88.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.94	96.00	80.00			81.82

Module Instance : tb.dut.u_sm1_33.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_33.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_33.gen_host_fifo[1].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_33.gen_host_fifo[1].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	332499	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	332499	0	0
T1	548539	767	0	0
T2	156058	83	0	0
T3	579139	8	0	0
T7	14425	30	0	0
T8	153351	80	0	0
T9	21337	0	0	0
T10	3692	2	0	0
T11	3416	4	0	0
T12	541477	0	0	0
T13	55351	128	0	0
T14	0	319	0	0
T15	0	696	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	3173761	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3173761	0	0
T1	548539	65283	0	0
T2	156058	1363	0	0
T3	579139	383	0	0
T7	14425	105	0	0
T8	153351	27795	0	0
T9	21337	0	0	0
T10	3692	14	0	0
T11	3416	4	0	0
T12	541477	0	0	0
T13	55351	242	0	0
T14	0	308	0	0
T15	0	86043	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	351673	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	351673	0	0
T2	156058	85	0	0
T3	579139	6	0	0
T7	14425	12	0	0
T8	153351	83	0	0
T9	21337	0	0	0
T10	3692	1	0	0
T11	3416	8	0	0
T12	541477	0	0	0
T13	55351	109	0	0
T14	93068	559	0	0
T16	0	37	0	0
T17	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	3357443	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3357443	0	0
T2	156058	84	0	0
T3	579139	382	0	0
T7	14425	95	0	0
T8	153351	26009	0	0
T9	21337	0	0	0
T10	3692	1	0	0
T11	3416	8	0	0
T12	541477	0	0	0
T13	55351	227	0	0
T14	93068	483	0	0
T16	0	199	0	0
T17	0	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	309227	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	309227	0	0
T1	548539	756	0	0
T2	156058	95	0	0
T3	579139	10	0	0
T7	14425	26	0	0
T8	153351	80	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	13	0	0
T12	541477	0	0	0
T13	55351	101	0	0
T14	0	646	0	0
T15	0	699	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	2946300	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	2946300	0	0
T1	548539	89830	0	0
T2	156058	88	0	0
T3	579139	414	0	0
T7	14425	130	0	0
T8	153351	29707	0	0
T9	21337	0	0	0
T10	3692	12	0	0
T11	3416	11	0	0
T12	541477	0	0	0
T13	55351	150	0	0
T14	0	575	0	0
T15	0	87886	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	368785	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	368785	0	0
T1	548539	719	0	0
T2	156058	95	0	0
T3	579139	10	0	0
T7	14425	13	0	0
T8	153351	88	0	0
T9	21337	0	0	0
T10	3692	7	0	0
T11	3416	11	0	0
T12	541477	0	0	0
T13	55351	165	0	0
T14	0	1293	0	0
T16	0	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	3130229	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3130229	0	0
T1	548539	70100	0	0
T2	156058	87	0	0
T3	579139	204	0	0
T7	14425	65	0	0
T8	153351	32908	0	0
T9	21337	0	0	0
T10	3692	51	0	0
T11	3416	10	0	0
T12	541477	0	0	0
T13	55351	175	0	0
T14	0	565	0	0
T16	0	250	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.reqfifo

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	3680047	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	442452457	3680047	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3680047	0	0
T1	548539	2724	0	0
T2	156058	678	0	0
T3	579139	5664	0	0
T7	14425	258	0	0
T8	153351	582	0	0
T9	21337	0	0	0
T10	3692	40	0	0
T11	3416	8	0	0
T12	541477	2197	0	0
T13	55351	1411	0	0
T14	0	643	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3680047	0	0
T1	548539	2724	0	0
T2	156058	678	0	0
T3	579139	5664	0	0
T7	14425	258	0	0
T8	153351	582	0	0
T9	21337	0	0	0
T10	3692	40	0	0
T11	3416	8	0	0
T12	541477	2197	0	0
T13	55351	1411	0	0
T14	0	643	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.rspfifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	4824003	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	442452457	4824003	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	4824003	0	0
T1	548539	103151	0	0
T2	156058	9422	0	0
T3	579139	897	0	0
T7	14425	80	0	0
T8	153351	21723	0	0
T9	21337	0	0	0
T10	3692	8	0	0
T11	3416	8	0	0
T12	541477	103669	0	0
T13	55351	289	0	0
T14	0	643	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	4824003	0	0
T1	548539	103151	0	0
T2	156058	9422	0	0
T3	579139	897	0	0
T7	14425	80	0	0
T8	153351	21723	0	0
T9	21337	0	0	0
T10	3692	8	0	0
T11	3416	8	0	0
T12	541477	103669	0	0
T13	55351	289	0	0
T14	0	643	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	304078	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	304078	0	0
T1	548539	855	0	0
T2	156058	84	0	0
T3	579139	10	0	0
T7	14425	11	0	0
T8	153351	71	0	0
T9	21337	0	0	0
T10	3692	2	0	0
T11	3416	3	0	0
T12	541477	688	0	0
T13	55351	124	0	0
T14	0	328	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	3915511	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3915511	0	0
T1	548539	84075	0	0
T2	156058	264	0	0
T3	579139	888	0	0
T7	14425	65	0	0
T8	153351	19066	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	3	0	0
T12	541477	82026	0	0
T13	55351	155	0	0
T14	0	318	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[1].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[1].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	401093	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	401093	0	0
T1	548539	963	0	0
T2	156058	84	0	0
T3	579139	9	0	0
T7	14425	36	0	0
T8	153351	88	0	0
T9	21337	0	0	0
T10	3692	3	0	0
T11	3416	5	0	0
T12	541477	908	0	0
T13	55351	146	0	0
T14	0	326	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[1].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[1].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	908492	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	908492	0	0
T1	548539	19076	0	0
T2	156058	9158	0	0
T3	579139	9	0	0
T7	14425	15	0	0
T8	153351	2657	0	0
T9	21337	0	0	0
T10	3692	3	0	0
T11	3416	5	0	0
T12	541477	21643	0	0
T13	55351	134	0	0
T14	0	325	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0