Unified Coverage Report :: Module Instance :: tb.dut.u_sm1_38.gen_host_fifo[0].u_hostfifo.reqfifo

Module Instance : tb.dut.u_sm1_38.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_38.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_38.gen_host_fifo[1].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_38.gen_host_fifo[1].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_40.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_40.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_40.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_40.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_40.gen_host_fifo[1].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_40.gen_host_fifo[1].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[1].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_42.u_devicefifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_42.u_devicefifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		u_devicefifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_42.gen_host_fifo[0].u_hostfifo.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_42.gen_host_fifo[0].u_hostfifo.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_host_fifo[0].u_hostfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	676649	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	676649	0	0
T1	548539	3497	0	0
T2	156058	310	0	0
T3	579139	5	0	0
T7	14425	15	0	0
T8	153351	90	0	0
T9	21337	0	0	0
T10	3692	1	0	0
T11	3416	5	0	0
T12	541477	0	0	0
T13	55351	115	0	0
T14	0	10822	0	0
T16	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	4210949	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	4210949	0	0
T1	548539	265093	0	0
T2	156058	1045	0	0
T3	579139	5	0	0
T7	14425	142	0	0
T8	153351	36206	0	0
T9	21337	0	0	0
T10	3692	1	0	0
T11	3416	5	0	0
T12	541477	0	0	0
T13	55351	534	0	0
T14	0	1155	0	0
T16	0	364	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[1].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[1].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	766635	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	766635	0	0
T1	548539	4134	0	0
T2	156058	225	0	0
T3	579139	1514	0	0
T7	14425	8	0	0
T8	153351	83	0	0
T9	21337	0	0	0
T10	3692	3	0	0
T11	3416	19	0	0
T12	541477	0	0	0
T13	55351	115	0	0
T14	0	7914	0	0
T16	0	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[1].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[1].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	919357	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	919357	0	0
T1	548539	34691	0	0
T2	156058	423	0	0
T3	579139	14	0	0
T7	14425	8	0	0
T8	153351	5295	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	12	0	0
T12	541477	0	0	0
T13	55351	264	0	0
T14	0	1076	0	0
T16	0	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_40.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	1267078	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	1267078	0	0
T2	156058	341	0	0
T3	579139	13	0	0
T7	14425	30	0	0
T8	153351	179	0	0
T9	21337	2460	0	0
T10	3692	20	0	0
T11	3416	13	0	0
T12	541477	0	0	0
T13	55351	223	0	0
T14	93068	1004	0	0
T15	0	1696	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_40.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	4884306	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	4884306	0	0
T2	156058	3045	0	0
T3	579139	899	0	0
T7	14425	94	0	0
T8	153351	40216	0	0
T9	21337	1822	0	0
T10	3692	7	0	0
T11	3416	13	0	0
T12	541477	0	0	0
T13	55351	568	0	0
T14	93068	647	0	0
T15	0	110178	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	731563	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	731563	0	0
T2	156058	181	0	0
T3	579139	8	0	0
T7	14425	24	0	0
T8	153351	95	0	0
T9	21337	1427	0	0
T10	3692	19	0	0
T11	3416	8	0	0
T12	541477	0	0	0
T13	55351	98	0	0
T14	93068	514	0	0
T15	0	1123	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	3845227	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3845227	0	0
T2	156058	87	0	0
T3	579139	806	0	0
T7	14425	88	0	0
T8	153351	34416	0	0
T9	21337	987	0	0
T10	3692	6	0	0
T11	3416	8	0	0
T12	541477	0	0	0
T13	55351	379	0	0
T14	93068	310	0	0
T15	0	99743	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[1].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[1].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	873884	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	873884	0	0
T2	156058	160	0	0
T3	579139	5	0	0
T7	14425	6	0	0
T8	153351	84	0	0
T9	21337	1762	0	0
T10	3692	1	0	0
T11	3416	5	0	0
T12	541477	0	0	0
T13	55351	125	0	0
T14	93068	497	0	0
T15	0	1437	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[1].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[1].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	1039079	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	1039079	0	0
T2	156058	2958	0	0
T3	579139	93	0	0
T7	14425	6	0	0
T8	153351	5800	0	0
T9	21337	835	0	0
T10	3692	1	0	0
T11	3416	5	0	0
T12	541477	0	0	0
T13	55351	189	0	0
T14	93068	337	0	0
T15	0	10435	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_42.u_devicefifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	1305486	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	1305486	0	0
T1	548539	6822	0	0
T2	156058	247	0	0
T3	579139	12	0	0
T7	14425	126	0	0
T8	153351	167	0	0
T9	21337	0	0	0
T10	3692	6	0	0
T11	3416	12	0	0
T12	541477	1522	0	0
T13	55351	275	0	0
T14	0	6496	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.u_devicefifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_42.u_devicefifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	4094642	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	4094642	0	0
T1	548539	186409	0	0
T2	156058	6635	0	0
T3	579139	1115	0	0
T7	14425	90	0	0
T8	153351	36735	0	0
T9	21337	0	0	0
T10	3692	6	0	0
T11	3416	12	0	0
T12	541477	98917	0	0
T13	55351	617	0	0
T14	0	1996	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[0].u_hostfifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[0].u_hostfifo.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	740282	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	740282	0	0
T1	548539	5287	0	0
T2	156058	100	0	0
T3	579139	9	0	0
T7	14425	52	0	0
T8	153351	80	0	0
T9	21337	0	0	0
T10	3692	1	0	0
T11	3416	6	0	0
T12	541477	977	0	0
T13	55351	112	0	0
T14	0	4889	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[0].u_hostfifo.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[0].u_hostfifo.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442452457	3392166	0	0
DepthKnown_A	442452457	442312719	0	0
RvalidKnown_A	442452457	442312719	0	0
WreadyKnown_A	442452457	442312719	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3392166	0	0
T1	548539	176022	0	0
T2	156058	73	0	0
T3	579139	1112	0	0
T7	14425	70	0	0
T8	153351	31880	0	0
T9	21337	0	0	0
T10	3692	1	0	0
T11	3416	6	0	0
T12	541477	82567	0	0
T13	55351	396	0	0
T14	0	994	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0