Line Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
875055 |
0 |
0 |
T1 |
548539 |
6206 |
0 |
0 |
T2 |
156058 |
147 |
0 |
0 |
T3 |
579139 |
3 |
0 |
0 |
T7 |
14425 |
74 |
0 |
0 |
T8 |
153351 |
87 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
5 |
0 |
0 |
T11 |
3416 |
6 |
0 |
0 |
T12 |
541477 |
1287 |
0 |
0 |
T13 |
55351 |
163 |
0 |
0 |
T14 |
0 |
4363 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
702476 |
0 |
0 |
T1 |
548539 |
10387 |
0 |
0 |
T2 |
156058 |
6562 |
0 |
0 |
T3 |
579139 |
3 |
0 |
0 |
T7 |
14425 |
20 |
0 |
0 |
T8 |
153351 |
4855 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
5 |
0 |
0 |
T11 |
3416 |
6 |
0 |
0 |
T12 |
541477 |
16350 |
0 |
0 |
T13 |
55351 |
221 |
0 |
0 |
T14 |
0 |
1002 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T2,T3,T7 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3790635 |
0 |
0 |
T2 |
156058 |
757 |
0 |
0 |
T3 |
579139 |
2495 |
0 |
0 |
T7 |
14425 |
188 |
0 |
0 |
T8 |
153351 |
579 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
101 |
0 |
0 |
T11 |
3416 |
17 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
1570 |
0 |
0 |
T14 |
93068 |
1518 |
0 |
0 |
T16 |
0 |
412 |
0 |
0 |
T17 |
0 |
257 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3790635 |
0 |
0 |
T2 |
156058 |
757 |
0 |
0 |
T3 |
579139 |
2495 |
0 |
0 |
T7 |
14425 |
188 |
0 |
0 |
T8 |
153351 |
579 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
101 |
0 |
0 |
T11 |
3416 |
17 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
1570 |
0 |
0 |
T14 |
93068 |
1518 |
0 |
0 |
T16 |
0 |
412 |
0 |
0 |
T17 |
0 |
257 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T2,T3,T7 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
4184491 |
0 |
0 |
T2 |
156058 |
7736 |
0 |
0 |
T3 |
579139 |
303 |
0 |
0 |
T7 |
14425 |
89 |
0 |
0 |
T8 |
153351 |
32578 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
26 |
0 |
0 |
T11 |
3416 |
17 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
355 |
0 |
0 |
T14 |
93068 |
1518 |
0 |
0 |
T16 |
0 |
256 |
0 |
0 |
T17 |
0 |
50 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
4184491 |
0 |
0 |
T2 |
156058 |
7736 |
0 |
0 |
T3 |
579139 |
303 |
0 |
0 |
T7 |
14425 |
89 |
0 |
0 |
T8 |
153351 |
32578 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
26 |
0 |
0 |
T11 |
3416 |
17 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
355 |
0 |
0 |
T14 |
93068 |
1518 |
0 |
0 |
T16 |
0 |
256 |
0 |
0 |
T17 |
0 |
50 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
346787 |
0 |
0 |
T2 |
156058 |
112 |
0 |
0 |
T3 |
579139 |
4 |
0 |
0 |
T7 |
14425 |
26 |
0 |
0 |
T8 |
153351 |
88 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
4 |
0 |
0 |
T11 |
3416 |
4 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
171 |
0 |
0 |
T14 |
93068 |
946 |
0 |
0 |
T16 |
0 |
34 |
0 |
0 |
T17 |
0 |
15 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3381077 |
0 |
0 |
T2 |
156058 |
95 |
0 |
0 |
T3 |
579139 |
300 |
0 |
0 |
T7 |
14425 |
78 |
0 |
0 |
T8 |
153351 |
31626 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
6 |
0 |
0 |
T11 |
3416 |
4 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
240 |
0 |
0 |
T14 |
93068 |
748 |
0 |
0 |
T16 |
0 |
200 |
0 |
0 |
T17 |
0 |
24 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
451516 |
0 |
0 |
T2 |
156058 |
91 |
0 |
0 |
T3 |
579139 |
3 |
0 |
0 |
T7 |
14425 |
11 |
0 |
0 |
T8 |
153351 |
64 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
12 |
0 |
0 |
T11 |
3416 |
13 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
117 |
0 |
0 |
T14 |
93068 |
895 |
0 |
0 |
T16 |
0 |
38 |
0 |
0 |
T17 |
0 |
27 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
803414 |
0 |
0 |
T2 |
156058 |
7641 |
0 |
0 |
T3 |
579139 |
3 |
0 |
0 |
T7 |
14425 |
11 |
0 |
0 |
T8 |
153351 |
952 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
20 |
0 |
0 |
T11 |
3416 |
13 |
0 |
0 |
T12 |
541477 |
0 |
0 |
0 |
T13 |
55351 |
115 |
0 |
0 |
T14 |
93068 |
770 |
0 |
0 |
T16 |
0 |
56 |
0 |
0 |
T17 |
0 |
26 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.reqfifo
| Total | Covered | Percent |
Conditions | 16 | 13 | 81.25 |
Logical | 16 | 13 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T2,T3,T7 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3731368 |
0 |
0 |
T2 |
156058 |
724 |
0 |
0 |
T3 |
579139 |
7496 |
0 |
0 |
T7 |
14425 |
198 |
0 |
0 |
T8 |
153351 |
688 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
40 |
0 |
0 |
T11 |
3416 |
21 |
0 |
0 |
T12 |
541477 |
2094 |
0 |
0 |
T13 |
55351 |
1687 |
0 |
0 |
T14 |
93068 |
1558 |
0 |
0 |
T15 |
0 |
2510 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3731368 |
0 |
0 |
T2 |
156058 |
724 |
0 |
0 |
T3 |
579139 |
7496 |
0 |
0 |
T7 |
14425 |
198 |
0 |
0 |
T8 |
153351 |
688 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
40 |
0 |
0 |
T11 |
3416 |
21 |
0 |
0 |
T12 |
541477 |
2094 |
0 |
0 |
T13 |
55351 |
1687 |
0 |
0 |
T14 |
93068 |
1558 |
0 |
0 |
T15 |
0 |
2510 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.rspfifo
| Total | Covered | Percent |
Conditions | 16 | 12 | 75.00 |
Logical | 16 | 12 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T2,T3,T7 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T7 |
0 |
Excluded |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3916382 |
0 |
0 |
T2 |
156058 |
10255 |
0 |
0 |
T3 |
579139 |
310 |
0 |
0 |
T7 |
14425 |
115 |
0 |
0 |
T8 |
153351 |
33503 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
8 |
0 |
0 |
T11 |
3416 |
21 |
0 |
0 |
T12 |
541477 |
96370 |
0 |
0 |
T13 |
55351 |
383 |
0 |
0 |
T14 |
93068 |
1558 |
0 |
0 |
T15 |
0 |
122529 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3916382 |
0 |
0 |
T2 |
156058 |
10255 |
0 |
0 |
T3 |
579139 |
310 |
0 |
0 |
T7 |
14425 |
115 |
0 |
0 |
T8 |
153351 |
33503 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
8 |
0 |
0 |
T11 |
3416 |
21 |
0 |
0 |
T12 |
541477 |
96370 |
0 |
0 |
T13 |
55351 |
383 |
0 |
0 |
T14 |
93068 |
1558 |
0 |
0 |
T15 |
0 |
122529 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[0].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[0].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
337994 |
0 |
0 |
T2 |
156058 |
89 |
0 |
0 |
T3 |
579139 |
9 |
0 |
0 |
T7 |
14425 |
15 |
0 |
0 |
T8 |
153351 |
85 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
2 |
0 |
0 |
T11 |
3416 |
7 |
0 |
0 |
T12 |
541477 |
711 |
0 |
0 |
T13 |
55351 |
153 |
0 |
0 |
T14 |
93068 |
1820 |
0 |
0 |
T15 |
0 |
717 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[0].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[0].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
3177691 |
0 |
0 |
T2 |
156058 |
82 |
0 |
0 |
T3 |
579139 |
302 |
0 |
0 |
T7 |
14425 |
91 |
0 |
0 |
T8 |
153351 |
30308 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
2 |
0 |
0 |
T11 |
3416 |
7 |
0 |
0 |
T12 |
541477 |
81702 |
0 |
0 |
T13 |
55351 |
260 |
0 |
0 |
T14 |
93068 |
781 |
0 |
0 |
T15 |
0 |
110276 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[1].u_hostfifo.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[1].u_hostfifo.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
439548 |
0 |
0 |
T2 |
156058 |
114 |
0 |
0 |
T3 |
579139 |
1138 |
0 |
0 |
T7 |
14425 |
26 |
0 |
0 |
T8 |
153351 |
100 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
2 |
0 |
0 |
T11 |
3416 |
14 |
0 |
0 |
T12 |
541477 |
865 |
0 |
0 |
T13 |
55351 |
152 |
0 |
0 |
T14 |
93068 |
1386 |
0 |
0 |
T15 |
0 |
851 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[1].u_hostfifo.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[1].u_hostfifo.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
738691 |
0 |
0 |
T2 |
156058 |
10173 |
0 |
0 |
T3 |
579139 |
8 |
0 |
0 |
T7 |
14425 |
24 |
0 |
0 |
T8 |
153351 |
3195 |
0 |
0 |
T9 |
21337 |
0 |
0 |
0 |
T10 |
3692 |
6 |
0 |
0 |
T11 |
3416 |
14 |
0 |
0 |
T12 |
541477 |
14668 |
0 |
0 |
T13 |
55351 |
123 |
0 |
0 |
T14 |
93068 |
777 |
0 |
0 |
T15 |
0 |
12253 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
442452457 |
442312719 |
0 |
0 |
T1 |
548539 |
548533 |
0 |
0 |
T2 |
156058 |
156055 |
0 |
0 |
T3 |
579139 |
579085 |
0 |
0 |
T7 |
14425 |
14359 |
0 |
0 |
T8 |
153351 |
153349 |
0 |
0 |
T9 |
21337 |
21308 |
0 |
0 |
T10 |
3692 |
3631 |
0 |
0 |
T11 |
3416 |
3362 |
0 |
0 |
T12 |
541477 |
541469 |
0 |
0 |
T13 |
55351 |
55341 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |