Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8999787	0	0
GntImpliesValid_A	2147483647	8999787	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8999787	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	488416044	0	0
ReadyAndValidImplyGrant_A	2147483647	8999787	0	0
ReqAndReadyImplyGrant_A	2147483647	8999787	0	0
ReqImpliesValid_A	2147483647	38421887	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	53307	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8999787	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	13164936	13164792	0	0
T2	3745392	3745320	0	0
T3	13899336	13898040	0	0
T7	346200	344616	0	0
T8	3680424	3680376	0	0
T9	512088	511392	0	0
T10	88608	87144	0	0
T11	81984	80688	0	0
T12	12995448	12995256	0	0
T13	1328424	1328184	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8999787	0	0
T1	6582468	11140	0	0
T2	3745392	5981	0	0
T3	13899336	514	0	0
T7	346200	866	0	0
T8	3680424	5143	0	0
T9	512088	2207	0	0
T10	88608	273	0	0
T11	81984	512	0	0
T12	12995448	9309	0	0
T13	1328424	6534	0	0
T14	1116816	28161	0	0
T15	0	5841	0	0
T16	0	1758	0	0
T17	0	102	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8999787	0	0
T1	6582468	11140	0	0
T2	3745392	5981	0	0
T3	13899336	514	0	0
T7	346200	866	0	0
T8	3680424	5143	0	0
T9	512088	2207	0	0
T10	88608	273	0	0
T11	81984	512	0	0
T12	12995448	9309	0	0
T13	1328424	6534	0	0
T14	1116816	28161	0	0
T15	0	5841	0	0
T16	0	1758	0	0
T17	0	102	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	13164936	13164792	0	0
T2	3745392	3745320	0	0
T3	13899336	13898040	0	0
T7	346200	344616	0	0
T8	3680424	3680376	0	0
T9	512088	511392	0	0
T10	88608	87144	0	0
T11	81984	80688	0	0
T12	12995448	12995256	0	0
T13	1328424	1328184	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	13164936	13164792	0	0
T2	3745392	3745320	0	0
T3	13899336	13898040	0	0
T7	346200	344616	0	0
T8	3680424	3680376	0	0
T9	512088	511392	0	0
T10	88608	87144	0	0
T11	81984	80688	0	0
T12	12995448	12995256	0	0
T13	1328424	1328184	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8999787	0	0
T1	6582468	11140	0	0
T2	3745392	5981	0	0
T3	13899336	514	0	0
T7	346200	866	0	0
T8	3680424	5143	0	0
T9	512088	2207	0	0
T10	88608	273	0	0
T11	81984	512	0	0
T12	12995448	9309	0	0
T13	1328424	6534	0	0
T14	1116816	28161	0	0
T15	0	5841	0	0
T16	0	1758	0	0
T17	0	102	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	488416044	0	0
T1	12616397	505090	0	0
T2	3745392	159517	0	0
T3	13899336	737051	0	0
T7	346200	19377	0	0
T8	3680424	146900	0	0
T9	512088	24958	0	0
T10	88608	5125	0	0
T11	81984	1283	0	0
T12	12995448	489856	0	0
T13	1328424	84571	0	0
T14	93068	22450	0	0
T15	0	2824	0	0
T16	0	801	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8999787	0	0
T1	6582468	11140	0	0
T2	3745392	5981	0	0
T3	13899336	514	0	0
T7	346200	866	0	0
T8	3680424	5143	0	0
T9	512088	2207	0	0
T10	88608	273	0	0
T11	81984	512	0	0
T12	12995448	9309	0	0
T13	1328424	6534	0	0
T14	1116816	28161	0	0
T15	0	5841	0	0
T16	0	1758	0	0
T17	0	102	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8999787	0	0
T1	6582468	11140	0	0
T2	3745392	5981	0	0
T3	13899336	514	0	0
T7	346200	866	0	0
T8	3680424	5143	0	0
T9	512088	2207	0	0
T10	88608	273	0	0
T11	81984	512	0	0
T12	12995448	9309	0	0
T13	1328424	6534	0	0
T14	1116816	28161	0	0
T15	0	5841	0	0
T16	0	1758	0	0
T17	0	102	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38421887	0	0
T1	6582468	34451	0	0
T2	3745392	10416	0	0
T3	13899336	25997	0	0
T7	346200	2024	0	0
T8	3680424	8340	0	0
T9	512088	10678	0	0
T10	88608	560	0	0
T11	81984	598	0	0
T12	12995448	31270	0	0
T13	1328424	14402	0	0
T14	1116816	52095	0	0
T15	0	14569	0	0
T16	0	8283	0	0
T17	0	123	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	53307	0	21600
T1	1097078	22	0	2
T2	312116	0	0	2
T3	1158278	0	0	2
T7	28850	0	0	2
T8	306702	0	0	2
T9	42674	0	0	2
T10	7384	0	0	2
T11	6832	0	0	2
T12	1082954	37	0	2
T13	110702	1	0	2
T14	0	53	0	0
T15	0	17	0	0
T18	0	15	0	0
T19	0	19	0	0
T20	0	379	0	0
T21	0	1	0	0
T22	0	29	0	0
T23	0	54	0	0
T24	0	7	0	0
T25	0	15	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	13164936	13164792	0	0
T2	3745392	3745320	0	0
T3	13899336	13898040	0	0
T7	346200	344616	0	0
T8	3680424	3680376	0	0
T9	512088	511392	0	0
T10	88608	87144	0	0
T11	81984	80688	0	0
T12	12995448	12995256	0	0
T13	1328424	1328184	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8999787	0	0
T1	6582468	11140	0	0
T2	3745392	5981	0	0
T3	13899336	514	0	0
T7	346200	866	0	0
T8	3680424	5143	0	0
T9	512088	2207	0	0
T10	88608	273	0	0
T11	81984	512	0	0
T12	12995448	9309	0	0
T13	1328424	6534	0	0
T14	1116816	28161	0	0
T15	0	5841	0	0
T16	0	1758	0	0
T17	0	102	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	996624	0	0
GntImpliesValid_A	442452457	996624	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	996624	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	13420646	0	0
ReadyAndValidImplyGrant_A	442452457	996624	0	0
ReqAndReadyImplyGrant_A	442452457	996624	0	0
ReqImpliesValid_A	442452457	2707036	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	996624	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	996624	0	0
T1	548539	2266	0	0
T2	156058	652	0	0
T3	579139	56	0	0
T7	14425	85	0	0
T8	153351	594	0	0
T9	21337	208	0	0
T10	3692	27	0	0
T11	3416	46	0	0
T12	541477	614	0	0
T13	55351	688	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	996624	0	0
T1	548539	2266	0	0
T2	156058	652	0	0
T3	579139	56	0	0
T7	14425	85	0	0
T8	153351	594	0	0
T9	21337	208	0	0
T10	3692	27	0	0
T11	3416	46	0	0
T12	541477	614	0	0
T13	55351	688	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	996624	0	0
T1	548539	2266	0	0
T2	156058	652	0	0
T3	579139	56	0	0
T7	14425	85	0	0
T8	153351	594	0	0
T9	21337	208	0	0
T10	3692	27	0	0
T11	3416	46	0	0
T12	541477	614	0	0
T13	55351	688	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	13420646	0	0
T1	548539	7844	0	0
T2	156058	2801	0	0
T3	579139	17789	0	0
T7	14425	523	0	0
T8	153351	2367	0	0
T9	21337	1455	0	0
T10	3692	185	0	0
T11	3416	44	0	0
T12	541477	2602	0	0
T13	55351	4574	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	996624	0	0
T1	548539	2266	0	0
T2	156058	652	0	0
T3	579139	56	0	0
T7	14425	85	0	0
T8	153351	594	0	0
T9	21337	208	0	0
T10	3692	27	0	0
T11	3416	46	0	0
T12	541477	614	0	0
T13	55351	688	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	996624	0	0
T1	548539	2266	0	0
T2	156058	652	0	0
T3	579139	56	0	0
T7	14425	85	0	0
T8	153351	594	0	0
T9	21337	208	0	0
T10	3692	27	0	0
T11	3416	46	0	0
T12	541477	614	0	0
T13	55351	688	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	2707036	0	0
T1	548539	4689	0	0
T2	156058	884	0	0
T3	579139	1519	0	0
T7	14425	127	0	0
T8	153351	788	0	0
T9	21337	300	0	0
T10	3692	38	0	0
T11	3416	49	0	0
T12	541477	893	0	0
T13	55351	1171	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	996624	0	0
T1	548539	2266	0	0
T2	156058	652	0	0
T3	579139	56	0	0
T7	14425	85	0	0
T8	153351	594	0	0
T9	21337	208	0	0
T10	3692	27	0	0
T11	3416	46	0	0
T12	541477	614	0	0
T13	55351	688	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	997749	0	0
GntImpliesValid_A	442452457	997749	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	997749	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	13754000	0	0
ReadyAndValidImplyGrant_A	442452457	997749	0	0
ReqAndReadyImplyGrant_A	442452457	997749	0	0
ReqImpliesValid_A	442452457	2824721	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	997749	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	997749	0	0
T1	548539	680	0	0
T2	156058	720	0	0
T3	579139	59	0	0
T7	14425	66	0	0
T8	153351	545	0	0
T9	21337	188	0	0
T10	3692	31	0	0
T11	3416	45	0	0
T12	541477	638	0	0
T13	55351	687	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	997749	0	0
T1	548539	680	0	0
T2	156058	720	0	0
T3	579139	59	0	0
T7	14425	66	0	0
T8	153351	545	0	0
T9	21337	188	0	0
T10	3692	31	0	0
T11	3416	45	0	0
T12	541477	638	0	0
T13	55351	687	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	997749	0	0
T1	548539	680	0	0
T2	156058	720	0	0
T3	579139	59	0	0
T7	14425	66	0	0
T8	153351	545	0	0
T9	21337	188	0	0
T10	3692	31	0	0
T11	3416	45	0	0
T12	541477	638	0	0
T13	55351	687	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	13754000	0	0
T1	548539	2769	0	0
T2	156058	2898	0	0
T3	579139	17175	0	0
T7	14425	485	0	0
T8	153351	2128	0	0
T9	21337	1371	0	0
T10	3692	201	0	0
T11	3416	39	0	0
T12	541477	2514	0	0
T13	55351	4556	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	997749	0	0
T1	548539	680	0	0
T2	156058	720	0	0
T3	579139	59	0	0
T7	14425	66	0	0
T8	153351	545	0	0
T9	21337	188	0	0
T10	3692	31	0	0
T11	3416	45	0	0
T12	541477	638	0	0
T13	55351	687	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	997749	0	0
T1	548539	680	0	0
T2	156058	720	0	0
T3	579139	59	0	0
T7	14425	66	0	0
T8	153351	545	0	0
T9	21337	188	0	0
T10	3692	31	0	0
T11	3416	45	0	0
T12	541477	638	0	0
T13	55351	687	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	2824721	0	0
T1	548539	972	0	0
T2	156058	1050	0	0
T3	579139	672	0	0
T7	14425	70	0	0
T8	153351	736	0	0
T9	21337	282	0	0
T10	3692	33	0	0
T11	3416	52	0	0
T12	541477	878	0	0
T13	55351	1354	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	997749	0	0
T1	548539	680	0	0
T2	156058	720	0	0
T3	579139	59	0	0
T7	14425	66	0	0
T8	153351	545	0	0
T9	21337	188	0	0
T10	3692	31	0	0
T11	3416	45	0	0
T12	541477	638	0	0
T13	55351	687	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	244054	0	0
GntImpliesValid_A	442452457	244054	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	244054	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	3327915	0	0
ReadyAndValidImplyGrant_A	442452457	244054	0	0
ReqAndReadyImplyGrant_A	442452457	244054	0	0
ReqImpliesValid_A	442452457	598343	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	244054	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	244054	0	0
T1	548539	561	0	0
T2	156058	145	0	0
T3	579139	19	0	0
T7	14425	26	0	0
T8	153351	127	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	8	0	0
T12	541477	470	0	0
T13	55351	183	0	0
T14	0	643	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	244054	0	0
T1	548539	561	0	0
T2	156058	145	0	0
T3	579139	19	0	0
T7	14425	26	0	0
T8	153351	127	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	8	0	0
T12	541477	470	0	0
T13	55351	183	0	0
T14	0	643	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	244054	0	0
T1	548539	561	0	0
T2	156058	145	0	0
T3	579139	19	0	0
T7	14425	26	0	0
T8	153351	127	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	8	0	0
T12	541477	470	0	0
T13	55351	183	0	0
T14	0	643	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3327915	0	0
T1	548539	1968	0	0
T2	156058	656	0	0
T3	579139	5665	0	0
T7	14425	238	0	0
T8	153351	551	0	0
T9	21337	1	0	0
T10	3692	41	0	0
T11	3416	9	0	0
T12	541477	1521	0	0
T13	55351	1325	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	244054	0	0
T1	548539	561	0	0
T2	156058	145	0	0
T3	579139	19	0	0
T7	14425	26	0	0
T8	153351	127	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	8	0	0
T12	541477	470	0	0
T13	55351	183	0	0
T14	0	643	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	244054	0	0
T1	548539	561	0	0
T2	156058	145	0	0
T3	579139	19	0	0
T7	14425	26	0	0
T8	153351	127	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	8	0	0
T12	541477	470	0	0
T13	55351	183	0	0
T14	0	643	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	598343	0	0
T1	548539	1318	0	0
T2	156058	168	0	0
T3	579139	19	0	0
T7	14425	47	0	0
T8	153351	159	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	8	0	0
T12	541477	1147	0	0
T13	55351	270	0	0
T14	0	652	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	244054	0	0
T1	548539	561	0	0
T2	156058	145	0	0
T3	579139	19	0	0
T7	14425	26	0	0
T8	153351	127	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	8	0	0
T12	541477	470	0	0
T13	55351	183	0	0
T14	0	643	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	243589	0	0
GntImpliesValid_A	442452457	243589	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	243589	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	3344837	0	0
ReadyAndValidImplyGrant_A	442452457	243589	0	0
ReqAndReadyImplyGrant_A	442452457	243589	0	0
ReqImpliesValid_A	442452457	602061	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	243589	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	243589	0	0
T2	156058	167	0	0
T3	579139	18	0	0
T7	14425	27	0	0
T8	153351	132	0	0
T9	21337	0	0	0
T10	3692	10	0	0
T11	3416	10	0	0
T12	541477	0	0	0
T13	55351	188	0	0
T14	93068	619	0	0
T15	0	1032	0	0
T16	0	496	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	243589	0	0
T2	156058	167	0	0
T3	579139	18	0	0
T7	14425	27	0	0
T8	153351	132	0	0
T9	21337	0	0	0
T10	3692	10	0	0
T11	3416	10	0	0
T12	541477	0	0	0
T13	55351	188	0	0
T14	93068	619	0	0
T15	0	1032	0	0
T16	0	496	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	243589	0	0
T2	156058	167	0	0
T3	579139	18	0	0
T7	14425	27	0	0
T8	153351	132	0	0
T9	21337	0	0	0
T10	3692	10	0	0
T11	3416	10	0	0
T12	541477	0	0	0
T13	55351	188	0	0
T14	93068	619	0	0
T15	0	1032	0	0
T16	0	496	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3344837	0	0
T1	548539	1	0	0
T2	156058	692	0	0
T3	579139	5605	0	0
T7	14425	209	0	0
T8	153351	529	0	0
T9	21337	1	0	0
T10	3692	80	0	0
T11	3416	11	0	0
T12	541477	1	0	0
T13	55351	1391	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	243589	0	0
T2	156058	167	0	0
T3	579139	18	0	0
T7	14425	27	0	0
T8	153351	132	0	0
T9	21337	0	0	0
T10	3692	10	0	0
T11	3416	10	0	0
T12	541477	0	0	0
T13	55351	188	0	0
T14	93068	619	0	0
T15	0	1032	0	0
T16	0	496	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	243589	0	0
T2	156058	167	0	0
T3	579139	18	0	0
T7	14425	27	0	0
T8	153351	132	0	0
T9	21337	0	0	0
T10	3692	10	0	0
T11	3416	10	0	0
T12	541477	0	0	0
T13	55351	188	0	0
T14	93068	619	0	0
T15	0	1032	0	0
T16	0	496	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	602061	0	0
T2	156058	187	0	0
T3	579139	491	0	0
T7	14425	38	0	0
T8	153351	185	0	0
T9	21337	0	0	0
T10	3692	10	0	0
T11	3416	10	0	0
T12	541477	0	0	0
T13	55351	245	0	0
T14	93068	632	0	0
T15	0	2343	0	0
T16	0	4784	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	243589	0	0
T2	156058	167	0	0
T3	579139	18	0	0
T7	14425	27	0	0
T8	153351	132	0	0
T9	21337	0	0	0
T10	3692	10	0	0
T11	3416	10	0	0
T12	541477	0	0	0
T13	55351	188	0	0
T14	93068	619	0	0
T15	0	1032	0	0
T16	0	496	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	246423	0	0
GntImpliesValid_A	442452457	246423	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	246423	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	5800191	0	0
ReadyAndValidImplyGrant_A	442452457	246423	0	0
ReqAndReadyImplyGrant_A	442452457	246423	0	0
ReqImpliesValid_A	442452457	1271916	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	246423	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	246423	0	0
T1	548539	424	0	0
T2	156058	165	0	0
T3	579139	15	0	0
T7	14425	24	0	0
T8	153351	125	0	0
T9	21337	0	0	0
T10	3692	7	0	0
T11	3416	16	0	0
T12	541477	454	0	0
T13	55351	193	0	0
T14	0	1029	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	246423	0	0
T1	548539	424	0	0
T2	156058	165	0	0
T3	579139	15	0	0
T7	14425	24	0	0
T8	153351	125	0	0
T9	21337	0	0	0
T10	3692	7	0	0
T11	3416	16	0	0
T12	541477	454	0	0
T13	55351	193	0	0
T14	0	1029	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	246423	0	0
T1	548539	424	0	0
T2	156058	165	0	0
T3	579139	15	0	0
T7	14425	24	0	0
T8	153351	125	0	0
T9	21337	0	0	0
T10	3692	7	0	0
T11	3416	16	0	0
T12	541477	454	0	0
T13	55351	193	0	0
T14	0	1029	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	5800191	0	0
T1	548539	2502	0	0
T2	156058	1867	0	0
T3	579139	11646	0	0
T7	14425	766	0	0
T8	153351	1229	0	0
T9	21337	0	0	0
T10	3692	129	0	0
T11	3416	406	0	0
T12	541477	15737	0	0
T13	55351	747	0	0
T14	0	4704	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	246423	0	0
T1	548539	424	0	0
T2	156058	165	0	0
T3	579139	15	0	0
T7	14425	24	0	0
T8	153351	125	0	0
T9	21337	0	0	0
T10	3692	7	0	0
T11	3416	16	0	0
T12	541477	454	0	0
T13	55351	193	0	0
T14	0	1029	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	246423	0	0
T1	548539	424	0	0
T2	156058	165	0	0
T3	579139	15	0	0
T7	14425	24	0	0
T8	153351	125	0	0
T9	21337	0	0	0
T10	3692	7	0	0
T11	3416	16	0	0
T12	541477	454	0	0
T13	55351	193	0	0
T14	0	1029	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	1271916	0	0
T1	548539	1691	0	0
T2	156058	244	0	0
T3	579139	15	0	0
T7	14425	131	0	0
T8	153351	165	0	0
T9	21337	0	0	0
T10	3692	7	0	0
T11	3416	79	0	0
T12	541477	7429	0	0
T13	55351	206	0	0
T14	0	2718	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	246423	0	0
T1	548539	424	0	0
T2	156058	165	0	0
T3	579139	15	0	0
T7	14425	24	0	0
T8	153351	125	0	0
T9	21337	0	0	0
T10	3692	7	0	0
T11	3416	16	0	0
T12	541477	454	0	0
T13	55351	193	0	0
T14	0	1029	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	248368	0	0
GntImpliesValid_A	442452457	248368	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	248368	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	5281328	0	0
ReadyAndValidImplyGrant_A	442452457	248368	0	0
ReqAndReadyImplyGrant_A	442452457	248368	0	0
ReqImpliesValid_A	442452457	1137007	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	248368	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	248368	0	0
T1	548539	1446	0	0
T2	156058	156	0	0
T3	579139	19	0	0
T7	14425	23	0	0
T8	153351	136	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	187	0	0
T14	0	2231	0	0
T16	0	81	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	248368	0	0
T1	548539	1446	0	0
T2	156058	156	0	0
T3	579139	19	0	0
T7	14425	23	0	0
T8	153351	136	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	187	0	0
T14	0	2231	0	0
T16	0	81	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	248368	0	0
T1	548539	1446	0	0
T2	156058	156	0	0
T3	579139	19	0	0
T7	14425	23	0	0
T8	153351	136	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	187	0	0
T14	0	2231	0	0
T16	0	81	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	5281328	0	0
T1	548539	8296	0	0
T2	156058	5234	0	0
T3	579139	23779	0	0
T7	14425	461	0	0
T8	153351	663	0	0
T9	21337	0	0	0
T10	3692	34	0	0
T11	3416	120	0	0
T12	541477	0	0	0
T13	55351	746	0	0
T14	0	5714	0	0
T16	0	801	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	248368	0	0
T1	548539	1446	0	0
T2	156058	156	0	0
T3	579139	19	0	0
T7	14425	23	0	0
T8	153351	136	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	187	0	0
T14	0	2231	0	0
T16	0	81	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	248368	0	0
T1	548539	1446	0	0
T2	156058	156	0	0
T3	579139	19	0	0
T7	14425	23	0	0
T8	153351	136	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	187	0	0
T14	0	2231	0	0
T16	0	81	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	1137007	0	0
T1	548539	5192	0	0
T2	156058	535	0	0
T3	579139	1519	0	0
T7	14425	23	0	0
T8	153351	173	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	24	0	0
T12	541477	0	0	0
T13	55351	230	0	0
T14	0	11968	0	0
T16	0	88	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	248368	0	0
T1	548539	1446	0	0
T2	156058	156	0	0
T3	579139	19	0	0
T7	14425	23	0	0
T8	153351	136	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	187	0	0
T14	0	2231	0	0
T16	0	81	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	235954	0	0
GntImpliesValid_A	442452457	235954	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	235954	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	6261361	0	0
ReadyAndValidImplyGrant_A	442452457	235954	0	0
ReqAndReadyImplyGrant_A	442452457	235954	0	0
ReqImpliesValid_A	442452457	1267078	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	235954	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	235954	0	0
T2	156058	162	0	0
T3	579139	13	0	0
T7	14425	21	0	0
T8	153351	142	0	0
T9	21337	436	0	0
T10	3692	5	0	0
T11	3416	13	0	0
T12	541477	0	0	0
T13	55351	182	0	0
T14	93068	647	0	0
T15	0	446	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	235954	0	0
T2	156058	162	0	0
T3	579139	13	0	0
T7	14425	21	0	0
T8	153351	142	0	0
T9	21337	436	0	0
T10	3692	5	0	0
T11	3416	13	0	0
T12	541477	0	0	0
T13	55351	182	0	0
T14	93068	647	0	0
T15	0	446	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	235954	0	0
T2	156058	162	0	0
T3	579139	13	0	0
T7	14425	21	0	0
T8	153351	142	0	0
T9	21337	436	0	0
T10	3692	5	0	0
T11	3416	13	0	0
T12	541477	0	0	0
T13	55351	182	0	0
T14	93068	647	0	0
T15	0	446	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	6261361	0	0
T2	156058	2420	0	0
T3	579139	3873	0	0
T7	14425	272	0	0
T8	153351	601	0	0
T9	21337	1014	0	0
T10	3692	87	0	0
T11	3416	351	0	0
T12	541477	0	0	0
T13	55351	1044	0	0
T14	93068	5571	0	0
T15	0	2824	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	235954	0	0
T2	156058	162	0	0
T3	579139	13	0	0
T7	14425	21	0	0
T8	153351	142	0	0
T9	21337	436	0	0
T10	3692	5	0	0
T11	3416	13	0	0
T12	541477	0	0	0
T13	55351	182	0	0
T14	93068	647	0	0
T15	0	446	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	235954	0	0
T2	156058	162	0	0
T3	579139	13	0	0
T7	14425	21	0	0
T8	153351	142	0	0
T9	21337	436	0	0
T10	3692	5	0	0
T11	3416	13	0	0
T12	541477	0	0	0
T13	55351	182	0	0
T14	93068	647	0	0
T15	0	446	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	1267078	0	0
T2	156058	341	0	0
T3	579139	13	0	0
T7	14425	30	0	0
T8	153351	179	0	0
T9	21337	2460	0	0
T10	3692	20	0	0
T11	3416	13	0	0
T12	541477	0	0	0
T13	55351	223	0	0
T14	93068	1004	0	0
T15	0	1696	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	235954	0	0
T2	156058	162	0	0
T3	579139	13	0	0
T7	14425	21	0	0
T8	153351	142	0	0
T9	21337	436	0	0
T10	3692	5	0	0
T11	3416	13	0	0
T12	541477	0	0	0
T13	55351	182	0	0
T14	93068	647	0	0
T15	0	446	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	237989	0	0
GntImpliesValid_A	442452457	237989	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	237989	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	6410987	0	0
ReadyAndValidImplyGrant_A	442452457	237989	0	0
ReqAndReadyImplyGrant_A	442452457	237989	0	0
ReqImpliesValid_A	442452457	1305486	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	237989	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	237989	0	0
T1	548539	1030	0	0
T2	156058	157	0	0
T3	579139	12	0	0
T7	14425	30	0	0
T8	153351	138	0	0
T9	21337	0	0	0
T10	3692	6	0	0
T11	3416	12	0	0
T12	541477	418	0	0
T13	55351	201	0	0
T14	0	1996	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	237989	0	0
T1	548539	1030	0	0
T2	156058	157	0	0
T3	579139	12	0	0
T7	14425	30	0	0
T8	153351	138	0	0
T9	21337	0	0	0
T10	3692	6	0	0
T11	3416	12	0	0
T12	541477	418	0	0
T13	55351	201	0	0
T14	0	1996	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	237989	0	0
T1	548539	1030	0	0
T2	156058	157	0	0
T3	579139	12	0	0
T7	14425	30	0	0
T8	153351	138	0	0
T9	21337	0	0	0
T10	3692	6	0	0
T11	3416	12	0	0
T12	541477	418	0	0
T13	55351	201	0	0
T14	0	1996	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	6410987	0	0
T1	548539	14623	0	0
T2	156058	1218	0	0
T3	579139	5664	0	0
T7	14425	541	0	0
T8	153351	727	0	0
T9	21337	0	0	0
T10	3692	88	0	0
T11	3416	80	0	0
T12	541477	2333	0	0
T13	55351	1053	0	0
T14	0	6461	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	237989	0	0
T1	548539	1030	0	0
T2	156058	157	0	0
T3	579139	12	0	0
T7	14425	30	0	0
T8	153351	138	0	0
T9	21337	0	0	0
T10	3692	6	0	0
T11	3416	12	0	0
T12	541477	418	0	0
T13	55351	201	0	0
T14	0	1996	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	237989	0	0
T1	548539	1030	0	0
T2	156058	157	0	0
T3	579139	12	0	0
T7	14425	30	0	0
T8	153351	138	0	0
T9	21337	0	0	0
T10	3692	6	0	0
T11	3416	12	0	0
T12	541477	418	0	0
T13	55351	201	0	0
T14	0	1996	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	1305486	0	0
T1	548539	6822	0	0
T2	156058	247	0	0
T3	579139	12	0	0
T7	14425	126	0	0
T8	153351	167	0	0
T9	21337	0	0	0
T10	3692	6	0	0
T11	3416	12	0	0
T12	541477	1522	0	0
T13	55351	275	0	0
T14	0	6496	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	237989	0	0
T1	548539	1030	0	0
T2	156058	157	0	0
T3	579139	12	0	0
T7	14425	30	0	0
T8	153351	138	0	0
T9	21337	0	0	0
T10	3692	6	0	0
T11	3416	12	0	0
T12	541477	418	0	0
T13	55351	201	0	0
T14	0	1996	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	254976	0	0
GntImpliesValid_A	442452457	254976	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	254976	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	3381314	0	0
ReadyAndValidImplyGrant_A	442452457	254976	0	0
ReqAndReadyImplyGrant_A	442452457	254976	0	0
ReqImpliesValid_A	442452457	666454	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	254976	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	254976	0	0
T2	156058	167	0	0
T3	579139	7	0	0
T7	14425	21	0	0
T8	153351	134	0	0
T9	21337	0	0	0
T10	3692	10	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	205	0	0
T14	93068	1518	0	0
T16	0	65	0	0
T17	0	33	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	254976	0	0
T2	156058	167	0	0
T3	579139	7	0	0
T7	14425	21	0	0
T8	153351	134	0	0
T9	21337	0	0	0
T10	3692	10	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	205	0	0
T14	93068	1518	0	0
T16	0	65	0	0
T17	0	33	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	254976	0	0
T2	156058	167	0	0
T3	579139	7	0	0
T7	14425	21	0	0
T8	153351	134	0	0
T9	21337	0	0	0
T10	3692	10	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	205	0	0
T14	93068	1518	0	0
T16	0	65	0	0
T17	0	33	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3381314	0	0
T1	548539	1	0	0
T2	156058	722	0	0
T3	579139	2496	0	0
T7	14425	174	0	0
T8	153351	562	0	0
T9	21337	1	0	0
T10	3692	96	0	0
T11	3416	18	0	0
T12	541477	1	0	0
T13	55351	1488	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	254976	0	0
T2	156058	167	0	0
T3	579139	7	0	0
T7	14425	21	0	0
T8	153351	134	0	0
T9	21337	0	0	0
T10	3692	10	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	205	0	0
T14	93068	1518	0	0
T16	0	65	0	0
T17	0	33	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	254976	0	0
T2	156058	167	0	0
T3	579139	7	0	0
T7	14425	21	0	0
T8	153351	134	0	0
T9	21337	0	0	0
T10	3692	10	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	205	0	0
T14	93068	1518	0	0
T16	0	65	0	0
T17	0	33	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	666454	0	0
T2	156058	203	0	0
T3	579139	7	0	0
T7	14425	36	0	0
T8	153351	152	0	0
T9	21337	0	0	0
T10	3692	16	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	288	0	0
T14	93068	1697	0	0
T16	0	72	0	0
T17	0	42	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	254976	0	0
T2	156058	167	0	0
T3	579139	7	0	0
T7	14425	21	0	0
T8	153351	134	0	0
T9	21337	0	0	0
T10	3692	10	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	205	0	0
T14	93068	1518	0	0
T16	0	65	0	0
T17	0	33	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	244570	0	0
GntImpliesValid_A	442452457	244570	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	244570	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	3335260	0	0
ReadyAndValidImplyGrant_A	442452457	244570	0	0
ReqAndReadyImplyGrant_A	442452457	244570	0	0
ReqImpliesValid_A	442452457	642835	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	244570	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	244570	0	0
T2	156058	171	0	0
T3	579139	17	0	0
T7	14425	29	0	0
T8	153351	153	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	21	0	0
T12	541477	429	0	0
T13	55351	218	0	0
T14	93068	1558	0	0
T15	0	518	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	244570	0	0
T2	156058	171	0	0
T3	579139	17	0	0
T7	14425	29	0	0
T8	153351	153	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	21	0	0
T12	541477	429	0	0
T13	55351	218	0	0
T14	93068	1558	0	0
T15	0	518	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	244570	0	0
T2	156058	171	0	0
T3	579139	17	0	0
T7	14425	29	0	0
T8	153351	153	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	21	0	0
T12	541477	429	0	0
T13	55351	218	0	0
T14	93068	1558	0	0
T15	0	518	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3335260	0	0
T1	548539	1	0	0
T2	156058	693	0	0
T3	579139	6367	0	0
T7	14425	187	0	0
T8	153351	657	0	0
T9	21337	1	0	0
T10	3692	41	0	0
T11	3416	22	0	0
T12	541477	1405	0	0
T13	55351	1601	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	244570	0	0
T2	156058	171	0	0
T3	579139	17	0	0
T7	14425	29	0	0
T8	153351	153	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	21	0	0
T12	541477	429	0	0
T13	55351	218	0	0
T14	93068	1558	0	0
T15	0	518	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	244570	0	0
T2	156058	171	0	0
T3	579139	17	0	0
T7	14425	29	0	0
T8	153351	153	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	21	0	0
T12	541477	429	0	0
T13	55351	218	0	0
T14	93068	1558	0	0
T15	0	518	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	642835	0	0
T2	156058	203	0	0
T3	579139	1147	0	0
T7	14425	41	0	0
T8	153351	185	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	21	0	0
T12	541477	1119	0	0
T13	55351	305	0	0
T14	93068	2309	0	0
T15	0	1184	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	244570	0	0
T2	156058	171	0	0
T3	579139	17	0	0
T7	14425	29	0	0
T8	153351	153	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	21	0	0
T12	541477	429	0	0
T13	55351	218	0	0
T14	93068	1558	0	0
T15	0	518	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	255222	0	0
GntImpliesValid_A	442452457	255222	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	255222	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	3425043	0	0
ReadyAndValidImplyGrant_A	442452457	255222	0	0
ReqAndReadyImplyGrant_A	442452457	255222	0	0
ReqImpliesValid_A	442452457	635274	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	255222	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	255222	0	0
T2	156058	173	0	0
T3	579139	16	0	0
T7	14425	23	0	0
T8	153351	143	0	0
T9	21337	0	0	0
T10	3692	11	0	0
T11	3416	11	0	0
T12	541477	0	0	0
T13	55351	201	0	0
T14	93068	2195	0	0
T15	0	528	0	0
T16	0	558	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	255222	0	0
T2	156058	173	0	0
T3	579139	16	0	0
T7	14425	23	0	0
T8	153351	143	0	0
T9	21337	0	0	0
T10	3692	11	0	0
T11	3416	11	0	0
T12	541477	0	0	0
T13	55351	201	0	0
T14	93068	2195	0	0
T15	0	528	0	0
T16	0	558	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	255222	0	0
T2	156058	173	0	0
T3	579139	16	0	0
T7	14425	23	0	0
T8	153351	143	0	0
T9	21337	0	0	0
T10	3692	11	0	0
T11	3416	11	0	0
T12	541477	0	0	0
T13	55351	201	0	0
T14	93068	2195	0	0
T15	0	528	0	0
T16	0	558	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3425043	0	0
T1	548539	1	0	0
T2	156058	746	0	0
T3	579139	6144	0	0
T7	14425	206	0	0
T8	153351	603	0	0
T9	21337	1	0	0
T10	3692	74	0	0
T11	3416	12	0	0
T12	541477	1	0	0
T13	55351	1538	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	255222	0	0
T2	156058	173	0	0
T3	579139	16	0	0
T7	14425	23	0	0
T8	153351	143	0	0
T9	21337	0	0	0
T10	3692	11	0	0
T11	3416	11	0	0
T12	541477	0	0	0
T13	55351	201	0	0
T14	93068	2195	0	0
T15	0	528	0	0
T16	0	558	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	255222	0	0
T2	156058	173	0	0
T3	579139	16	0	0
T7	14425	23	0	0
T8	153351	143	0	0
T9	21337	0	0	0
T10	3692	11	0	0
T11	3416	11	0	0
T12	541477	0	0	0
T13	55351	201	0	0
T14	93068	2195	0	0
T15	0	528	0	0
T16	0	558	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	635274	0	0
T2	156058	196	0	0
T3	579139	255	0	0
T7	14425	23	0	0
T8	153351	166	0	0
T9	21337	0	0	0
T10	3692	11	0	0
T11	3416	11	0	0
T12	541477	0	0	0
T13	55351	269	0	0
T14	93068	3371	0	0
T15	0	1183	0	0
T16	0	2394	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	255222	0	0
T2	156058	173	0	0
T3	579139	16	0	0
T7	14425	23	0	0
T8	153351	143	0	0
T9	21337	0	0	0
T10	3692	11	0	0
T11	3416	11	0	0
T12	541477	0	0	0
T13	55351	201	0	0
T14	93068	2195	0	0
T15	0	528	0	0
T16	0	558	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	255275	0	0
GntImpliesValid_A	442452457	255275	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	255275	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	3459633	0	0
ReadyAndValidImplyGrant_A	442452457	255275	0	0
ReqAndReadyImplyGrant_A	442452457	255275	0	0
ReqImpliesValid_A	442452457	689092	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	255275	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	255275	0	0
T2	156058	145	0	0
T3	579139	15	0	0
T7	14425	20	0	0
T8	153351	145	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	11	0	0
T12	541477	0	0	0
T13	55351	159	0	0
T14	93068	2131	0	0
T16	0	75	0	0
T17	0	33	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	255275	0	0
T2	156058	145	0	0
T3	579139	15	0	0
T7	14425	20	0	0
T8	153351	145	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	11	0	0
T12	541477	0	0	0
T13	55351	159	0	0
T14	93068	2131	0	0
T16	0	75	0	0
T17	0	33	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	255275	0	0
T2	156058	145	0	0
T3	579139	15	0	0
T7	14425	20	0	0
T8	153351	145	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	11	0	0
T12	541477	0	0	0
T13	55351	159	0	0
T14	93068	2131	0	0
T16	0	75	0	0
T17	0	33	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3459633	0	0
T1	548539	1	0	0
T2	156058	608	0	0
T3	579139	4124	0	0
T7	14425	131	0	0
T8	153351	626	0	0
T9	21337	1	0	0
T10	3692	49	0	0
T11	3416	12	0	0
T12	541477	1	0	0
T13	55351	1109	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	255275	0	0
T2	156058	145	0	0
T3	579139	15	0	0
T7	14425	20	0	0
T8	153351	145	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	11	0	0
T12	541477	0	0	0
T13	55351	159	0	0
T14	93068	2131	0	0
T16	0	75	0	0
T17	0	33	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	255275	0	0
T2	156058	145	0	0
T3	579139	15	0	0
T7	14425	20	0	0
T8	153351	145	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	11	0	0
T12	541477	0	0	0
T13	55351	159	0	0
T14	93068	2131	0	0
T16	0	75	0	0
T17	0	33	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	689092	0	0
T2	156058	167	0	0
T3	579139	68	0	0
T7	14425	26	0	0
T8	153351	169	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	11	0	0
T12	541477	0	0	0
T13	55351	197	0	0
T14	93068	2921	0	0
T16	0	81	0	0
T17	0	33	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	255275	0	0
T2	156058	145	0	0
T3	579139	15	0	0
T7	14425	20	0	0
T8	153351	145	0	0
T9	21337	0	0	0
T10	3692	5	0	0
T11	3416	11	0	0
T12	541477	0	0	0
T13	55351	159	0	0
T14	93068	2131	0	0
T16	0	75	0	0
T17	0	33	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	245454	0	0
GntImpliesValid_A	442452457	245454	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	245454	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	3296639	0	0
ReadyAndValidImplyGrant_A	442452457	245454	0	0
ReqAndReadyImplyGrant_A	442452457	245454	0	0
ReqImpliesValid_A	442452457	608213	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	245454	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	245454	0	0
T1	548539	516	0	0
T2	156058	153	0	0
T3	579139	14	0	0
T7	14425	30	0	0
T8	153351	133	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	21	0	0
T12	541477	484	0	0
T13	55351	180	0	0
T14	0	1584	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	245454	0	0
T1	548539	516	0	0
T2	156058	153	0	0
T3	579139	14	0	0
T7	14425	30	0	0
T8	153351	133	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	21	0	0
T12	541477	484	0	0
T13	55351	180	0	0
T14	0	1584	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	245454	0	0
T1	548539	516	0	0
T2	156058	153	0	0
T3	579139	14	0	0
T7	14425	30	0	0
T8	153351	133	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	21	0	0
T12	541477	484	0	0
T13	55351	180	0	0
T14	0	1584	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3296639	0	0
T1	548539	1773	0	0
T2	156058	652	0	0
T3	579139	5383	0	0
T7	14425	255	0	0
T8	153351	578	0	0
T9	21337	1	0	0
T10	3692	26	0	0
T11	3416	21	0	0
T12	541477	1546	0	0
T13	55351	1311	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	245454	0	0
T1	548539	516	0	0
T2	156058	153	0	0
T3	579139	14	0	0
T7	14425	30	0	0
T8	153351	133	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	21	0	0
T12	541477	484	0	0
T13	55351	180	0	0
T14	0	1584	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	245454	0	0
T1	548539	516	0	0
T2	156058	153	0	0
T3	579139	14	0	0
T7	14425	30	0	0
T8	153351	133	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	21	0	0
T12	541477	484	0	0
T13	55351	180	0	0
T14	0	1584	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	608213	0	0
T1	548539	1218	0	0
T2	156058	185	0	0
T3	579139	14	0	0
T7	14425	38	0	0
T8	153351	156	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	22	0	0
T12	541477	1216	0	0
T13	55351	376	0	0
T14	0	2194	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	245454	0	0
T1	548539	516	0	0
T2	156058	153	0	0
T3	579139	14	0	0
T7	14425	30	0	0
T8	153351	133	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	21	0	0
T12	541477	484	0	0
T13	55351	180	0	0
T14	0	1584	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	249023	0	0
GntImpliesValid_A	442452457	249023	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	249023	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	3353437	0	0
ReadyAndValidImplyGrant_A	442452457	249023	0	0
ReqAndReadyImplyGrant_A	442452457	249023	0	0
ReqImpliesValid_A	442452457	635111	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	249023	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	249023	0	0
T2	156058	196	0	0
T3	579139	16	0	0
T7	14425	24	0	0
T8	153351	154	0	0
T9	21337	493	0	0
T10	3692	8	0	0
T11	3416	11	0	0
T12	541477	546	0	0
T13	55351	173	0	0
T14	93068	1603	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	249023	0	0
T2	156058	196	0	0
T3	579139	16	0	0
T7	14425	24	0	0
T8	153351	154	0	0
T9	21337	493	0	0
T10	3692	8	0	0
T11	3416	11	0	0
T12	541477	546	0	0
T13	55351	173	0	0
T14	93068	1603	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	249023	0	0
T2	156058	196	0	0
T3	579139	16	0	0
T7	14425	24	0	0
T8	153351	154	0	0
T9	21337	493	0	0
T10	3692	8	0	0
T11	3416	11	0	0
T12	541477	546	0	0
T13	55351	173	0	0
T14	93068	1603	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3353437	0	0
T1	548539	1	0	0
T2	156058	809	0	0
T3	579139	4523	0	0
T7	14425	190	0	0
T8	153351	626	0	0
T9	21337	1054	0	0
T10	3692	51	0	0
T11	3416	11	0	0
T12	541477	1815	0	0
T13	55351	1236	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	249023	0	0
T2	156058	196	0	0
T3	579139	16	0	0
T7	14425	24	0	0
T8	153351	154	0	0
T9	21337	493	0	0
T10	3692	8	0	0
T11	3416	11	0	0
T12	541477	546	0	0
T13	55351	173	0	0
T14	93068	1603	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	249023	0	0
T2	156058	196	0	0
T3	579139	16	0	0
T7	14425	24	0	0
T8	153351	154	0	0
T9	21337	493	0	0
T10	3692	8	0	0
T11	3416	11	0	0
T12	541477	546	0	0
T13	55351	173	0	0
T14	93068	1603	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	635111	0	0
T2	156058	257	0	0
T3	579139	16	0	0
T7	14425	24	0	0
T8	153351	193	0	0
T9	21337	1816	0	0
T10	3692	8	0	0
T11	3416	12	0	0
T12	541477	1174	0	0
T13	55351	268	0	0
T14	93068	2363	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	249023	0	0
T2	156058	196	0	0
T3	579139	16	0	0
T7	14425	24	0	0
T8	153351	154	0	0
T9	21337	493	0	0
T10	3692	8	0	0
T11	3416	11	0	0
T12	541477	546	0	0
T13	55351	173	0	0
T14	93068	1603	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	259183	0	0
GntImpliesValid_A	442452457	259183	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	259183	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	3458380	0	0
ReadyAndValidImplyGrant_A	442452457	259183	0	0
ReqAndReadyImplyGrant_A	442452457	259183	0	0
ReqImpliesValid_A	442452457	681347	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	259183	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	259183	0	0
T2	156058	156	0	0
T3	579139	10	0	0
T7	14425	18	0	0
T8	153351	141	0	0
T9	21337	0	0	0
T10	3692	10	0	0
T11	3416	9	0	0
T12	541477	1412	0	0
T13	55351	178	0	0
T14	93068	1100	0	0
T16	0	216	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	259183	0	0
T2	156058	156	0	0
T3	579139	10	0	0
T7	14425	18	0	0
T8	153351	141	0	0
T9	21337	0	0	0
T10	3692	10	0	0
T11	3416	9	0	0
T12	541477	1412	0	0
T13	55351	178	0	0
T14	93068	1100	0	0
T16	0	216	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	259183	0	0
T2	156058	156	0	0
T3	579139	10	0	0
T7	14425	18	0	0
T8	153351	141	0	0
T9	21337	0	0	0
T10	3692	10	0	0
T11	3416	9	0	0
T12	541477	1412	0	0
T13	55351	178	0	0
T14	93068	1100	0	0
T16	0	216	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3458380	0	0
T1	548539	1	0	0
T2	156058	620	0	0
T3	579139	3563	0	0
T7	14425	118	0	0
T8	153351	611	0	0
T9	21337	1	0	0
T10	3692	87	0	0
T11	3416	9	0	0
T12	541477	4542	0	0
T13	55351	1209	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	259183	0	0
T2	156058	156	0	0
T3	579139	10	0	0
T7	14425	18	0	0
T8	153351	141	0	0
T9	21337	0	0	0
T10	3692	10	0	0
T11	3416	9	0	0
T12	541477	1412	0	0
T13	55351	178	0	0
T14	93068	1100	0	0
T16	0	216	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	259183	0	0
T2	156058	156	0	0
T3	579139	10	0	0
T7	14425	18	0	0
T8	153351	141	0	0
T9	21337	0	0	0
T10	3692	10	0	0
T11	3416	9	0	0
T12	541477	1412	0	0
T13	55351	178	0	0
T14	93068	1100	0	0
T16	0	216	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	681347	0	0
T2	156058	201	0	0
T3	579139	10	0	0
T7	14425	29	0	0
T8	153351	174	0	0
T9	21337	0	0	0
T10	3692	16	0	0
T11	3416	10	0	0
T12	541477	3375	0	0
T13	55351	286	0	0
T14	93068	1628	0	0
T16	0	456	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	259183	0	0
T2	156058	156	0	0
T3	579139	10	0	0
T7	14425	18	0	0
T8	153351	141	0	0
T9	21337	0	0	0
T10	3692	10	0	0
T11	3416	9	0	0
T12	541477	1412	0	0
T13	55351	178	0	0
T14	93068	1100	0	0
T16	0	216	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	256368	0	0
GntImpliesValid_A	442452457	256368	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	256368	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	3410756	0	0
ReadyAndValidImplyGrant_A	442452457	256368	0	0
ReqAndReadyImplyGrant_A	442452457	256368	0	0
ReqImpliesValid_A	442452457	659047	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	256368	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	256368	0	0
T2	156058	158	0	0
T3	579139	10	0	0
T7	14425	26	0	0
T8	153351	132	0	0
T9	21337	0	0	0
T10	3692	9	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	184	0	0
T14	93068	2109	0	0
T15	0	898	0	0
T16	0	125	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	256368	0	0
T2	156058	158	0	0
T3	579139	10	0	0
T7	14425	26	0	0
T8	153351	132	0	0
T9	21337	0	0	0
T10	3692	9	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	184	0	0
T14	93068	2109	0	0
T15	0	898	0	0
T16	0	125	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	256368	0	0
T2	156058	158	0	0
T3	579139	10	0	0
T7	14425	26	0	0
T8	153351	132	0	0
T9	21337	0	0	0
T10	3692	9	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	184	0	0
T14	93068	2109	0	0
T15	0	898	0	0
T16	0	125	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3410756	0	0
T1	548539	1	0	0
T2	156058	681	0	0
T3	579139	3369	0	0
T7	14425	210	0	0
T8	153351	551	0	0
T9	21337	1	0	0
T10	3692	91	0	0
T11	3416	17	0	0
T12	541477	1	0	0
T13	55351	1487	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	256368	0	0
T2	156058	158	0	0
T3	579139	10	0	0
T7	14425	26	0	0
T8	153351	132	0	0
T9	21337	0	0	0
T10	3692	9	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	184	0	0
T14	93068	2109	0	0
T15	0	898	0	0
T16	0	125	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	256368	0	0
T2	156058	158	0	0
T3	579139	10	0	0
T7	14425	26	0	0
T8	153351	132	0	0
T9	21337	0	0	0
T10	3692	9	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	184	0	0
T14	93068	2109	0	0
T15	0	898	0	0
T16	0	125	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	659047	0	0
T2	156058	179	0	0
T3	579139	10	0	0
T7	14425	38	0	0
T8	153351	158	0	0
T9	21337	0	0	0
T10	3692	9	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	233	0	0
T14	93068	2811	0	0
T15	0	2289	0	0
T16	0	249	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	256368	0	0
T2	156058	158	0	0
T3	579139	10	0	0
T7	14425	26	0	0
T8	153351	132	0	0
T9	21337	0	0	0
T10	3692	9	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	184	0	0
T14	93068	2109	0	0
T15	0	898	0	0
T16	0	125	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	269170	0	0
GntImpliesValid_A	442452457	269170	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	269170	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	3449650	0	0
ReadyAndValidImplyGrant_A	442452457	269170	0	0
ReqAndReadyImplyGrant_A	442452457	269170	0	0
ReqImpliesValid_A	442452457	682152	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	269170	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	269170	0	0
T2	156058	167	0	0
T3	579139	12	0	0
T7	14425	44	0	0
T8	153351	129	0	0
T9	21337	0	0	0
T10	3692	14	0	0
T11	3416	13	0	0
T12	541477	559	0	0
T13	55351	198	0	0
T14	93068	654	0	0
T15	0	1079	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	269170	0	0
T2	156058	167	0	0
T3	579139	12	0	0
T7	14425	44	0	0
T8	153351	129	0	0
T9	21337	0	0	0
T10	3692	14	0	0
T11	3416	13	0	0
T12	541477	559	0	0
T13	55351	198	0	0
T14	93068	654	0	0
T15	0	1079	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	269170	0	0
T2	156058	167	0	0
T3	579139	12	0	0
T7	14425	44	0	0
T8	153351	129	0	0
T9	21337	0	0	0
T10	3692	14	0	0
T11	3416	13	0	0
T12	541477	559	0	0
T13	55351	198	0	0
T14	93068	654	0	0
T15	0	1079	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3449650	0	0
T1	548539	1	0	0
T2	156058	681	0	0
T3	579139	4649	0	0
T7	14425	281	0	0
T8	153351	541	0	0
T9	21337	1	0	0
T10	3692	131	0	0
T11	3416	14	0	0
T12	541477	1864	0	0
T13	55351	1358	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	269170	0	0
T2	156058	167	0	0
T3	579139	12	0	0
T7	14425	44	0	0
T8	153351	129	0	0
T9	21337	0	0	0
T10	3692	14	0	0
T11	3416	13	0	0
T12	541477	559	0	0
T13	55351	198	0	0
T14	93068	654	0	0
T15	0	1079	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	269170	0	0
T2	156058	167	0	0
T3	579139	12	0	0
T7	14425	44	0	0
T8	153351	129	0	0
T9	21337	0	0	0
T10	3692	14	0	0
T11	3416	13	0	0
T12	541477	559	0	0
T13	55351	198	0	0
T14	93068	654	0	0
T15	0	1079	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	682152	0	0
T2	156058	187	0	0
T3	579139	775	0	0
T7	14425	61	0	0
T8	153351	146	0	0
T9	21337	0	0	0
T10	3692	26	0	0
T11	3416	13	0	0
T12	541477	1252	0	0
T13	55351	303	0	0
T14	93068	671	0	0
T15	0	2503	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	269170	0	0
T2	156058	167	0	0
T3	579139	12	0	0
T7	14425	44	0	0
T8	153351	129	0	0
T9	21337	0	0	0
T10	3692	14	0	0
T11	3416	13	0	0
T12	541477	559	0	0
T13	55351	198	0	0
T14	93068	654	0	0
T15	0	1079	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	248070	0	0
GntImpliesValid_A	442452457	248070	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	248070	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	3414081	0	0
ReadyAndValidImplyGrant_A	442452457	248070	0	0
ReqAndReadyImplyGrant_A	442452457	248070	0	0
ReqImpliesValid_A	442452457	619102	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	248070	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	248070	0	0
T2	156058	157	0	0
T3	579139	15	0	0
T7	14425	22	0	0
T8	153351	142	0	0
T9	21337	478	0	0
T10	3692	8	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	189	0	0
T14	93068	2596	0	0
T15	0	443	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	248070	0	0
T2	156058	157	0	0
T3	579139	15	0	0
T7	14425	22	0	0
T8	153351	142	0	0
T9	21337	478	0	0
T10	3692	8	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	189	0	0
T14	93068	2596	0	0
T15	0	443	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	248070	0	0
T2	156058	157	0	0
T3	579139	15	0	0
T7	14425	22	0	0
T8	153351	142	0	0
T9	21337	478	0	0
T10	3692	8	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	189	0	0
T14	93068	2596	0	0
T15	0	443	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3414081	0	0
T1	548539	1	0	0
T2	156058	686	0	0
T3	579139	6818	0	0
T7	14425	180	0	0
T8	153351	622	0	0
T9	21337	1209	0	0
T10	3692	69	0	0
T11	3416	18	0	0
T12	541477	1	0	0
T13	55351	1504	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	248070	0	0
T2	156058	157	0	0
T3	579139	15	0	0
T7	14425	22	0	0
T8	153351	142	0	0
T9	21337	478	0	0
T10	3692	8	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	189	0	0
T14	93068	2596	0	0
T15	0	443	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	248070	0	0
T2	156058	157	0	0
T3	579139	15	0	0
T7	14425	22	0	0
T8	153351	142	0	0
T9	21337	478	0	0
T10	3692	8	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	189	0	0
T14	93068	2596	0	0
T15	0	443	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	619102	0	0
T2	156058	206	0	0
T3	579139	220	0	0
T7	14425	44	0	0
T8	153351	175	0	0
T9	21337	4074	0	0
T10	3692	8	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	320	0	0
T14	93068	4050	0	0
T15	0	1132	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	248070	0	0
T2	156058	157	0	0
T3	579139	15	0	0
T7	14425	22	0	0
T8	153351	142	0	0
T9	21337	478	0	0
T10	3692	8	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	189	0	0
T14	93068	2596	0	0
T15	0	443	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	251684	0	0
GntImpliesValid_A	442452457	251684	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	251684	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	3315352	0	0
ReadyAndValidImplyGrant_A	442452457	251684	0	0
ReqAndReadyImplyGrant_A	442452457	251684	0	0
ReqImpliesValid_A	442452457	644179	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	251684	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	251684	0	0
T1	548539	481	0	0
T2	156058	160	0	0
T3	579139	20	0	0
T7	14425	25	0	0
T8	153351	143	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	202	0	0
T14	0	616	0	0
T15	0	422	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	251684	0	0
T1	548539	481	0	0
T2	156058	160	0	0
T3	579139	20	0	0
T7	14425	25	0	0
T8	153351	143	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	202	0	0
T14	0	616	0	0
T15	0	422	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	251684	0	0
T1	548539	481	0	0
T2	156058	160	0	0
T3	579139	20	0	0
T7	14425	25	0	0
T8	153351	143	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	202	0	0
T14	0	616	0	0
T15	0	422	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3315352	0	0
T1	548539	1372	0	0
T2	156058	724	0	0
T3	579139	7446	0	0
T7	14425	212	0	0
T8	153351	622	0	0
T9	21337	1	0	0
T10	3692	31	0	0
T11	3416	17	0	0
T12	541477	1	0	0
T13	55351	1397	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	251684	0	0
T1	548539	481	0	0
T2	156058	160	0	0
T3	579139	20	0	0
T7	14425	25	0	0
T8	153351	143	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	202	0	0
T14	0	616	0	0
T15	0	422	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	251684	0	0
T1	548539	481	0	0
T2	156058	160	0	0
T3	579139	20	0	0
T7	14425	25	0	0
T8	153351	143	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	202	0	0
T14	0	616	0	0
T15	0	422	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	644179	0	0
T1	548539	1309	0	0
T2	156058	188	0	0
T3	579139	1075	0	0
T7	14425	39	0	0
T8	153351	155	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	286	0	0
T14	0	628	0	0
T15	0	1111	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	251684	0	0
T1	548539	481	0	0
T2	156058	160	0	0
T3	579139	20	0	0
T7	14425	25	0	0
T8	153351	143	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	202	0	0
T14	0	616	0	0
T15	0	422	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	249622	0	0
GntImpliesValid_A	442452457	249622	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	249622	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	3380421	0	0
ReadyAndValidImplyGrant_A	442452457	249622	0	0
ReqAndReadyImplyGrant_A	442452457	249622	0	0
ReqImpliesValid_A	442452457	678983	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	249622	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	249622	0	0
T2	156058	162	0	0
T3	579139	13	0	0
T7	14425	26	0	0
T8	153351	146	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	187	0	0
T14	93068	1098	0	0
T16	0	67	0	0
T17	0	36	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	249622	0	0
T2	156058	162	0	0
T3	579139	13	0	0
T7	14425	26	0	0
T8	153351	146	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	187	0	0
T14	93068	1098	0	0
T16	0	67	0	0
T17	0	36	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	249622	0	0
T2	156058	162	0	0
T3	579139	13	0	0
T7	14425	26	0	0
T8	153351	146	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	187	0	0
T14	93068	1098	0	0
T16	0	67	0	0
T17	0	36	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3380421	0	0
T1	548539	1	0	0
T2	156058	727	0	0
T3	579139	5209	0	0
T7	14425	205	0	0
T8	153351	618	0	0
T9	21337	1	0	0
T10	3692	31	0	0
T11	3416	17	0	0
T12	541477	1	0	0
T13	55351	1242	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	249622	0	0
T2	156058	162	0	0
T3	579139	13	0	0
T7	14425	26	0	0
T8	153351	146	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	187	0	0
T14	93068	1098	0	0
T16	0	67	0	0
T17	0	36	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	249622	0	0
T2	156058	162	0	0
T3	579139	13	0	0
T7	14425	26	0	0
T8	153351	146	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	187	0	0
T14	93068	1098	0	0
T16	0	67	0	0
T17	0	36	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	678983	0	0
T2	156058	181	0	0
T3	579139	477	0	0
T7	14425	30	0	0
T8	153351	176	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	296	0	0
T14	93068	1181	0	0
T16	0	67	0	0
T17	0	48	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	249622	0	0
T2	156058	162	0	0
T3	579139	13	0	0
T7	14425	26	0	0
T8	153351	146	0	0
T9	21337	0	0	0
T10	3692	4	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	187	0	0
T14	93068	1098	0	0
T16	0	67	0	0
T17	0	36	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	244649	0	0
GntImpliesValid_A	442452457	244649	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	244649	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	3357242	0	0
ReadyAndValidImplyGrant_A	442452457	244649	0	0
ReqAndReadyImplyGrant_A	442452457	244649	0	0
ReqImpliesValid_A	442452457	612160	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	244649	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	244649	0	0
T1	548539	544	0	0
T2	156058	172	0	0
T3	579139	18	0	0
T7	14425	30	0	0
T8	153351	149	0	0
T9	21337	0	0	0
T10	3692	9	0	0
T11	3416	18	0	0
T12	541477	0	0	0
T13	55351	187	0	0
T14	0	1113	0	0
T15	0	475	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	244649	0	0
T1	548539	544	0	0
T2	156058	172	0	0
T3	579139	18	0	0
T7	14425	30	0	0
T8	153351	149	0	0
T9	21337	0	0	0
T10	3692	9	0	0
T11	3416	18	0	0
T12	541477	0	0	0
T13	55351	187	0	0
T14	0	1113	0	0
T15	0	475	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	244649	0	0
T1	548539	544	0	0
T2	156058	172	0	0
T3	579139	18	0	0
T7	14425	30	0	0
T8	153351	149	0	0
T9	21337	0	0	0
T10	3692	9	0	0
T11	3416	18	0	0
T12	541477	0	0	0
T13	55351	187	0	0
T14	0	1113	0	0
T15	0	475	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3357242	0	0
T1	548539	1723	0	0
T2	156058	702	0	0
T3	579139	3703	0	0
T7	14425	232	0	0
T8	153351	630	0	0
T9	21337	1	0	0
T10	3692	69	0	0
T11	3416	17	0	0
T12	541477	1	0	0
T13	55351	1439	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	244649	0	0
T1	548539	544	0	0
T2	156058	172	0	0
T3	579139	18	0	0
T7	14425	30	0	0
T8	153351	149	0	0
T9	21337	0	0	0
T10	3692	9	0	0
T11	3416	18	0	0
T12	541477	0	0	0
T13	55351	187	0	0
T14	0	1113	0	0
T15	0	475	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	244649	0	0
T1	548539	544	0	0
T2	156058	172	0	0
T3	579139	18	0	0
T7	14425	30	0	0
T8	153351	149	0	0
T9	21337	0	0	0
T10	3692	9	0	0
T11	3416	18	0	0
T12	541477	0	0	0
T13	55351	187	0	0
T14	0	1113	0	0
T15	0	475	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	612160	0	0
T1	548539	1238	0	0
T2	156058	197	0	0
T3	579139	18	0	0
T7	14425	43	0	0
T8	153351	179	0	0
T9	21337	0	0	0
T10	3692	16	0	0
T11	3416	20	0	0
T12	541477	0	0	0
T13	55351	243	0	0
T14	0	1188	0	0
T15	0	1128	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	244649	0	0
T1	548539	544	0	0
T2	156058	172	0	0
T3	579139	18	0	0
T7	14425	30	0	0
T8	153351	149	0	0
T9	21337	0	0	0
T10	3692	9	0	0
T11	3416	18	0	0
T12	541477	0	0	0
T13	55351	187	0	0
T14	0	1113	0	0
T15	0	475	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	260602	0	0
GntImpliesValid_A	442452457	260602	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	260602	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	3387018	0	0
ReadyAndValidImplyGrant_A	442452457	260602	0	0
ReqAndReadyImplyGrant_A	442452457	260602	0	0
ReqImpliesValid_A	442452457	702187	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	0	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	260602	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	260602	0	0
T1	548539	435	0	0
T2	156058	173	0	0
T3	579139	19	0	0
T7	14425	22	0	0
T8	153351	149	0	0
T9	21337	0	0	0
T10	3692	14	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	179	0	0
T14	0	1121	0	0
T16	0	75	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	260602	0	0
T1	548539	435	0	0
T2	156058	173	0	0
T3	579139	19	0	0
T7	14425	22	0	0
T8	153351	149	0	0
T9	21337	0	0	0
T10	3692	14	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	179	0	0
T14	0	1121	0	0
T16	0	75	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	260602	0	0
T1	548539	435	0	0
T2	156058	173	0	0
T3	579139	19	0	0
T7	14425	22	0	0
T8	153351	149	0	0
T9	21337	0	0	0
T10	3692	14	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	179	0	0
T14	0	1121	0	0
T16	0	75	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	3387018	0	0
T1	548539	1434	0	0
T2	156058	737	0	0
T3	579139	5470	0	0
T7	14425	158	0	0
T8	153351	687	0	0
T9	21337	1	0	0
T10	3692	80	0	0
T11	3416	16	0	0
T12	541477	1	0	0
T13	55351	1432	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	260602	0	0
T1	548539	435	0	0
T2	156058	173	0	0
T3	579139	19	0	0
T7	14425	22	0	0
T8	153351	149	0	0
T9	21337	0	0	0
T10	3692	14	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	179	0	0
T14	0	1121	0	0
T16	0	75	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	260602	0	0
T1	548539	435	0	0
T2	156058	173	0	0
T3	579139	19	0	0
T7	14425	22	0	0
T8	153351	149	0	0
T9	21337	0	0	0
T10	3692	14	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	179	0	0
T14	0	1121	0	0
T16	0	75	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	702187	0	0
T1	548539	1070	0	0
T2	156058	211	0	0
T3	579139	19	0	0
T7	14425	24	0	0
T8	153351	155	0	0
T9	21337	0	0	0
T10	3692	23	0	0
T11	3416	17	0	0
T12	541477	0	0	0
T13	55351	294	0	0
T14	0	1613	0	0
T16	0	92	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	260602	0	0
T1	548539	435	0	0
T2	156058	173	0	0
T3	579139	19	0	0
T7	14425	22	0	0
T8	153351	149	0	0
T9	21337	0	0	0
T10	3692	14	0	0
T11	3416	16	0	0
T12	541477	0	0	0
T13	55351	179	0	0
T14	0	1121	0	0
T16	0	75	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	1005867	0	0
GntImpliesValid_A	442452457	1005867	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	1005867	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	12867553	0	0
ReadyAndValidImplyGrant_A	442452457	1005867	0	0
ReqAndReadyImplyGrant_A	442452457	1005867	0	0
ReqImpliesValid_A	442452457	2732997	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	23024	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	1005867	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	1005867	0	0
T1	548539	1417	0	0
T2	156058	658	0	0
T3	579139	49	0	0
T7	14425	110	0	0
T8	153351	623	0	0
T9	21337	211	0	0
T10	3692	34	0	0
T11	3416	69	0	0
T12	541477	1275	0	0
T13	55351	736	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	1005867	0	0
T1	548539	1417	0	0
T2	156058	658	0	0
T3	579139	49	0	0
T7	14425	110	0	0
T8	153351	623	0	0
T9	21337	211	0	0
T10	3692	34	0	0
T11	3416	69	0	0
T12	541477	1275	0	0
T13	55351	736	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	1005867	0	0
T1	548539	1417	0	0
T2	156058	658	0	0
T3	579139	49	0	0
T7	14425	110	0	0
T8	153351	623	0	0
T9	21337	211	0	0
T10	3692	34	0	0
T11	3416	69	0	0
T12	541477	1275	0	0
T13	55351	736	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	12867553	0	0
T1	548539	4131	0	0
T2	156058	2146	0	0
T3	579139	15787	0	0
T7	14425	798	0	0
T8	153351	2083	0	0
T9	21337	1373	0	0
T10	3692	269	0	0
T11	3416	1	0	0
T12	541477	3600	0	0
T13	55351	3929	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	1005867	0	0
T1	548539	1417	0	0
T2	156058	658	0	0
T3	579139	49	0	0
T7	14425	110	0	0
T8	153351	623	0	0
T9	21337	211	0	0
T10	3692	34	0	0
T11	3416	69	0	0
T12	541477	1275	0	0
T13	55351	736	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	1005867	0	0
T1	548539	1417	0	0
T2	156058	658	0	0
T3	579139	49	0	0
T7	14425	110	0	0
T8	153351	623	0	0
T9	21337	211	0	0
T10	3692	34	0	0
T11	3416	69	0	0
T12	541477	1275	0	0
T13	55351	736	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	2732997	0	0
T1	548539	2677	0	0
T2	156058	861	0	0
T3	579139	448	0	0
T7	14425	126	0	0
T8	153351	840	0	0
T9	21337	341	0	0
T10	3692	36	0	0
T11	3416	69	0	0
T12	541477	2362	0	0
T13	55351	1393	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	23024	0	900
T1	548539	8	0	1
T2	156058	0	0	1
T3	579139	0	0	1
T7	14425	0	0	1
T8	153351	0	0	1
T9	21337	0	0	1
T10	3692	0	0	1
T11	3416	0	0	1
T12	541477	9	0	1
T13	55351	0	0	1
T14	0	27	0	0
T15	0	7	0	0
T18	0	6	0	0
T19	0	12	0	0
T20	0	337	0	0
T23	0	54	0	0
T24	0	7	0	0
T25	0	15	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	1005867	0	0
T1	548539	1417	0	0
T2	156058	658	0	0
T3	579139	49	0	0
T7	14425	110	0	0
T8	153351	623	0	0
T9	21337	211	0	0
T10	3692	34	0	0
T11	3416	69	0	0
T12	541477	1275	0	0
T13	55351	736	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442452457	442312719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442452457	999302	0	0
GntImpliesValid_A	442452457	999302	0	0
GrantKnown_A	442452457	442312719	0	0
IdxKnown_A	442452457	442312719	0	0
IndexIsCorrect_A	442452457	999302	0	0
LockArbDecision_A	442452457	0	0	0
NoReadyValidNoGrant_A	442452457	370523000	0	0
ReadyAndValidImplyGrant_A	442452457	999302	0	0
ReqAndReadyImplyGrant_A	442452457	999302	0	0
ReqImpliesValid_A	442452457	14819106	0	0
ReqStaysHighUntilGranted0_M	442452457	0	0	0
RoundRobin_A	442452457	30283	0	900
ValidKnown_A	442452457	442312719	0	0
gen_data_port_assertion.DataFlow_A	442452457	999302	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	999302	0	0
T1	548539	1340	0	0
T2	156058	689	0	0
T3	579139	52	0	0
T7	14425	94	0	0
T8	153351	588	0	0
T9	21337	193	0	0
T10	3692	30	0	0
T11	3416	63	0	0
T12	541477	2010	0	0
T13	55351	649	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	999302	0	0
T1	548539	1340	0	0
T2	156058	689	0	0
T3	579139	52	0	0
T7	14425	94	0	0
T8	153351	588	0	0
T9	21337	193	0	0
T10	3692	30	0	0
T11	3416	63	0	0
T12	541477	2010	0	0
T13	55351	649	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	999302	0	0
T1	548539	1340	0	0
T2	156058	689	0	0
T3	579139	52	0	0
T7	14425	94	0	0
T8	153351	588	0	0
T9	21337	193	0	0
T10	3692	30	0	0
T11	3416	63	0	0
T12	541477	2010	0	0
T13	55351	649	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	370523000	0	0
T1	548539	456644	0	0
T2	156058	129797	0	0
T3	579139	560804	0	0
T7	14425	12345	0	0
T8	153351	127488	0	0
T9	21337	17468	0	0
T10	3692	3085	0	0
T11	3416	1	0	0
T12	541477	450367	0	0
T13	55351	45855	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	999302	0	0
T1	548539	1340	0	0
T2	156058	689	0	0
T3	579139	52	0	0
T7	14425	94	0	0
T8	153351	588	0	0
T9	21337	193	0	0
T10	3692	30	0	0
T11	3416	63	0	0
T12	541477	2010	0	0
T13	55351	649	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	999302	0	0
T1	548539	1340	0	0
T2	156058	689	0	0
T3	579139	52	0	0
T7	14425	94	0	0
T8	153351	588	0	0
T9	21337	193	0	0
T10	3692	30	0	0
T11	3416	63	0	0
T12	541477	2010	0	0
T13	55351	649	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	14819106	0	0
T1	548539	6255	0	0
T2	156058	3138	0	0
T3	579139	17178	0	0
T7	14425	810	0	0
T8	153351	2609	0	0
T9	21337	1405	0	0
T10	3692	247	0	0
T11	3416	63	0	0
T12	541477	8903	0	0
T13	55351	5071	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	30283	0	900
T1	548539	14	0	1
T2	156058	0	0	1
T3	579139	0	0	1
T7	14425	0	0	1
T8	153351	0	0	1
T9	21337	0	0	1
T10	3692	0	0	1
T11	3416	0	0	1
T12	541477	28	0	1
T13	55351	1	0	1
T14	0	26	0	0
T15	0	10	0	0
T18	0	9	0	0
T19	0	7	0	0
T20	0	42	0	0
T21	0	1	0	0
T22	0	29	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	442312719	0	0
T1	548539	548533	0	0
T2	156058	156055	0	0
T3	579139	579085	0	0
T7	14425	14359	0	0
T8	153351	153349	0	0
T9	21337	21308	0	0
T10	3692	3631	0	0
T11	3416	3362	0	0
T12	541477	541469	0	0
T13	55351	55341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442452457	999302	0	0
T1	548539	1340	0	0
T2	156058	689	0	0
T3	579139	52	0	0
T7	14425	94	0	0
T8	153351	588	0	0
T9	21337	193	0	0
T10	3692	30	0	0
T11	3416	63	0	0
T12	541477	2010	0	0
T13	55351	649	0	0