Line Coverage for Instance : tb.dut.u_s1n_27
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 87 | 87 | 100.00 |
| CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| ALWAYS | 116 | 9 | 9 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| ALWAYS | 180 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
| ALWAYS | 192 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 198 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 199 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 202 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 203 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 204 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 205 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 230 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 234 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 235 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 237 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 239 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 241 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 112 |
1 |
1 |
| 113 |
1 |
1 |
| 116 |
1 |
1 |
| 117 |
1 |
1 |
| 118 |
1 |
1 |
| 119 |
1 |
1 |
| 120 |
1 |
1 |
| 121 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 123 |
1 |
1 |
| 124 |
1 |
1 |
| 125 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 132 |
1 |
1 |
| 145 |
1 |
1 |
| 155 |
4 |
4 |
| 157 |
4 |
4 |
| 158 |
4 |
4 |
| 159 |
4 |
4 |
| 160 |
4 |
4 |
| 161 |
4 |
4 |
| 162 |
4 |
4 |
| 163 |
4 |
4 |
| 164 |
4 |
4 |
| 167 |
4 |
4 |
| 171 |
4 |
4 |
| 180 |
1 |
1 |
| 181 |
1 |
1 |
| 183 |
2 |
2 |
|
|
|
MISSING_ELSE |
| 185 |
2 |
2 |
|
|
|
MISSING_ELSE |
| 189 |
1 |
1 |
| 192 |
1 |
1 |
| 193 |
1 |
1 |
| 194 |
2 |
2 |
|
|
|
MISSING_ELSE |
| 197 |
1 |
1 |
| 198 |
1 |
1 |
| 199 |
1 |
1 |
| 200 |
1 |
1 |
| 201 |
1 |
1 |
| 202 |
1 |
1 |
| 203 |
1 |
1 |
| 204 |
1 |
1 |
| 205 |
1 |
1 |
| 230 |
1 |
1 |
| 231 |
1 |
1 |
| 234 |
1 |
1 |
| 235 |
1 |
1 |
| 236 |
1 |
1 |
| 237 |
1 |
1 |
| 238 |
1 |
1 |
| 239 |
1 |
1 |
| 240 |
1 |
1 |
| 241 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_s1n_27
| Total | Covered | Percent |
|---|
| Conditions | 72 | 71 | 98.61 |
| Logical | 72 | 71 | 98.61 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 112
EXPRESSION (tl_t_o.a_valid & tl_t_i.a_ready)
-------1------ -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 113
EXPRESSION (tl_t_i.d_valid & tl_t_o.d_ready)
-------1------ -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION ((num_req_outstanding != '0) & (dev_select_t != dev_select_outstanding))
-------------1------------- --------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 132
SUB-EXPRESSION (num_req_outstanding != '0)
-------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 132
SUB-EXPRESSION (dev_select_t != dev_select_outstanding)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 3'(0)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 3'(0))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 3'(1)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 3'(1))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 3'(2)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 3'(2))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 3'(3)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 3'(3))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[0].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T26,T27,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[1].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T29 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[2].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T23,T30 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[3].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T23,T30 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[2].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[3].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[2].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[3].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
EXPRESSION (dev_select_t == 3'(idx))
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 189
EXPRESSION (tl_t_o.a_valid & hfifo_reqready)
-------1------ -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T7,T16,T17 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 194
EXPRESSION (dev_select_outstanding == 3'(idx))
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 231
EXPRESSION (tl_t_o.a_valid & (dev_select_t >= 3'(N)) & ((~hold_all_requests)))
-------1------ -----------2----------- -----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T7,T16,T17 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T7,T10,T14 |
| 1 | 1 | 1 | Covered | T1,T7,T8 |
Branch Coverage for Instance : tb.dut.u_s1n_27
| Line No. | Total | Covered | Percent |
| Branches |
|
27 |
27 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| IF |
116 |
5 |
5 |
100.00 |
| IF |
183 |
2 |
2 |
100.00 |
| IF |
185 |
2 |
2 |
100.00 |
| IF |
194 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 164 (gen_u_o[0].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[0].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[1].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[1].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[2].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[2].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[3].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[3].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 116 if ((!rst_ni))
-2-: 119 if (accept_t_req)
-3-: 120 if ((!accept_t_rsp))
-4-: 124 if (accept_t_rsp)
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
0 |
- |
Covered |
T1,T9,T11 |
| 0 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if ((dev_select_t == 3'(idx)))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 185 if (hold_all_requests)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 194 if ((dev_select_outstanding == 3'(idx)))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_s1n_27
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
NotOverflowed_A |
442452457 |
442312719 |
0 |
0 |
|
maxN |
900 |
900 |
0 |
0 |
NotOverflowed_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
442452457 |
442312719 |
0 |
0 |
| T1 |
548539 |
548533 |
0 |
0 |
| T2 |
156058 |
156055 |
0 |
0 |
| T3 |
579139 |
579085 |
0 |
0 |
| T7 |
14425 |
14359 |
0 |
0 |
| T8 |
153351 |
153349 |
0 |
0 |
| T9 |
21337 |
21308 |
0 |
0 |
| T10 |
3692 |
3631 |
0 |
0 |
| T11 |
3416 |
3362 |
0 |
0 |
| T12 |
541477 |
541469 |
0 |
0 |
| T13 |
55351 |
55341 |
0 |
0 |
maxN
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
900 |
900 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_s1n_32
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 307 | 307 | 100.00 |
| CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| ALWAYS | 116 | 9 | 9 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| ALWAYS | 180 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
| ALWAYS | 192 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 198 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 199 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 202 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 203 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 204 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 205 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 230 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 234 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 235 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 237 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 239 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 241 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 112 |
1 |
1 |
| 113 |
1 |
1 |
| 116 |
1 |
1 |
| 117 |
1 |
1 |
| 118 |
1 |
1 |
| 119 |
1 |
1 |
| 120 |
1 |
1 |
| 121 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 123 |
1 |
1 |
| 124 |
1 |
1 |
| 125 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 132 |
1 |
1 |
| 145 |
1 |
1 |
| 155 |
24 |
24 |
| 157 |
24 |
24 |
| 158 |
24 |
24 |
| 159 |
24 |
24 |
| 160 |
24 |
24 |
| 161 |
24 |
24 |
| 162 |
24 |
24 |
| 163 |
24 |
24 |
| 164 |
24 |
24 |
| 167 |
24 |
24 |
| 171 |
24 |
24 |
| 180 |
1 |
1 |
| 181 |
1 |
1 |
| 183 |
2 |
2 |
|
|
|
MISSING_ELSE |
| 185 |
2 |
2 |
|
|
|
MISSING_ELSE |
| 189 |
1 |
1 |
| 192 |
1 |
1 |
| 193 |
1 |
1 |
| 194 |
2 |
2 |
|
|
|
MISSING_ELSE |
| 197 |
1 |
1 |
| 198 |
1 |
1 |
| 199 |
1 |
1 |
| 200 |
1 |
1 |
| 201 |
1 |
1 |
| 202 |
1 |
1 |
| 203 |
1 |
1 |
| 204 |
1 |
1 |
| 205 |
1 |
1 |
| 230 |
1 |
1 |
| 231 |
1 |
1 |
| 234 |
1 |
1 |
| 235 |
1 |
1 |
| 236 |
1 |
1 |
| 237 |
1 |
1 |
| 238 |
1 |
1 |
| 239 |
1 |
1 |
| 240 |
1 |
1 |
| 241 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_s1n_32
| Total | Covered | Percent |
|---|
| Conditions | 312 | 299 | 95.83 |
| Logical | 312 | 299 | 95.83 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 112
EXPRESSION (tl_t_o.a_valid & tl_t_i.a_ready)
-------1------ -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 113
EXPRESSION (tl_t_i.d_valid & tl_t_o.d_ready)
-------1------ -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION ((num_req_outstanding != '0) & (dev_select_t != dev_select_outstanding))
-------------1------------- --------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 132
SUB-EXPRESSION (num_req_outstanding != '0)
-------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 132
SUB-EXPRESSION (dev_select_t != dev_select_outstanding)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(0)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(0))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(1)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(1))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(2)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(2))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(3)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(3))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(4)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(4))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(5)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(5))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(6)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(6))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(7)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(7))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(8)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(8))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(9)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(9))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(10)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(10))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(11)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(11))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(12)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(12))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(13)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(13))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(14)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(14))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(15)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(15))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(16)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(16))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(17)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(17))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(18)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(18))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(19)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(19))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(20)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(20))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(21)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(21))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(22)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(22))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(23)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(23))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[0].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T32,T33,T31 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[1].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[2].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T31 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[3].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[4].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T32,T33,T31 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[5].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T7,T34,T32 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[6].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[7].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[8].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T35,T36 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[9].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[10].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[11].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T32,T37,T33 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[12].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[13].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[14].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[15].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T39 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[16].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[17].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T40,T41 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[18].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T7,T42,T21 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[19].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T33,T31,T43 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[20].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[21].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T44 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[22].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[23].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[2].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[3].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[4].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[5].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[6].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[7].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[8].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[9].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[10].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[11].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[12].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[13].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[14].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[15].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[16].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[17].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[18].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[19].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[20].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[21].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[22].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[23].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[2].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[3].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[4].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[5].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[6].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[7].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[8].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[9].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[10].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[11].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[12].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[13].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[14].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[15].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[16].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[17].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[18].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[19].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[20].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[21].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[22].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[23].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
EXPRESSION (dev_select_t == 5'(idx))
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 189
EXPRESSION (tl_t_o.a_valid & hfifo_reqready)
-------1------ -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T7,T11,T42 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 194
EXPRESSION (dev_select_outstanding == 5'(idx))
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 231
EXPRESSION (tl_t_o.a_valid & (dev_select_t >= 5'(N)) & ((~hold_all_requests)))
-------1------ -----------2----------- -----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T7,T11,T42 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T7,T10,T14 |
| 1 | 1 | 1 | Covered | T1,T2,T7 |
Branch Coverage for Instance : tb.dut.u_s1n_32
| Line No. | Total | Covered | Percent |
| Branches |
|
107 |
107 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| IF |
116 |
5 |
5 |
100.00 |
| IF |
183 |
2 |
2 |
100.00 |
| IF |
185 |
2 |
2 |
100.00 |
| IF |
194 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 164 (gen_u_o[0].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[0].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[1].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[1].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[2].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[2].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[3].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[3].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[4].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[4].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[5].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[5].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[6].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[6].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[7].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[7].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[8].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[8].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[9].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[9].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[10].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[10].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[11].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[11].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[12].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[12].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[13].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[13].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[14].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[14].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[15].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[15].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[16].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[16].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[17].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[17].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[18].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[18].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[19].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[19].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[20].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[20].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[21].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[21].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[22].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[22].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[23].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[23].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 116 if ((!rst_ni))
-2-: 119 if (accept_t_req)
-3-: 120 if ((!accept_t_rsp))
-4-: 124 if (accept_t_rsp)
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
0 |
- |
Covered |
T1,T9,T12 |
| 0 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if ((dev_select_t == 5'(idx)))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 185 if (hold_all_requests)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 194 if ((dev_select_outstanding == 5'(idx)))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_s1n_32
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
NotOverflowed_A |
442452457 |
442312719 |
0 |
0 |
|
maxN |
900 |
900 |
0 |
0 |
NotOverflowed_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
442452457 |
442312719 |
0 |
0 |
| T1 |
548539 |
548533 |
0 |
0 |
| T2 |
156058 |
156055 |
0 |
0 |
| T3 |
579139 |
579085 |
0 |
0 |
| T7 |
14425 |
14359 |
0 |
0 |
| T8 |
153351 |
153349 |
0 |
0 |
| T9 |
21337 |
21308 |
0 |
0 |
| T10 |
3692 |
3631 |
0 |
0 |
| T11 |
3416 |
3362 |
0 |
0 |
| T12 |
541477 |
541469 |
0 |
0 |
| T13 |
55351 |
55341 |
0 |
0 |
maxN
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
900 |
900 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_s1n_57
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 307 | 307 | 100.00 |
| CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| ALWAYS | 116 | 9 | 9 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| ALWAYS | 180 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
| ALWAYS | 192 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 198 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 199 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 202 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 203 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 204 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 205 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 230 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 234 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 235 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 237 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 239 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 241 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 112 |
1 |
1 |
| 113 |
1 |
1 |
| 116 |
1 |
1 |
| 117 |
1 |
1 |
| 118 |
1 |
1 |
| 119 |
1 |
1 |
| 120 |
1 |
1 |
| 121 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 123 |
1 |
1 |
| 124 |
1 |
1 |
| 125 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 132 |
1 |
1 |
| 145 |
1 |
1 |
| 155 |
24 |
24 |
| 157 |
24 |
24 |
| 158 |
24 |
24 |
| 159 |
24 |
24 |
| 160 |
24 |
24 |
| 161 |
24 |
24 |
| 162 |
24 |
24 |
| 163 |
24 |
24 |
| 164 |
24 |
24 |
| 167 |
24 |
24 |
| 171 |
24 |
24 |
| 180 |
1 |
1 |
| 181 |
1 |
1 |
| 183 |
2 |
2 |
|
|
|
MISSING_ELSE |
| 185 |
2 |
2 |
|
|
|
MISSING_ELSE |
| 189 |
1 |
1 |
| 192 |
1 |
1 |
| 193 |
1 |
1 |
| 194 |
2 |
2 |
|
|
|
MISSING_ELSE |
| 197 |
1 |
1 |
| 198 |
1 |
1 |
| 199 |
1 |
1 |
| 200 |
1 |
1 |
| 201 |
1 |
1 |
| 202 |
1 |
1 |
| 203 |
1 |
1 |
| 204 |
1 |
1 |
| 205 |
1 |
1 |
| 230 |
1 |
1 |
| 231 |
1 |
1 |
| 234 |
1 |
1 |
| 235 |
1 |
1 |
| 236 |
1 |
1 |
| 237 |
1 |
1 |
| 238 |
1 |
1 |
| 239 |
1 |
1 |
| 240 |
1 |
1 |
| 241 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_s1n_57
| Total | Covered | Percent |
|---|
| Conditions | 312 | 286 | 91.67 |
| Logical | 312 | 286 | 91.67 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 112
EXPRESSION (tl_t_o.a_valid & tl_t_i.a_ready)
-------1------ -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 113
EXPRESSION (tl_t_i.d_valid & tl_t_o.d_ready)
-------1------ -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION ((num_req_outstanding != '0) & (dev_select_t != dev_select_outstanding))
-------------1------------- --------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 132
SUB-EXPRESSION (num_req_outstanding != '0)
-------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 132
SUB-EXPRESSION (dev_select_t != dev_select_outstanding)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(0)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(0))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(1)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(1))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(2)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(2))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(3)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(3))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(4)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(4))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(5)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(5))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(6)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(6))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(7)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(7))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(8)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(8))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(9)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(9))
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(10)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(10))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(11)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(11))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(12)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(12))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(13)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(13))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(14)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(14))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(15)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(15))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(16)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(16))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(17)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(17))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(18)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(18))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(19)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(19))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(20)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(20))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(21)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(21))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 155
EXPRESSION ((dev_select_t == 5'(22)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(22))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((dev_select_t == 5'(23)) & ((~hold_all_requests)))
------------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (dev_select_t == 5'(23))
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[0].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[1].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[2].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[3].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[4].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[5].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[6].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[7].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[8].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[9].dev_select)
-------1------ ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[10].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[11].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[12].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[13].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[14].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[15].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[16].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[17].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[18].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[19].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[20].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[21].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T7 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[22].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (tl_t_o.a_valid & gen_u_o[23].dev_select)
-------1------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[2].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[3].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[4].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[5].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[6].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[7].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[8].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[9].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[10].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[11].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[12].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[13].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[14].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[15].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[16].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[17].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[18].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[19].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[20].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[21].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 164
EXPRESSION (gen_u_o[22].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_u_o[23].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[2].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[3].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[4].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[5].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[6].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[7].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[8].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[9].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[10].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[11].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[12].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[13].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[14].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[15].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[16].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[17].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[18].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[19].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[20].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[21].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 167
EXPRESSION (gen_u_o[22].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (gen_u_o[23].dev_select ? tl_t_o.a_user : blanked_auser)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
EXPRESSION (dev_select_t == 5'(idx))
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 189
EXPRESSION (tl_t_o.a_valid & hfifo_reqready)
-------1------ -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 194
EXPRESSION (dev_select_outstanding == 5'(idx))
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 231
EXPRESSION (tl_t_o.a_valid & (dev_select_t >= 5'(N)) & ((~hold_all_requests)))
-------1------ -----------2----------- -----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T7,T10,T14 |
| 1 | 1 | 1 | Covered | T7,T10,T12 |
Branch Coverage for Instance : tb.dut.u_s1n_57
| Line No. | Total | Covered | Percent |
| Branches |
|
107 |
107 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| TERNARY |
164 |
2 |
2 |
100.00 |
| TERNARY |
167 |
2 |
2 |
100.00 |
| IF |
116 |
5 |
5 |
100.00 |
| IF |
183 |
2 |
2 |
100.00 |
| IF |
185 |
2 |
2 |
100.00 |
| IF |
194 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 164 (gen_u_o[0].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[0].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[1].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[1].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[2].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[2].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[3].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[3].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[4].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[4].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[5].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[5].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[6].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[6].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[7].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[7].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[8].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[8].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[9].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[9].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[10].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[10].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[11].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[11].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[12].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[12].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[13].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[13].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[14].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[14].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[15].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[15].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[16].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[16].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[17].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[17].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[18].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[18].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[19].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[19].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[20].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[20].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[21].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[21].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[22].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[22].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 (gen_u_o[23].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (gen_u_o[23].dev_select) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 116 if ((!rst_ni))
-2-: 119 if (accept_t_req)
-3-: 120 if ((!accept_t_rsp))
-4-: 124 if (accept_t_rsp)
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
0 |
- |
Covered |
T1,T9,T12 |
| 0 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if ((dev_select_t == 5'(idx)))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 185 if (hold_all_requests)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 194 if ((dev_select_outstanding == 5'(idx)))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_s1n_57
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
NotOverflowed_A |
442452457 |
442312719 |
0 |
0 |
|
maxN |
900 |
900 |
0 |
0 |
NotOverflowed_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
442452457 |
442312719 |
0 |
0 |
| T1 |
548539 |
548533 |
0 |
0 |
| T2 |
156058 |
156055 |
0 |
0 |
| T3 |
579139 |
579085 |
0 |
0 |
| T7 |
14425 |
14359 |
0 |
0 |
| T8 |
153351 |
153349 |
0 |
0 |
| T9 |
21337 |
21308 |
0 |
0 |
| T10 |
3692 |
3631 |
0 |
0 |
| T11 |
3416 |
3362 |
0 |
0 |
| T12 |
541477 |
541469 |
0 |
0 |
| T13 |
55351 |
55341 |
0 |
0 |
maxN
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
900 |
900 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
