Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1533193 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 244424 1 T1 314 T2 13 T3 3


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 601862 1 T1 811 T2 62 T3 2
values[0x0] 573497 1 T1 809 T2 14 T3 1
values[0x1] 602258 1 T1 776 T2 60 T3 4


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1185356 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 592261 1 T1 785 T2 45 T3 3


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27817 1 T1 35 T2 1 T6 5
valid_sources[0x01] 27902 1 T1 26 T2 1 T6 7
valid_sources[0x02] 27988 1 T1 45 T2 3 T6 1
valid_sources[0x03] 27252 1 T1 67 T2 4 T6 3
valid_sources[0x04] 26791 1 T1 8 T2 4 T6 8
valid_sources[0x05] 27929 1 T1 29 T6 8 T7 28
valid_sources[0x06] 27156 1 T1 46 T2 2 T6 12
valid_sources[0x07] 27681 1 T1 26 T6 10 T4 18
valid_sources[0x08] 27250 1 T1 71 T2 2 T6 4
valid_sources[0x09] 28705 1 T1 28 T2 7 T6 9
valid_sources[0x0a] 27610 1 T1 53 T2 3 T6 6
valid_sources[0x0b] 26999 1 T1 26 T2 1 T6 5
valid_sources[0x0c] 28360 1 T1 65 T2 3 T6 9
valid_sources[0x0d] 27227 1 T1 22 T2 4 T6 8
valid_sources[0x0e] 28261 1 T1 9 T2 3 T6 6
valid_sources[0x0f] 28223 1 T1 57 T2 3 T6 4
valid_sources[0x10] 27596 1 T1 25 T2 4 T3 1
valid_sources[0x11] 29341 1 T1 44 T2 5 T6 6
valid_sources[0x12] 28113 1 T1 7 T6 4 T4 7
valid_sources[0x13] 28816 1 T1 23 T2 8 T6 2
valid_sources[0x14] 28758 1 T1 59 T2 1 T6 6
valid_sources[0x15] 28108 1 T1 65 T2 2 T6 3
valid_sources[0x16] 28317 1 T1 24 T2 3 T3 1
valid_sources[0x17] 28231 1 T1 51 T6 9 T7 25
valid_sources[0x18] 27282 1 T1 37 T2 1 T6 9
valid_sources[0x19] 27983 1 T1 46 T2 3 T6 5
valid_sources[0x1a] 27111 1 T1 19 T2 1 T3 1
valid_sources[0x1b] 28617 1 T1 51 T2 1 T6 4
valid_sources[0x1c] 28154 1 T1 35 T2 2 T6 9
valid_sources[0x1d] 27577 1 T1 21 T2 3 T6 6
valid_sources[0x1e] 27704 1 T1 53 T2 3 T6 5
valid_sources[0x1f] 28252 1 T1 26 T2 1 T6 7
valid_sources[0x20] 28197 1 T1 35 T6 9 T4 57


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25543 1 T1 26 T2 3 T3 1
values[0x0] all_enables biggest_size 193632 1 T1 253 T2 6 T6 19
values[0x1] all_enables biggest_size 25249 1 T1 35 T2 4 T3 2


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1544290 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 251594 1 T1 370 T2 16 T3 2


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 613970 1 T1 865 T2 49 T3 5
values[0x0] 568336 1 T1 770 T2 10 T3 2
values[0x1] 613578 1 T1 823 T2 58 T3 3


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1186052 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 609832 1 T1 843 T2 46 T3 5


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28249 1 T1 36 T2 5 T6 6
valid_sources[0x01] 29155 1 T1 45 T2 2 T3 1
valid_sources[0x02] 27425 1 T1 31 T6 6 T4 12
valid_sources[0x03] 27762 1 T1 40 T2 4 T6 3
valid_sources[0x04] 27674 1 T1 43 T2 1 T6 9
valid_sources[0x05] 28285 1 T1 43 T2 3 T6 6
valid_sources[0x06] 27930 1 T1 47 T2 1 T6 2
valid_sources[0x07] 28105 1 T1 44 T2 3 T6 6
valid_sources[0x08] 27763 1 T1 32 T2 1 T6 4
valid_sources[0x09] 28064 1 T1 36 T2 2 T6 6
valid_sources[0x0a] 28845 1 T1 26 T6 4 T4 22
valid_sources[0x0b] 27684 1 T1 46 T2 3 T3 2
valid_sources[0x0c] 28090 1 T1 36 T2 2 T6 5
valid_sources[0x0d] 28180 1 T1 36 T2 1 T6 4
valid_sources[0x0e] 28822 1 T1 30 T2 1 T6 5
valid_sources[0x0f] 27724 1 T1 46 T2 2 T6 5
valid_sources[0x10] 28167 1 T1 29 T2 3 T6 3
valid_sources[0x11] 27558 1 T1 39 T6 6 T4 9
valid_sources[0x12] 27471 1 T1 24 T2 1 T6 7
valid_sources[0x13] 27802 1 T1 38 T2 1 T6 3
valid_sources[0x14] 28751 1 T1 33 T6 5 T4 14
valid_sources[0x15] 28181 1 T1 41 T6 7 T4 19
valid_sources[0x16] 28145 1 T1 47 T2 3 T6 7
valid_sources[0x17] 27930 1 T1 53 T2 2 T6 4
valid_sources[0x18] 27922 1 T1 41 T2 5 T6 11
valid_sources[0x19] 27828 1 T1 29 T2 1 T3 1
valid_sources[0x1a] 27742 1 T1 38 T6 6 T4 14
valid_sources[0x1b] 28182 1 T1 44 T2 4 T6 5
valid_sources[0x1c] 28240 1 T1 37 T2 1 T6 4
valid_sources[0x1d] 27095 1 T1 35 T2 1 T6 9
valid_sources[0x1e] 28258 1 T1 38 T2 2 T6 3
valid_sources[0x1f] 28443 1 T1 37 T2 1 T6 6
valid_sources[0x20] 28088 1 T1 28 T2 1 T6 7


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26549 1 T1 41 T2 5 T6 14
values[0x0] all_enables biggest_size 198982 1 T1 291 T2 7 T3 2
values[0x1] all_enables biggest_size 26063 1 T1 38 T2 4 T6 13


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1540162 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 245585 1 T1 336 T2 13 T6 28


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 605172 1 T1 860 T2 68 T3 4
values[0x0] 576320 1 T1 796 T2 12 T6 22
values[0x1] 604255 1 T1 769 T2 58 T3 4


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1191433 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 594314 1 T1 809 T2 58 T3 2


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27919 1 T1 24 T2 2 T6 3
valid_sources[0x01] 27645 1 T1 39 T2 4 T6 4
valid_sources[0x02] 27353 1 T1 49 T2 2 T6 9
valid_sources[0x03] 27605 1 T1 33 T6 5 T4 25
valid_sources[0x04] 27469 1 T1 31 T2 2 T6 4
valid_sources[0x05] 27415 1 T1 32 T2 1 T6 2
valid_sources[0x06] 28574 1 T1 45 T2 4 T6 6
valid_sources[0x07] 28117 1 T1 34 T2 7 T3 2
valid_sources[0x08] 27520 1 T1 25 T2 1 T6 13
valid_sources[0x09] 27478 1 T1 40 T2 3 T6 4
valid_sources[0x0a] 28261 1 T1 29 T6 10 T4 3
valid_sources[0x0b] 26760 1 T1 57 T2 1 T6 5
valid_sources[0x0c] 27847 1 T1 33 T2 3 T6 4
valid_sources[0x0d] 27381 1 T1 38 T2 1 T6 5
valid_sources[0x0e] 27166 1 T1 54 T2 1 T6 7
valid_sources[0x0f] 27868 1 T1 37 T2 1 T6 1
valid_sources[0x10] 28449 1 T1 34 T2 5 T6 4
valid_sources[0x11] 28588 1 T1 33 T2 6 T6 9
valid_sources[0x12] 28939 1 T1 40 T2 3 T3 1
valid_sources[0x13] 28616 1 T1 41 T2 2 T6 4
valid_sources[0x14] 27736 1 T1 47 T2 1 T6 3
valid_sources[0x15] 28919 1 T1 36 T6 2 T4 1
valid_sources[0x16] 28566 1 T1 44 T2 3 T6 7
valid_sources[0x17] 27975 1 T1 55 T6 8 T4 6
valid_sources[0x18] 27888 1 T1 44 T2 1 T6 9
valid_sources[0x19] 27272 1 T1 36 T2 5 T6 1
valid_sources[0x1a] 27256 1 T1 35 T2 3 T3 1
valid_sources[0x1b] 27740 1 T1 35 T6 4 T4 12
valid_sources[0x1c] 27724 1 T1 53 T2 3 T6 7
valid_sources[0x1d] 27801 1 T1 30 T2 2 T6 5
valid_sources[0x1e] 27646 1 T1 39 T2 3 T6 6
valid_sources[0x1f] 28441 1 T1 33 T2 1 T6 2
valid_sources[0x20] 27968 1 T1 37 T2 2 T6 4


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25403 1 T1 34 T2 2 T6 10
values[0x0] all_enables biggest_size 194845 1 T1 268 T2 5 T6 8
values[0x1] all_enables biggest_size 25337 1 T1 34 T2 6 T6 10

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%