Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7174531	0	0
GntImpliesValid_A	2147483647	7174531	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7174531	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	447773040	0	0
ReadyAndValidImplyGrant_A	2147483647	7174531	0	0
ReqAndReadyImplyGrant_A	2147483647	7174531	0	0
ReqImpliesValid_A	2147483647	32162029	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	38693	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7174531	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2004552	2003136	0	0
T2	1688424	1687488	0	0
T3	33408	32064	0	0
T4	3071136	3070944	0	0
T6	6969816	6966768	0	0
T7	5063832	5063808	0	0
T8	6942864	6941280	0	0
T9	131616	130848	0	0
T10	111264	109728	0	0
T11	67488	65592	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7174531	0	0
T1	2004552	7274	0	0
T2	1688424	4535	0	0
T3	33408	442	0	0
T4	3071136	3005	0	0
T6	6969816	22186	0	0
T7	5063832	4454	0	0
T8	6942864	538	0	0
T9	131616	3425	0	0
T10	111264	535	0	0
T11	67488	466	0	0
T12	0	14862	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7174531	0	0
T1	2004552	7274	0	0
T2	1688424	4535	0	0
T3	33408	442	0	0
T4	3071136	3005	0	0
T6	6969816	22186	0	0
T7	5063832	4454	0	0
T8	6942864	538	0	0
T9	131616	3425	0	0
T10	111264	535	0	0
T11	67488	466	0	0
T12	0	14862	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2004552	2003136	0	0
T2	1688424	1687488	0	0
T3	33408	32064	0	0
T4	3071136	3070944	0	0
T6	6969816	6966768	0	0
T7	5063832	5063808	0	0
T8	6942864	6941280	0	0
T9	131616	130848	0	0
T10	111264	109728	0	0
T11	67488	65592	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2004552	2003136	0	0
T2	1688424	1687488	0	0
T3	33408	32064	0	0
T4	3071136	3070944	0	0
T6	6969816	6966768	0	0
T7	5063832	5063808	0	0
T8	6942864	6941280	0	0
T9	131616	130848	0	0
T10	111264	109728	0	0
T11	67488	65592	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7174531	0	0
T1	2004552	7274	0	0
T2	1688424	4535	0	0
T3	33408	442	0	0
T4	3071136	3005	0	0
T6	6969816	22186	0	0
T7	5063832	4454	0	0
T8	6942864	538	0	0
T9	131616	3425	0	0
T10	111264	535	0	0
T11	67488	466	0	0
T12	0	14862	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	447773040	0	0
T1	2004552	135141	0	0
T2	1688424	94824	0	0
T3	33408	713	0	0
T4	3071136	1120443	0	0
T6	6969816	360781	0	0
T7	5063832	187372	0	0
T8	6942864	243350	0	0
T9	131616	3472	0	0
T10	111264	7276	0	0
T11	67488	926	0	0
T12	0	37289	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7174531	0	0
T1	2004552	7274	0	0
T2	1688424	4535	0	0
T3	33408	442	0	0
T4	3071136	3005	0	0
T6	6969816	22186	0	0
T7	5063832	4454	0	0
T8	6942864	538	0	0
T9	131616	3425	0	0
T10	111264	535	0	0
T11	67488	466	0	0
T12	0	14862	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7174531	0	0
T1	2004552	7274	0	0
T2	1688424	4535	0	0
T3	33408	442	0	0
T4	3071136	3005	0	0
T6	6969816	22186	0	0
T7	5063832	4454	0	0
T8	6942864	538	0	0
T9	131616	3425	0	0
T10	111264	535	0	0
T11	67488	466	0	0
T12	0	14862	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32162029	0	0
T1	2004552	18188	0	0
T2	1688424	9399	0	0
T3	33408	570	0	0
T4	3071136	198747	0	0
T6	6969816	93969	0	0
T7	5063832	12461	0	0
T8	6942864	876	0	0
T9	131616	3876	0	0
T10	111264	1290	0	0
T11	67488	551	0	0
T12	0	46110	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38693	0	21600
T1	83523	3	0	1
T2	70351	0	0	1
T3	2784	2	0	2
T4	255928	0	0	2
T5	0	1	0	0
T6	580818	71	0	2
T7	421986	21	0	2
T8	578572	0	0	2
T9	10968	10	0	2
T10	9272	0	0	2
T11	5624	0	0	2
T12	337929	10	0	1
T13	309526	22	0	1
T14	0	1	0	0
T15	0	56	0	0
T16	0	34	0	0
T17	0	7	0	0
T18	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2004552	2003136	0	0
T2	1688424	1687488	0	0
T3	33408	32064	0	0
T4	3071136	3070944	0	0
T6	6969816	6966768	0	0
T7	5063832	5063808	0	0
T8	6942864	6941280	0	0
T9	131616	130848	0	0
T10	111264	109728	0	0
T11	67488	65592	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7174531	0	0
T1	2004552	7274	0	0
T2	1688424	4535	0	0
T3	33408	442	0	0
T4	3071136	3005	0	0
T6	6969816	22186	0	0
T7	5063832	4454	0	0
T8	6942864	538	0	0
T9	131616	3425	0	0
T10	111264	535	0	0
T11	67488	466	0	0
T12	0	14862	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	804791	0	0
GntImpliesValid_A	414178145	804791	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	804791	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	11208914	0	0
ReadyAndValidImplyGrant_A	414178145	804791	0	0
ReqAndReadyImplyGrant_A	414178145	804791	0	0
ReqImpliesValid_A	414178145	2258844	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	804791	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	804791	0	0
T1	83523	784	0	0
T2	70351	496	0	0
T3	1392	44	0	0
T4	127964	364	0	0
T6	290409	3478	0	0
T7	210993	926	0	0
T8	289286	61	0	0
T9	5484	403	0	0
T10	4636	62	0	0
T11	2812	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	804791	0	0
T1	83523	784	0	0
T2	70351	496	0	0
T3	1392	44	0	0
T4	127964	364	0	0
T6	290409	3478	0	0
T7	210993	926	0	0
T8	289286	61	0	0
T9	5484	403	0	0
T10	4636	62	0	0
T11	2812	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	804791	0	0
T1	83523	784	0	0
T2	70351	496	0	0
T3	1392	44	0	0
T4	127964	364	0	0
T6	290409	3478	0	0
T7	210993	926	0	0
T8	289286	61	0	0
T9	5484	403	0	0
T10	4636	62	0	0
T11	2812	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	11208914	0	0
T1	83523	5464	0	0
T2	70351	3584	0	0
T3	1392	33	0	0
T4	127964	122564	0	0
T6	290409	18530	0	0
T7	210993	3076	0	0
T8	289286	259	0	0
T9	5484	284	0	0
T10	4636	447	0	0
T11	2812	33	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	804791	0	0
T1	83523	784	0	0
T2	70351	496	0	0
T3	1392	44	0	0
T4	127964	364	0	0
T6	290409	3478	0	0
T7	210993	926	0	0
T8	289286	61	0	0
T9	5484	403	0	0
T10	4636	62	0	0
T11	2812	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	804791	0	0
T1	83523	784	0	0
T2	70351	496	0	0
T3	1392	44	0	0
T4	127964	364	0	0
T6	290409	3478	0	0
T7	210993	926	0	0
T8	289286	61	0	0
T9	5484	403	0	0
T10	4636	62	0	0
T11	2812	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	2258844	0	0
T1	83523	1298	0	0
T2	70351	742	0	0
T3	1392	56	0	0
T4	127964	15473	0	0
T6	290409	8297	0	0
T7	210993	2163	0	0
T8	289286	81	0	0
T9	5484	523	0	0
T10	4636	121	0	0
T11	2812	48	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	804791	0	0
T1	83523	784	0	0
T2	70351	496	0	0
T3	1392	44	0	0
T4	127964	364	0	0
T6	290409	3478	0	0
T7	210993	926	0	0
T8	289286	61	0	0
T9	5484	403	0	0
T10	4636	62	0	0
T11	2812	40	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	787119	0	0
GntImpliesValid_A	414178145	787119	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	787119	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	11352829	0	0
ReadyAndValidImplyGrant_A	414178145	787119	0	0
ReqAndReadyImplyGrant_A	414178145	787119	0	0
ReqImpliesValid_A	414178145	2223738	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	787119	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	787119	0	0
T1	83523	832	0	0
T2	70351	523	0	0
T3	1392	49	0	0
T4	127964	333	0	0
T6	290409	1829	0	0
T7	210993	182	0	0
T8	289286	64	0	0
T9	5484	380	0	0
T10	4636	64	0	0
T11	2812	59	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	787119	0	0
T1	83523	832	0	0
T2	70351	523	0	0
T3	1392	49	0	0
T4	127964	333	0	0
T6	290409	1829	0	0
T7	210993	182	0	0
T8	289286	64	0	0
T9	5484	380	0	0
T10	4636	64	0	0
T11	2812	59	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	787119	0	0
T1	83523	832	0	0
T2	70351	523	0	0
T3	1392	49	0	0
T4	127964	333	0	0
T6	290409	1829	0	0
T7	210993	182	0	0
T8	289286	64	0	0
T9	5484	380	0	0
T10	4636	64	0	0
T11	2812	59	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	11352829	0	0
T1	83523	6156	0	0
T2	70351	3678	0	0
T3	1392	40	0	0
T4	127964	109736	0	0
T6	290409	13815	0	0
T7	210993	705	0	0
T8	289286	239	0	0
T9	5484	289	0	0
T10	4636	491	0	0
T11	2812	41	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	787119	0	0
T1	83523	832	0	0
T2	70351	523	0	0
T3	1392	49	0	0
T4	127964	333	0	0
T6	290409	1829	0	0
T7	210993	182	0	0
T8	289286	64	0	0
T9	5484	380	0	0
T10	4636	64	0	0
T11	2812	59	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	787119	0	0
T1	83523	832	0	0
T2	70351	523	0	0
T3	1392	49	0	0
T4	127964	333	0	0
T6	290409	1829	0	0
T7	210993	182	0	0
T8	289286	64	0	0
T9	5484	380	0	0
T10	4636	64	0	0
T11	2812	59	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	2223738	0	0
T1	83523	1505	0	0
T2	70351	799	0	0
T3	1392	59	0	0
T4	127964	12201	0	0
T6	290409	2584	0	0
T7	210993	259	0	0
T8	289286	79	0	0
T9	5484	472	0	0
T10	4636	99	0	0
T11	2812	78	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	787119	0	0
T1	83523	832	0	0
T2	70351	523	0	0
T3	1392	49	0	0
T4	127964	333	0	0
T6	290409	1829	0	0
T7	210993	182	0	0
T8	289286	64	0	0
T9	5484	380	0	0
T10	4636	64	0	0
T11	2812	59	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	197173	0	0
GntImpliesValid_A	414178145	197173	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	197173	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	2861798	0	0
ReadyAndValidImplyGrant_A	414178145	197173	0	0
ReqAndReadyImplyGrant_A	414178145	197173	0	0
ReqImpliesValid_A	414178145	569770	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	197173	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	197173	0	0
T1	83523	204	0	0
T2	70351	117	0	0
T3	1392	13	0	0
T4	127964	89	0	0
T6	290409	736	0	0
T7	210993	0	0	0
T8	289286	16	0	0
T9	5484	102	0	0
T10	4636	13	0	0
T11	2812	16	0	0
T12	0	573	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	197173	0	0
T1	83523	204	0	0
T2	70351	117	0	0
T3	1392	13	0	0
T4	127964	89	0	0
T6	290409	736	0	0
T7	210993	0	0	0
T8	289286	16	0	0
T9	5484	102	0	0
T10	4636	13	0	0
T11	2812	16	0	0
T12	0	573	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	197173	0	0
T1	83523	204	0	0
T2	70351	117	0	0
T3	1392	13	0	0
T4	127964	89	0	0
T6	290409	736	0	0
T7	210993	0	0	0
T8	289286	16	0	0
T9	5484	102	0	0
T10	4636	13	0	0
T11	2812	16	0	0
T12	0	573	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	2861798	0	0
T1	83523	1425	0	0
T2	70351	963	0	0
T3	1392	13	0	0
T4	127964	28544	0	0
T6	290409	3010	0	0
T7	210993	1	0	0
T8	289286	61	0	0
T9	5484	97	0	0
T10	4636	121	0	0
T11	2812	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	197173	0	0
T1	83523	204	0	0
T2	70351	117	0	0
T3	1392	13	0	0
T4	127964	89	0	0
T6	290409	736	0	0
T7	210993	0	0	0
T8	289286	16	0	0
T9	5484	102	0	0
T10	4636	13	0	0
T11	2812	16	0	0
T12	0	573	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	197173	0	0
T1	83523	204	0	0
T2	70351	117	0	0
T3	1392	13	0	0
T4	127964	89	0	0
T6	290409	736	0	0
T7	210993	0	0	0
T8	289286	16	0	0
T9	5484	102	0	0
T10	4636	13	0	0
T11	2812	16	0	0
T12	0	573	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	569770	0	0
T1	83523	326	0	0
T2	70351	168	0	0
T3	1392	14	0	0
T4	127964	1704	0	0
T6	290409	4561	0	0
T7	210993	0	0	0
T8	289286	17	0	0
T9	5484	108	0	0
T10	4636	13	0	0
T11	2812	17	0	0
T12	0	783	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	197173	0	0
T1	83523	204	0	0
T2	70351	117	0	0
T3	1392	13	0	0
T4	127964	89	0	0
T6	290409	736	0	0
T7	210993	0	0	0
T8	289286	16	0	0
T9	5484	102	0	0
T10	4636	13	0	0
T11	2812	16	0	0
T12	0	573	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	202898	0	0
GntImpliesValid_A	414178145	202898	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	202898	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	2796507	0	0
ReadyAndValidImplyGrant_A	414178145	202898	0	0
ReqAndReadyImplyGrant_A	414178145	202898	0	0
ReqImpliesValid_A	414178145	520506	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	202898	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	202898	0	0
T1	83523	208	0	0
T2	70351	117	0	0
T3	1392	14	0	0
T4	127964	93	0	0
T6	290409	241	0	0
T7	210993	0	0	0
T8	289286	11	0	0
T9	5484	116	0	0
T10	4636	14	0	0
T11	2812	11	0	0
T12	0	549	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	202898	0	0
T1	83523	208	0	0
T2	70351	117	0	0
T3	1392	14	0	0
T4	127964	93	0	0
T6	290409	241	0	0
T7	210993	0	0	0
T8	289286	11	0	0
T9	5484	116	0	0
T10	4636	14	0	0
T11	2812	11	0	0
T12	0	549	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	202898	0	0
T1	83523	208	0	0
T2	70351	117	0	0
T3	1392	14	0	0
T4	127964	93	0	0
T6	290409	241	0	0
T7	210993	0	0	0
T8	289286	11	0	0
T9	5484	116	0	0
T10	4636	14	0	0
T11	2812	11	0	0
T12	0	549	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	2796507	0	0
T1	83523	1588	0	0
T2	70351	765	0	0
T3	1392	13	0	0
T4	127964	31172	0	0
T6	290409	1726	0	0
T7	210993	1	0	0
T8	289286	42	0	0
T9	5484	111	0	0
T10	4636	109	0	0
T11	2812	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	202898	0	0
T1	83523	208	0	0
T2	70351	117	0	0
T3	1392	14	0	0
T4	127964	93	0	0
T6	290409	241	0	0
T7	210993	0	0	0
T8	289286	11	0	0
T9	5484	116	0	0
T10	4636	14	0	0
T11	2812	11	0	0
T12	0	549	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	202898	0	0
T1	83523	208	0	0
T2	70351	117	0	0
T3	1392	14	0	0
T4	127964	93	0	0
T6	290409	241	0	0
T7	210993	0	0	0
T8	289286	11	0	0
T9	5484	116	0	0
T10	4636	14	0	0
T11	2812	11	0	0
T12	0	549	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	520506	0	0
T1	83523	296	0	0
T2	70351	145	0	0
T3	1392	16	0	0
T4	127964	994	0	0
T6	290409	264	0	0
T7	210993	0	0	0
T8	289286	11	0	0
T9	5484	122	0	0
T10	4636	28	0	0
T11	2812	12	0	0
T12	0	649	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	202898	0	0
T1	83523	208	0	0
T2	70351	117	0	0
T3	1392	14	0	0
T4	127964	93	0	0
T6	290409	241	0	0
T7	210993	0	0	0
T8	289286	11	0	0
T9	5484	116	0	0
T10	4636	14	0	0
T11	2812	11	0	0
T12	0	549	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	193237	0	0
GntImpliesValid_A	414178145	193237	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	193237	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	5732522	0	0
ReadyAndValidImplyGrant_A	414178145	193237	0	0
ReqAndReadyImplyGrant_A	414178145	193237	0	0
ReqImpliesValid_A	414178145	1298569	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	193237	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	193237	0	0
T1	83523	205	0	0
T2	70351	129	0	0
T3	1392	16	0	0
T4	127964	86	0	0
T6	290409	606	0	0
T7	210993	0	0	0
T8	289286	16	0	0
T9	5484	89	0	0
T10	4636	15	0	0
T11	2812	17	0	0
T12	0	532	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	193237	0	0
T1	83523	205	0	0
T2	70351	129	0	0
T3	1392	16	0	0
T4	127964	86	0	0
T6	290409	606	0	0
T7	210993	0	0	0
T8	289286	16	0	0
T9	5484	89	0	0
T10	4636	15	0	0
T11	2812	17	0	0
T12	0	532	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	193237	0	0
T1	83523	205	0	0
T2	70351	129	0	0
T3	1392	16	0	0
T4	127964	86	0	0
T6	290409	606	0	0
T7	210993	0	0	0
T8	289286	16	0	0
T9	5484	89	0	0
T10	4636	15	0	0
T11	2812	17	0	0
T12	0	532	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	5732522	0	0
T1	83523	2939	0	0
T2	70351	2324	0	0
T3	1392	81	0	0
T4	127964	72821	0	0
T6	290409	14305	0	0
T7	210993	0	0	0
T8	289286	143	0	0
T9	5484	386	0	0
T10	4636	140	0	0
T11	2812	86	0	0
T12	0	7692	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	193237	0	0
T1	83523	205	0	0
T2	70351	129	0	0
T3	1392	16	0	0
T4	127964	86	0	0
T6	290409	606	0	0
T7	210993	0	0	0
T8	289286	16	0	0
T9	5484	89	0	0
T10	4636	15	0	0
T11	2812	17	0	0
T12	0	532	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	193237	0	0
T1	83523	205	0	0
T2	70351	129	0	0
T3	1392	16	0	0
T4	127964	86	0	0
T6	290409	606	0	0
T7	210993	0	0	0
T8	289286	16	0	0
T9	5484	89	0	0
T10	4636	15	0	0
T11	2812	17	0	0
T12	0	532	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	1298569	0	0
T1	83523	431	0	0
T2	70351	245	0	0
T3	1392	28	0	0
T4	127964	5494	0	0
T6	290409	5289	0	0
T7	210993	0	0	0
T8	289286	51	0	0
T9	5484	131	0	0
T10	4636	15	0	0
T11	2812	24	0	0
T12	0	720	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	193237	0	0
T1	83523	205	0	0
T2	70351	129	0	0
T3	1392	16	0	0
T4	127964	86	0	0
T6	290409	606	0	0
T7	210993	0	0	0
T8	289286	16	0	0
T9	5484	89	0	0
T10	4636	15	0	0
T11	2812	17	0	0
T12	0	532	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	189152	0	0
GntImpliesValid_A	414178145	189152	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	189152	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	5066919	0	0
ReadyAndValidImplyGrant_A	414178145	189152	0	0
ReqAndReadyImplyGrant_A	414178145	189152	0	0
ReqImpliesValid_A	414178145	1036755	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	189152	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	189152	0	0
T1	83523	195	0	0
T2	70351	124	0	0
T3	1392	16	0	0
T4	127964	75	0	0
T6	290409	740	0	0
T7	210993	0	0	0
T8	289286	16	0	0
T9	5484	80	0	0
T10	4636	12	0	0
T11	2812	17	0	0
T12	0	1174	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	189152	0	0
T1	83523	195	0	0
T2	70351	124	0	0
T3	1392	16	0	0
T4	127964	75	0	0
T6	290409	740	0	0
T7	210993	0	0	0
T8	289286	16	0	0
T9	5484	80	0	0
T10	4636	12	0	0
T11	2812	17	0	0
T12	0	1174	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	189152	0	0
T1	83523	195	0	0
T2	70351	124	0	0
T3	1392	16	0	0
T4	127964	75	0	0
T6	290409	740	0	0
T7	210993	0	0	0
T8	289286	16	0	0
T9	5484	80	0	0
T10	4636	12	0	0
T11	2812	17	0	0
T12	0	1174	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	5066919	0	0
T1	83523	2618	0	0
T2	70351	3196	0	0
T3	1392	81	0	0
T4	127964	84392	0	0
T6	290409	4037	0	0
T7	210993	0	0	0
T8	289286	229	0	0
T9	5484	368	0	0
T10	4636	209	0	0
T11	2812	282	0	0
T12	0	24415	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	189152	0	0
T1	83523	195	0	0
T2	70351	124	0	0
T3	1392	16	0	0
T4	127964	75	0	0
T6	290409	740	0	0
T7	210993	0	0	0
T8	289286	16	0	0
T9	5484	80	0	0
T10	4636	12	0	0
T11	2812	17	0	0
T12	0	1174	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	189152	0	0
T1	83523	195	0	0
T2	70351	124	0	0
T3	1392	16	0	0
T4	127964	75	0	0
T6	290409	740	0	0
T7	210993	0	0	0
T8	289286	16	0	0
T9	5484	80	0	0
T10	4636	12	0	0
T11	2812	17	0	0
T12	0	1174	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	1036755	0	0
T1	83523	404	0	0
T2	70351	344	0	0
T3	1392	37	0	0
T4	127964	7134	0	0
T6	290409	6563	0	0
T7	210993	0	0	0
T8	289286	33	0	0
T9	5484	112	0	0
T10	4636	12	0	0
T11	2812	31	0	0
T12	0	11180	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	189152	0	0
T1	83523	195	0	0
T2	70351	124	0	0
T3	1392	16	0	0
T4	127964	75	0	0
T6	290409	740	0	0
T7	210993	0	0	0
T8	289286	16	0	0
T9	5484	80	0	0
T10	4636	12	0	0
T11	2812	17	0	0
T12	0	1174	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	197264	0	0
GntImpliesValid_A	414178145	197264	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	197264	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	4896983	0	0
ReadyAndValidImplyGrant_A	414178145	197264	0	0
ReqAndReadyImplyGrant_A	414178145	197264	0	0
ReqImpliesValid_A	414178145	1079570	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	197264	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	197264	0	0
T1	83523	180	0	0
T2	70351	130	0	0
T3	1392	22	0	0
T4	127964	73	0	0
T6	290409	268	0	0
T7	210993	498	0	0
T8	289286	14	0	0
T9	5484	77	0	0
T10	4636	10	0	0
T11	2812	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	197264	0	0
T1	83523	180	0	0
T2	70351	130	0	0
T3	1392	22	0	0
T4	127964	73	0	0
T6	290409	268	0	0
T7	210993	498	0	0
T8	289286	14	0	0
T9	5484	77	0	0
T10	4636	10	0	0
T11	2812	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	197264	0	0
T1	83523	180	0	0
T2	70351	130	0	0
T3	1392	22	0	0
T4	127964	73	0	0
T6	290409	268	0	0
T7	210993	498	0	0
T8	289286	14	0	0
T9	5484	77	0	0
T10	4636	10	0	0
T11	2812	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	4896983	0	0
T1	83523	10046	0	0
T2	70351	1508	0	0
T3	1392	208	0	0
T4	127964	28733	0	0
T6	290409	2906	0	0
T7	210993	2268	0	0
T8	289286	220	0	0
T9	5484	304	0	0
T10	4636	116	0	0
T11	2812	192	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	197264	0	0
T1	83523	180	0	0
T2	70351	130	0	0
T3	1392	22	0	0
T4	127964	73	0	0
T6	290409	268	0	0
T7	210993	498	0	0
T8	289286	14	0	0
T9	5484	77	0	0
T10	4636	10	0	0
T11	2812	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	197264	0	0
T1	83523	180	0	0
T2	70351	130	0	0
T3	1392	22	0	0
T4	127964	73	0	0
T6	290409	268	0	0
T7	210993	498	0	0
T8	289286	14	0	0
T9	5484	77	0	0
T10	4636	10	0	0
T11	2812	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	1079570	0	0
T1	83523	791	0	0
T2	70351	231	0	0
T3	1392	83	0	0
T4	127964	702	0	0
T6	290409	301	0	0
T7	210993	1450	0	0
T8	289286	26	0	0
T9	5484	116	0	0
T10	4636	20	0	0
T11	2812	44	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	197264	0	0
T1	83523	180	0	0
T2	70351	130	0	0
T3	1392	22	0	0
T4	127964	73	0	0
T6	290409	268	0	0
T7	210993	498	0	0
T8	289286	14	0	0
T9	5484	77	0	0
T10	4636	10	0	0
T11	2812	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	197251	0	0
GntImpliesValid_A	414178145	197251	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	197251	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	4771676	0	0
ReadyAndValidImplyGrant_A	414178145	197251	0	0
ReqAndReadyImplyGrant_A	414178145	197251	0	0
ReqImpliesValid_A	414178145	1028854	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	197251	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	197251	0	0
T1	83523	205	0	0
T2	70351	132	0	0
T3	1392	10	0	0
T4	127964	89	0	0
T6	290409	716	0	0
T7	210993	0	0	0
T8	289286	10	0	0
T9	5484	83	0	0
T10	4636	17	0	0
T11	2812	10	0	0
T12	0	543	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	197251	0	0
T1	83523	205	0	0
T2	70351	132	0	0
T3	1392	10	0	0
T4	127964	89	0	0
T6	290409	716	0	0
T7	210993	0	0	0
T8	289286	10	0	0
T9	5484	83	0	0
T10	4636	17	0	0
T11	2812	10	0	0
T12	0	543	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	197251	0	0
T1	83523	205	0	0
T2	70351	132	0	0
T3	1392	10	0	0
T4	127964	89	0	0
T6	290409	716	0	0
T7	210993	0	0	0
T8	289286	10	0	0
T9	5484	83	0	0
T10	4636	17	0	0
T11	2812	10	0	0
T12	0	543	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	4771676	0	0
T1	83523	10298	0	0
T2	70351	1061	0	0
T3	1392	58	0	0
T4	127964	36197	0	0
T6	290409	3557	0	0
T7	210993	0	0	0
T8	289286	119	0	0
T9	5484	379	0	0
T10	4636	113	0	0
T11	2812	57	0	0
T12	0	5182	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	197251	0	0
T1	83523	205	0	0
T2	70351	132	0	0
T3	1392	10	0	0
T4	127964	89	0	0
T6	290409	716	0	0
T7	210993	0	0	0
T8	289286	10	0	0
T9	5484	83	0	0
T10	4636	17	0	0
T11	2812	10	0	0
T12	0	543	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	197251	0	0
T1	83523	205	0	0
T2	70351	132	0	0
T3	1392	10	0	0
T4	127964	89	0	0
T6	290409	716	0	0
T7	210993	0	0	0
T8	289286	10	0	0
T9	5484	83	0	0
T10	4636	17	0	0
T11	2812	10	0	0
T12	0	543	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	1028854	0	0
T1	83523	1717	0	0
T2	70351	169	0	0
T3	1392	10	0	0
T4	127964	1302	0	0
T6	290409	4564	0	0
T7	210993	0	0	0
T8	289286	22	0	0
T9	5484	111	0	0
T10	4636	42	0	0
T11	2812	10	0	0
T12	0	689	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	197251	0	0
T1	83523	205	0	0
T2	70351	132	0	0
T3	1392	10	0	0
T4	127964	89	0	0
T6	290409	716	0	0
T7	210993	0	0	0
T8	289286	10	0	0
T9	5484	83	0	0
T10	4636	17	0	0
T11	2812	10	0	0
T12	0	543	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	199820	0	0
GntImpliesValid_A	414178145	199820	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	199820	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	2853961	0	0
ReadyAndValidImplyGrant_A	414178145	199820	0	0
ReqAndReadyImplyGrant_A	414178145	199820	0	0
ReqImpliesValid_A	414178145	545494	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	199820	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	199820	0	0
T1	83523	233	0	0
T2	70351	123	0	0
T3	1392	7	0	0
T4	127964	66	0	0
T6	290409	254	0	0
T7	210993	524	0	0
T8	289286	11	0	0
T9	5484	110	0	0
T10	4636	19	0	0
T11	2812	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	199820	0	0
T1	83523	233	0	0
T2	70351	123	0	0
T3	1392	7	0	0
T4	127964	66	0	0
T6	290409	254	0	0
T7	210993	524	0	0
T8	289286	11	0	0
T9	5484	110	0	0
T10	4636	19	0	0
T11	2812	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	199820	0	0
T1	83523	233	0	0
T2	70351	123	0	0
T3	1392	7	0	0
T4	127964	66	0	0
T6	290409	254	0	0
T7	210993	524	0	0
T8	289286	11	0	0
T9	5484	110	0	0
T10	4636	19	0	0
T11	2812	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	2853961	0	0
T1	83523	1841	0	0
T2	70351	952	0	0
T3	1392	8	0	0
T4	127964	23950	0	0
T6	290409	1909	0	0
T7	210993	1807	0	0
T8	289286	56	0	0
T9	5484	102	0	0
T10	4636	164	0	0
T11	2812	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	199820	0	0
T1	83523	233	0	0
T2	70351	123	0	0
T3	1392	7	0	0
T4	127964	66	0	0
T6	290409	254	0	0
T7	210993	524	0	0
T8	289286	11	0	0
T9	5484	110	0	0
T10	4636	19	0	0
T11	2812	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	199820	0	0
T1	83523	233	0	0
T2	70351	123	0	0
T3	1392	7	0	0
T4	127964	66	0	0
T6	290409	254	0	0
T7	210993	524	0	0
T8	289286	11	0	0
T9	5484	110	0	0
T10	4636	19	0	0
T11	2812	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	545494	0	0
T1	83523	280	0	0
T2	70351	141	0	0
T3	1392	7	0	0
T4	127964	791	0	0
T6	290409	255	0	0
T7	210993	1180	0	0
T8	289286	11	0	0
T9	5484	119	0	0
T10	4636	37	0	0
T11	2812	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	199820	0	0
T1	83523	233	0	0
T2	70351	123	0	0
T3	1392	7	0	0
T4	127964	66	0	0
T6	290409	254	0	0
T7	210993	524	0	0
T8	289286	11	0	0
T9	5484	110	0	0
T10	4636	19	0	0
T11	2812	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	203279	0	0
GntImpliesValid_A	414178145	203279	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	203279	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	2774426	0	0
ReadyAndValidImplyGrant_A	414178145	203279	0	0
ReqAndReadyImplyGrant_A	414178145	203279	0	0
ReqImpliesValid_A	414178145	586357	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	203279	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	203279	0	0
T1	83523	206	0	0
T2	70351	140	0	0
T3	1392	10	0	0
T4	127964	79	0	0
T6	290409	721	0	0
T7	210993	0	0	0
T8	289286	12	0	0
T9	5484	89	0	0
T10	4636	23	0	0
T11	2812	14	0	0
T12	0	546	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	203279	0	0
T1	83523	206	0	0
T2	70351	140	0	0
T3	1392	10	0	0
T4	127964	79	0	0
T6	290409	721	0	0
T7	210993	0	0	0
T8	289286	12	0	0
T9	5484	89	0	0
T10	4636	23	0	0
T11	2812	14	0	0
T12	0	546	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	203279	0	0
T1	83523	206	0	0
T2	70351	140	0	0
T3	1392	10	0	0
T4	127964	79	0	0
T6	290409	721	0	0
T7	210993	0	0	0
T8	289286	12	0	0
T9	5484	89	0	0
T10	4636	23	0	0
T11	2812	14	0	0
T12	0	546	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	2774426	0	0
T1	83523	1481	0	0
T2	70351	1215	0	0
T3	1392	10	0	0
T4	127964	24207	0	0
T6	290409	2847	0	0
T7	210993	1	0	0
T8	289286	52	0	0
T9	5484	85	0	0
T10	4636	218	0	0
T11	2812	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	203279	0	0
T1	83523	206	0	0
T2	70351	140	0	0
T3	1392	10	0	0
T4	127964	79	0	0
T6	290409	721	0	0
T7	210993	0	0	0
T8	289286	12	0	0
T9	5484	89	0	0
T10	4636	23	0	0
T11	2812	14	0	0
T12	0	546	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	203279	0	0
T1	83523	206	0	0
T2	70351	140	0	0
T3	1392	10	0	0
T4	127964	79	0	0
T6	290409	721	0	0
T7	210993	0	0	0
T8	289286	12	0	0
T9	5484	89	0	0
T10	4636	23	0	0
T11	2812	14	0	0
T12	0	546	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	586357	0	0
T1	83523	265	0	0
T2	70351	200	0	0
T3	1392	11	0	0
T4	127964	492	0	0
T6	290409	4105	0	0
T7	210993	0	0	0
T8	289286	15	0	0
T9	5484	94	0	0
T10	4636	37	0	0
T11	2812	16	0	0
T12	0	629	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	203279	0	0
T1	83523	206	0	0
T2	70351	140	0	0
T3	1392	10	0	0
T4	127964	79	0	0
T6	290409	721	0	0
T7	210993	0	0	0
T8	289286	12	0	0
T9	5484	89	0	0
T10	4636	23	0	0
T11	2812	14	0	0
T12	0	546	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	189688	0	0
GntImpliesValid_A	414178145	189688	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	189688	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	2777428	0	0
ReadyAndValidImplyGrant_A	414178145	189688	0	0
ReqAndReadyImplyGrant_A	414178145	189688	0	0
ReqImpliesValid_A	414178145	513994	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	189688	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	189688	0	0
T1	83523	225	0	0
T2	70351	115	0	0
T3	1392	13	0	0
T4	127964	82	0	0
T6	290409	806	0	0
T7	210993	0	0	0
T8	289286	10	0	0
T9	5484	90	0	0
T10	4636	9	0	0
T11	2812	14	0	0
T12	0	1064	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	189688	0	0
T1	83523	225	0	0
T2	70351	115	0	0
T3	1392	13	0	0
T4	127964	82	0	0
T6	290409	806	0	0
T7	210993	0	0	0
T8	289286	10	0	0
T9	5484	90	0	0
T10	4636	9	0	0
T11	2812	14	0	0
T12	0	1064	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	189688	0	0
T1	83523	225	0	0
T2	70351	115	0	0
T3	1392	13	0	0
T4	127964	82	0	0
T6	290409	806	0	0
T7	210993	0	0	0
T8	289286	10	0	0
T9	5484	90	0	0
T10	4636	9	0	0
T11	2812	14	0	0
T12	0	1064	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	2777428	0	0
T1	83523	1628	0	0
T2	70351	841	0	0
T3	1392	14	0	0
T4	127964	27644	0	0
T6	290409	5179	0	0
T7	210993	1	0	0
T8	289286	47	0	0
T9	5484	85	0	0
T10	4636	65	0	0
T11	2812	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	189688	0	0
T1	83523	225	0	0
T2	70351	115	0	0
T3	1392	13	0	0
T4	127964	82	0	0
T6	290409	806	0	0
T7	210993	0	0	0
T8	289286	10	0	0
T9	5484	90	0	0
T10	4636	9	0	0
T11	2812	14	0	0
T12	0	1064	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	189688	0	0
T1	83523	225	0	0
T2	70351	115	0	0
T3	1392	13	0	0
T4	127964	82	0	0
T6	290409	806	0	0
T7	210993	0	0	0
T8	289286	10	0	0
T9	5484	90	0	0
T10	4636	9	0	0
T11	2812	14	0	0
T12	0	1064	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	513994	0	0
T1	83523	340	0	0
T2	70351	126	0	0
T3	1392	13	0	0
T4	127964	1949	0	0
T6	290409	2457	0	0
T7	210993	0	0	0
T8	289286	10	0	0
T9	5484	96	0	0
T10	4636	9	0	0
T11	2812	15	0	0
T12	0	3321	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	189688	0	0
T1	83523	225	0	0
T2	70351	115	0	0
T3	1392	13	0	0
T4	127964	82	0	0
T6	290409	806	0	0
T7	210993	0	0	0
T8	289286	10	0	0
T9	5484	90	0	0
T10	4636	9	0	0
T11	2812	14	0	0
T12	0	1064	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	200658	0	0
GntImpliesValid_A	414178145	200658	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	200658	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	2810951	0	0
ReadyAndValidImplyGrant_A	414178145	200658	0	0
ReqAndReadyImplyGrant_A	414178145	200658	0	0
ReqImpliesValid_A	414178145	554207	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	200658	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	200658	0	0
T1	83523	216	0	0
T2	70351	116	0	0
T3	1392	17	0	0
T4	127964	89	0	0
T6	290409	234	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	95	0	0
T10	4636	9	0	0
T11	2812	17	0	0
T12	0	1017	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	200658	0	0
T1	83523	216	0	0
T2	70351	116	0	0
T3	1392	17	0	0
T4	127964	89	0	0
T6	290409	234	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	95	0	0
T10	4636	9	0	0
T11	2812	17	0	0
T12	0	1017	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	200658	0	0
T1	83523	216	0	0
T2	70351	116	0	0
T3	1392	17	0	0
T4	127964	89	0	0
T6	290409	234	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	95	0	0
T10	4636	9	0	0
T11	2812	17	0	0
T12	0	1017	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	2810951	0	0
T1	83523	1546	0	0
T2	70351	925	0	0
T3	1392	17	0	0
T4	127964	31956	0	0
T6	290409	1772	0	0
T7	210993	1	0	0
T8	289286	60	0	0
T9	5484	91	0	0
T10	4636	76	0	0
T11	2812	18	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	200658	0	0
T1	83523	216	0	0
T2	70351	116	0	0
T3	1392	17	0	0
T4	127964	89	0	0
T6	290409	234	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	95	0	0
T10	4636	9	0	0
T11	2812	17	0	0
T12	0	1017	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	200658	0	0
T1	83523	216	0	0
T2	70351	116	0	0
T3	1392	17	0	0
T4	127964	89	0	0
T6	290409	234	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	95	0	0
T10	4636	9	0	0
T11	2812	17	0	0
T12	0	1017	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	554207	0	0
T1	83523	349	0	0
T2	70351	148	0	0
T3	1392	18	0	0
T4	127964	2365	0	0
T6	290409	246	0	0
T7	210993	0	0	0
T8	289286	15	0	0
T9	5484	100	0	0
T10	4636	9	0	0
T11	2812	17	0	0
T12	0	2936	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	200658	0	0
T1	83523	216	0	0
T2	70351	116	0	0
T3	1392	17	0	0
T4	127964	89	0	0
T6	290409	234	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	95	0	0
T10	4636	9	0	0
T11	2812	17	0	0
T12	0	1017	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	198414	0	0
GntImpliesValid_A	414178145	198414	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	198414	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	2850873	0	0
ReadyAndValidImplyGrant_A	414178145	198414	0	0
ReqAndReadyImplyGrant_A	414178145	198414	0	0
ReqImpliesValid_A	414178145	516760	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	198414	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	198414	0	0
T1	83523	194	0	0
T2	70351	109	0	0
T3	1392	13	0	0
T4	127964	86	0	0
T6	290409	691	0	0
T7	210993	518	0	0
T8	289286	14	0	0
T9	5484	88	0	0
T10	4636	13	0	0
T11	2812	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	198414	0	0
T1	83523	194	0	0
T2	70351	109	0	0
T3	1392	13	0	0
T4	127964	86	0	0
T6	290409	691	0	0
T7	210993	518	0	0
T8	289286	14	0	0
T9	5484	88	0	0
T10	4636	13	0	0
T11	2812	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	198414	0	0
T1	83523	194	0	0
T2	70351	109	0	0
T3	1392	13	0	0
T4	127964	86	0	0
T6	290409	691	0	0
T7	210993	518	0	0
T8	289286	14	0	0
T9	5484	88	0	0
T10	4636	13	0	0
T11	2812	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	2850873	0	0
T1	83523	1546	0	0
T2	70351	761	0	0
T3	1392	13	0	0
T4	127964	28374	0	0
T6	290409	4443	0	0
T7	210993	1720	0	0
T8	289286	63	0	0
T9	5484	82	0	0
T10	4636	108	0	0
T11	2812	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	198414	0	0
T1	83523	194	0	0
T2	70351	109	0	0
T3	1392	13	0	0
T4	127964	86	0	0
T6	290409	691	0	0
T7	210993	518	0	0
T8	289286	14	0	0
T9	5484	88	0	0
T10	4636	13	0	0
T11	2812	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	198414	0	0
T1	83523	194	0	0
T2	70351	109	0	0
T3	1392	13	0	0
T4	127964	86	0	0
T6	290409	691	0	0
T7	210993	518	0	0
T8	289286	14	0	0
T9	5484	88	0	0
T10	4636	13	0	0
T11	2812	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	516760	0	0
T1	83523	245	0	0
T2	70351	176	0	0
T3	1392	14	0	0
T4	127964	1442	0	0
T6	290409	2222	0	0
T7	210993	1176	0	0
T8	289286	14	0	0
T9	5484	95	0	0
T10	4636	13	0	0
T11	2812	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	198414	0	0
T1	83523	194	0	0
T2	70351	109	0	0
T3	1392	13	0	0
T4	127964	86	0	0
T6	290409	691	0	0
T7	210993	518	0	0
T8	289286	14	0	0
T9	5484	88	0	0
T10	4636	13	0	0
T11	2812	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	196025	0	0
GntImpliesValid_A	414178145	196025	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	196025	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	2809098	0	0
ReadyAndValidImplyGrant_A	414178145	196025	0	0
ReqAndReadyImplyGrant_A	414178145	196025	0	0
ReqImpliesValid_A	414178145	507696	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	196025	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	196025	0	0
T1	83523	207	0	0
T2	70351	140	0	0
T3	1392	17	0	0
T4	127964	72	0	0
T6	290409	1187	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	67	0	0
T10	4636	15	0	0
T11	2812	23	0	0
T12	0	608	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	196025	0	0
T1	83523	207	0	0
T2	70351	140	0	0
T3	1392	17	0	0
T4	127964	72	0	0
T6	290409	1187	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	67	0	0
T10	4636	15	0	0
T11	2812	23	0	0
T12	0	608	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	196025	0	0
T1	83523	207	0	0
T2	70351	140	0	0
T3	1392	17	0	0
T4	127964	72	0	0
T6	290409	1187	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	67	0	0
T10	4636	15	0	0
T11	2812	23	0	0
T12	0	608	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	2809098	0	0
T1	83523	1469	0	0
T2	70351	1128	0	0
T3	1392	16	0	0
T4	127964	23789	0	0
T6	290409	4169	0	0
T7	210993	1	0	0
T8	289286	59	0	0
T9	5484	65	0	0
T10	4636	112	0	0
T11	2812	24	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	196025	0	0
T1	83523	207	0	0
T2	70351	140	0	0
T3	1392	17	0	0
T4	127964	72	0	0
T6	290409	1187	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	67	0	0
T10	4636	15	0	0
T11	2812	23	0	0
T12	0	608	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	196025	0	0
T1	83523	207	0	0
T2	70351	140	0	0
T3	1392	17	0	0
T4	127964	72	0	0
T6	290409	1187	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	67	0	0
T10	4636	15	0	0
T11	2812	23	0	0
T12	0	608	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	507696	0	0
T1	83523	315	0	0
T2	70351	180	0	0
T3	1392	19	0	0
T4	127964	1322	0	0
T6	290409	8579	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	70	0	0
T10	4636	38	0	0
T11	2812	23	0	0
T12	0	760	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	196025	0	0
T1	83523	207	0	0
T2	70351	140	0	0
T3	1392	17	0	0
T4	127964	72	0	0
T6	290409	1187	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	67	0	0
T10	4636	15	0	0
T11	2812	23	0	0
T12	0	608	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	190115	0	0
GntImpliesValid_A	414178145	190115	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	190115	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	2752663	0	0
ReadyAndValidImplyGrant_A	414178145	190115	0	0
ReqAndReadyImplyGrant_A	414178145	190115	0	0
ReqImpliesValid_A	414178145	488167	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	190115	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	190115	0	0
T1	83523	190	0	0
T2	70351	124	0	0
T3	1392	10	0	0
T4	127964	86	0	0
T6	290409	675	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	92	0	0
T10	4636	16	0	0
T11	2812	5	0	0
T12	0	1090	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	190115	0	0
T1	83523	190	0	0
T2	70351	124	0	0
T3	1392	10	0	0
T4	127964	86	0	0
T6	290409	675	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	92	0	0
T10	4636	16	0	0
T11	2812	5	0	0
T12	0	1090	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	190115	0	0
T1	83523	190	0	0
T2	70351	124	0	0
T3	1392	10	0	0
T4	127964	86	0	0
T6	290409	675	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	92	0	0
T10	4636	16	0	0
T11	2812	5	0	0
T12	0	1090	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	2752663	0	0
T1	83523	1383	0	0
T2	70351	876	0	0
T3	1392	11	0	0
T4	127964	25650	0	0
T6	290409	2749	0	0
T7	210993	1	0	0
T8	289286	54	0	0
T9	5484	87	0	0
T10	4636	86	0	0
T11	2812	6	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	190115	0	0
T1	83523	190	0	0
T2	70351	124	0	0
T3	1392	10	0	0
T4	127964	86	0	0
T6	290409	675	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	92	0	0
T10	4636	16	0	0
T11	2812	5	0	0
T12	0	1090	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	190115	0	0
T1	83523	190	0	0
T2	70351	124	0	0
T3	1392	10	0	0
T4	127964	86	0	0
T6	290409	675	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	92	0	0
T10	4636	16	0	0
T11	2812	5	0	0
T12	0	1090	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	488167	0	0
T1	83523	265	0	0
T2	70351	135	0	0
T3	1392	10	0	0
T4	127964	1486	0	0
T6	290409	3927	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	98	0	0
T10	4636	16	0	0
T11	2812	5	0	0
T12	0	2979	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	190115	0	0
T1	83523	190	0	0
T2	70351	124	0	0
T3	1392	10	0	0
T4	127964	86	0	0
T6	290409	675	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	92	0	0
T10	4636	16	0	0
T11	2812	5	0	0
T12	0	1090	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	195828	0	0
GntImpliesValid_A	414178145	195828	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	195828	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	2773558	0	0
ReadyAndValidImplyGrant_A	414178145	195828	0	0
ReqAndReadyImplyGrant_A	414178145	195828	0	0
ReqImpliesValid_A	414178145	533657	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	195828	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	195828	0	0
T1	83523	171	0	0
T2	70351	114	0	0
T3	1392	13	0	0
T4	127964	78	0	0
T6	290409	245	0	0
T7	210993	0	0	0
T8	289286	22	0	0
T9	5484	99	0	0
T10	4636	12	0	0
T11	2812	18	0	0
T12	0	1120	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	195828	0	0
T1	83523	171	0	0
T2	70351	114	0	0
T3	1392	13	0	0
T4	127964	78	0	0
T6	290409	245	0	0
T7	210993	0	0	0
T8	289286	22	0	0
T9	5484	99	0	0
T10	4636	12	0	0
T11	2812	18	0	0
T12	0	1120	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	195828	0	0
T1	83523	171	0	0
T2	70351	114	0	0
T3	1392	13	0	0
T4	127964	78	0	0
T6	290409	245	0	0
T7	210993	0	0	0
T8	289286	22	0	0
T9	5484	99	0	0
T10	4636	12	0	0
T11	2812	18	0	0
T12	0	1120	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	2773558	0	0
T1	83523	1202	0	0
T2	70351	775	0	0
T3	1392	14	0	0
T4	127964	24589	0	0
T6	290409	2009	0	0
T7	210993	1	0	0
T8	289286	114	0	0
T9	5484	93	0	0
T10	4636	81	0	0
T11	2812	19	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	195828	0	0
T1	83523	171	0	0
T2	70351	114	0	0
T3	1392	13	0	0
T4	127964	78	0	0
T6	290409	245	0	0
T7	210993	0	0	0
T8	289286	22	0	0
T9	5484	99	0	0
T10	4636	12	0	0
T11	2812	18	0	0
T12	0	1120	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	195828	0	0
T1	83523	171	0	0
T2	70351	114	0	0
T3	1392	13	0	0
T4	127964	78	0	0
T6	290409	245	0	0
T7	210993	0	0	0
T8	289286	22	0	0
T9	5484	99	0	0
T10	4636	12	0	0
T11	2812	18	0	0
T12	0	1120	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	533657	0	0
T1	83523	228	0	0
T2	70351	155	0	0
T3	1392	13	0	0
T4	127964	1088	0	0
T6	290409	268	0	0
T7	210993	0	0	0
T8	289286	38	0	0
T9	5484	106	0	0
T10	4636	12	0	0
T11	2812	18	0	0
T12	0	2993	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	195828	0	0
T1	83523	171	0	0
T2	70351	114	0	0
T3	1392	13	0	0
T4	127964	78	0	0
T6	290409	245	0	0
T7	210993	0	0	0
T8	289286	22	0	0
T9	5484	99	0	0
T10	4636	12	0	0
T11	2812	18	0	0
T12	0	1120	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	207889	0	0
GntImpliesValid_A	414178145	207889	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	207889	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	2879364	0	0
ReadyAndValidImplyGrant_A	414178145	207889	0	0
ReqAndReadyImplyGrant_A	414178145	207889	0	0
ReqImpliesValid_A	414178145	528813	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	207889	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	207889	0	0
T1	83523	195	0	0
T2	70351	194	0	0
T3	1392	9	0	0
T4	127964	86	0	0
T6	290409	690	0	0
T7	210993	0	0	0
T8	289286	19	0	0
T9	5484	101	0	0
T10	4636	15	0	0
T11	2812	13	0	0
T12	0	804	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	207889	0	0
T1	83523	195	0	0
T2	70351	194	0	0
T3	1392	9	0	0
T4	127964	86	0	0
T6	290409	690	0	0
T7	210993	0	0	0
T8	289286	19	0	0
T9	5484	101	0	0
T10	4636	15	0	0
T11	2812	13	0	0
T12	0	804	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	207889	0	0
T1	83523	195	0	0
T2	70351	194	0	0
T3	1392	9	0	0
T4	127964	86	0	0
T6	290409	690	0	0
T7	210993	0	0	0
T8	289286	19	0	0
T9	5484	101	0	0
T10	4636	15	0	0
T11	2812	13	0	0
T12	0	804	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	2879364	0	0
T1	83523	1468	0	0
T2	70351	1429	0	0
T3	1392	10	0	0
T4	127964	32091	0	0
T6	290409	3007	0	0
T7	210993	1	0	0
T8	289286	87	0	0
T9	5484	92	0	0
T10	4636	82	0	0
T11	2812	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	207889	0	0
T1	83523	195	0	0
T2	70351	194	0	0
T3	1392	9	0	0
T4	127964	86	0	0
T6	290409	690	0	0
T7	210993	0	0	0
T8	289286	19	0	0
T9	5484	101	0	0
T10	4636	15	0	0
T11	2812	13	0	0
T12	0	804	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	207889	0	0
T1	83523	195	0	0
T2	70351	194	0	0
T3	1392	9	0	0
T4	127964	86	0	0
T6	290409	690	0	0
T7	210993	0	0	0
T8	289286	19	0	0
T9	5484	101	0	0
T10	4636	15	0	0
T11	2812	13	0	0
T12	0	804	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	528813	0	0
T1	83523	272	0	0
T2	70351	208	0	0
T3	1392	9	0	0
T4	127964	1680	0	0
T6	290409	4079	0	0
T7	210993	0	0	0
T8	289286	21	0	0
T9	5484	111	0	0
T10	4636	19	0	0
T11	2812	13	0	0
T12	0	1526	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	207889	0	0
T1	83523	195	0	0
T2	70351	194	0	0
T3	1392	9	0	0
T4	127964	86	0	0
T6	290409	690	0	0
T7	210993	0	0	0
T8	289286	19	0	0
T9	5484	101	0	0
T10	4636	15	0	0
T11	2812	13	0	0
T12	0	804	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	206651	0	0
GntImpliesValid_A	414178145	206651	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	206651	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	2833168	0	0
ReadyAndValidImplyGrant_A	414178145	206651	0	0
ReqAndReadyImplyGrant_A	414178145	206651	0	0
ReqImpliesValid_A	414178145	588069	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	206651	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	206651	0	0
T1	83523	215	0	0
T2	70351	122	0	0
T3	1392	17	0	0
T4	127964	78	0	0
T6	290409	808	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	88	0	0
T10	4636	12	0	0
T11	2812	20	0	0
T12	0	935	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	206651	0	0
T1	83523	215	0	0
T2	70351	122	0	0
T3	1392	17	0	0
T4	127964	78	0	0
T6	290409	808	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	88	0	0
T10	4636	12	0	0
T11	2812	20	0	0
T12	0	935	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	206651	0	0
T1	83523	215	0	0
T2	70351	122	0	0
T3	1392	17	0	0
T4	127964	78	0	0
T6	290409	808	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	88	0	0
T10	4636	12	0	0
T11	2812	20	0	0
T12	0	935	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	2833168	0	0
T1	83523	1584	0	0
T2	70351	931	0	0
T3	1392	17	0	0
T4	127964	24618	0	0
T6	290409	5381	0	0
T7	210993	1	0	0
T8	289286	61	0	0
T9	5484	82	0	0
T10	4636	83	0	0
T11	2812	21	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	206651	0	0
T1	83523	215	0	0
T2	70351	122	0	0
T3	1392	17	0	0
T4	127964	78	0	0
T6	290409	808	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	88	0	0
T10	4636	12	0	0
T11	2812	20	0	0
T12	0	935	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	206651	0	0
T1	83523	215	0	0
T2	70351	122	0	0
T3	1392	17	0	0
T4	127964	78	0	0
T6	290409	808	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	88	0	0
T10	4636	12	0	0
T11	2812	20	0	0
T12	0	935	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	588069	0	0
T1	83523	300	0	0
T2	70351	157	0	0
T3	1392	18	0	0
T4	127964	673	0	0
T6	290409	2483	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	95	0	0
T10	4636	12	0	0
T11	2812	20	0	0
T12	0	1666	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	206651	0	0
T1	83523	215	0	0
T2	70351	122	0	0
T3	1392	17	0	0
T4	127964	78	0	0
T6	290409	808	0	0
T7	210993	0	0	0
T8	289286	14	0	0
T9	5484	88	0	0
T10	4636	12	0	0
T11	2812	20	0	0
T12	0	935	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	208253	0	0
GntImpliesValid_A	414178145	208253	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	208253	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	2889584	0	0
ReadyAndValidImplyGrant_A	414178145	208253	0	0
ReqAndReadyImplyGrant_A	414178145	208253	0	0
ReqImpliesValid_A	414178145	580485	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	208253	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	208253	0	0
T1	83523	186	0	0
T2	70351	131	0	0
T3	1392	16	0	0
T4	127964	110	0	0
T6	290409	269	0	0
T7	210993	0	0	0
T8	289286	17	0	0
T9	5484	131	0	0
T10	4636	24	0	0
T11	2812	14	0	0
T12	0	550	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	208253	0	0
T1	83523	186	0	0
T2	70351	131	0	0
T3	1392	16	0	0
T4	127964	110	0	0
T6	290409	269	0	0
T7	210993	0	0	0
T8	289286	17	0	0
T9	5484	131	0	0
T10	4636	24	0	0
T11	2812	14	0	0
T12	0	550	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	208253	0	0
T1	83523	186	0	0
T2	70351	131	0	0
T3	1392	16	0	0
T4	127964	110	0	0
T6	290409	269	0	0
T7	210993	0	0	0
T8	289286	17	0	0
T9	5484	131	0	0
T10	4636	24	0	0
T11	2812	14	0	0
T12	0	550	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	2889584	0	0
T1	83523	1378	0	0
T2	70351	950	0	0
T3	1392	16	0	0
T4	127964	39300	0	0
T6	290409	2126	0	0
T7	210993	1	0	0
T8	289286	63	0	0
T9	5484	121	0	0
T10	4636	161	0	0
T11	2812	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	208253	0	0
T1	83523	186	0	0
T2	70351	131	0	0
T3	1392	16	0	0
T4	127964	110	0	0
T6	290409	269	0	0
T7	210993	0	0	0
T8	289286	17	0	0
T9	5484	131	0	0
T10	4636	24	0	0
T11	2812	14	0	0
T12	0	550	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	208253	0	0
T1	83523	186	0	0
T2	70351	131	0	0
T3	1392	16	0	0
T4	127964	110	0	0
T6	290409	269	0	0
T7	210993	0	0	0
T8	289286	17	0	0
T9	5484	131	0	0
T10	4636	24	0	0
T11	2812	14	0	0
T12	0	550	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	580485	0	0
T1	83523	259	0	0
T2	70351	157	0	0
T3	1392	17	0	0
T4	127964	3187	0	0
T6	290409	292	0	0
T7	210993	0	0	0
T8	289286	17	0	0
T9	5484	142	0	0
T10	4636	26	0	0
T11	2812	14	0	0
T12	0	644	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	208253	0	0
T1	83523	186	0	0
T2	70351	131	0	0
T3	1392	16	0	0
T4	127964	110	0	0
T6	290409	269	0	0
T7	210993	0	0	0
T8	289286	17	0	0
T9	5484	131	0	0
T10	4636	24	0	0
T11	2812	14	0	0
T12	0	550	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	194318	0	0
GntImpliesValid_A	414178145	194318	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	194318	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	2751074	0	0
ReadyAndValidImplyGrant_A	414178145	194318	0	0
ReqAndReadyImplyGrant_A	414178145	194318	0	0
ReqImpliesValid_A	414178145	525172	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	194318	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	194318	0	0
T1	83523	213	0	0
T2	70351	142	0	0
T3	1392	11	0	0
T4	127964	72	0	0
T6	290409	239	0	0
T7	210993	0	0	0
T8	289286	20	0	0
T9	5484	88	0	0
T10	4636	16	0	0
T11	2812	14	0	0
T12	0	1078	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	194318	0	0
T1	83523	213	0	0
T2	70351	142	0	0
T3	1392	11	0	0
T4	127964	72	0	0
T6	290409	239	0	0
T7	210993	0	0	0
T8	289286	20	0	0
T9	5484	88	0	0
T10	4636	16	0	0
T11	2812	14	0	0
T12	0	1078	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	194318	0	0
T1	83523	213	0	0
T2	70351	142	0	0
T3	1392	11	0	0
T4	127964	72	0	0
T6	290409	239	0	0
T7	210993	0	0	0
T8	289286	20	0	0
T9	5484	88	0	0
T10	4636	16	0	0
T11	2812	14	0	0
T12	0	1078	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	2751074	0	0
T1	83523	1420	0	0
T2	70351	1201	0	0
T3	1392	12	0	0
T4	127964	23048	0	0
T6	290409	1889	0	0
T7	210993	1	0	0
T8	289286	89	0	0
T9	5484	86	0	0
T10	4636	171	0	0
T11	2812	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	194318	0	0
T1	83523	213	0	0
T2	70351	142	0	0
T3	1392	11	0	0
T4	127964	72	0	0
T6	290409	239	0	0
T7	210993	0	0	0
T8	289286	20	0	0
T9	5484	88	0	0
T10	4636	16	0	0
T11	2812	14	0	0
T12	0	1078	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	194318	0	0
T1	83523	213	0	0
T2	70351	142	0	0
T3	1392	11	0	0
T4	127964	72	0	0
T6	290409	239	0	0
T7	210993	0	0	0
T8	289286	20	0	0
T9	5484	88	0	0
T10	4636	16	0	0
T11	2812	14	0	0
T12	0	1078	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	525172	0	0
T1	83523	322	0	0
T2	70351	191	0	0
T3	1392	11	0	0
T4	127964	2059	0	0
T6	290409	260	0	0
T7	210993	0	0	0
T8	289286	23	0	0
T9	5484	91	0	0
T10	4636	21	0	0
T11	2812	14	0	0
T12	0	1920	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	194318	0	0
T1	83523	213	0	0
T2	70351	142	0	0
T3	1392	11	0	0
T4	127964	72	0	0
T6	290409	239	0	0
T7	210993	0	0	0
T8	289286	20	0	0
T9	5484	88	0	0
T10	4636	16	0	0
T11	2812	14	0	0
T12	0	1078	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	205181	0	0
GntImpliesValid_A	414178145	205181	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	205181	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	2861950	0	0
ReadyAndValidImplyGrant_A	414178145	205181	0	0
ReqAndReadyImplyGrant_A	414178145	205181	0	0
ReqImpliesValid_A	414178145	565803	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	205181	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	205181	0	0
T1	83523	176	0	0
T2	70351	113	0	0
T3	1392	12	0	0
T4	127964	80	0	0
T6	290409	788	0	0
T7	210993	0	0	0
T8	289286	9	0	0
T9	5484	91	0	0
T10	4636	11	0	0
T11	2812	7	0	0
T12	0	529	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	205181	0	0
T1	83523	176	0	0
T2	70351	113	0	0
T3	1392	12	0	0
T4	127964	80	0	0
T6	290409	788	0	0
T7	210993	0	0	0
T8	289286	9	0	0
T9	5484	91	0	0
T10	4636	11	0	0
T11	2812	7	0	0
T12	0	529	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	205181	0	0
T1	83523	176	0	0
T2	70351	113	0	0
T3	1392	12	0	0
T4	127964	80	0	0
T6	290409	788	0	0
T7	210993	0	0	0
T8	289286	9	0	0
T9	5484	91	0	0
T10	4636	11	0	0
T11	2812	7	0	0
T12	0	529	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	2861950	0	0
T1	83523	1326	0	0
T2	70351	865	0	0
T3	1392	11	0	0
T4	127964	27385	0	0
T6	290409	3100	0	0
T7	210993	1	0	0
T8	289286	31	0	0
T9	5484	90	0	0
T10	4636	85	0	0
T11	2812	8	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	205181	0	0
T1	83523	176	0	0
T2	70351	113	0	0
T3	1392	12	0	0
T4	127964	80	0	0
T6	290409	788	0	0
T7	210993	0	0	0
T8	289286	9	0	0
T9	5484	91	0	0
T10	4636	11	0	0
T11	2812	7	0	0
T12	0	529	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	205181	0	0
T1	83523	176	0	0
T2	70351	113	0	0
T3	1392	12	0	0
T4	127964	80	0	0
T6	290409	788	0	0
T7	210993	0	0	0
T8	289286	9	0	0
T9	5484	91	0	0
T10	4636	11	0	0
T11	2812	7	0	0
T12	0	529	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	565803	0	0
T1	83523	215	0	0
T2	70351	119	0	0
T3	1392	14	0	0
T4	127964	1531	0	0
T6	290409	2597	0	0
T7	210993	0	0	0
T8	289286	9	0	0
T9	5484	93	0	0
T10	4636	11	0	0
T11	2812	7	0	0
T12	0	648	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	205181	0	0
T1	83523	176	0	0
T2	70351	113	0	0
T3	1392	12	0	0
T4	127964	80	0	0
T6	290409	788	0	0
T7	210993	0	0	0
T8	289286	9	0	0
T9	5484	91	0	0
T10	4636	11	0	0
T11	2812	7	0	0
T12	0	529	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	203088	0	0
GntImpliesValid_A	414178145	203088	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	203088	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	2842632	0	0
ReadyAndValidImplyGrant_A	414178145	203088	0	0
ReqAndReadyImplyGrant_A	414178145	203088	0	0
ReqImpliesValid_A	414178145	562722	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	0	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	203088	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	203088	0	0
T1	83523	224	0	0
T2	70351	136	0	0
T3	1392	14	0	0
T4	127964	69	0	0
T6	290409	764	0	0
T7	210993	0	0	0
T8	289286	6	0	0
T9	5484	95	0	0
T10	4636	14	0	0
T11	2812	12	0	0
T12	0	2150	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	203088	0	0
T1	83523	224	0	0
T2	70351	136	0	0
T3	1392	14	0	0
T4	127964	69	0	0
T6	290409	764	0	0
T7	210993	0	0	0
T8	289286	6	0	0
T9	5484	95	0	0
T10	4636	14	0	0
T11	2812	12	0	0
T12	0	2150	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	203088	0	0
T1	83523	224	0	0
T2	70351	136	0	0
T3	1392	14	0	0
T4	127964	69	0	0
T6	290409	764	0	0
T7	210993	0	0	0
T8	289286	6	0	0
T9	5484	95	0	0
T10	4636	14	0	0
T11	2812	12	0	0
T12	0	2150	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	2842632	0	0
T1	83523	1532	0	0
T2	70351	890	0	0
T3	1392	15	0	0
T4	127964	24380	0	0
T6	290409	4885	0	0
T7	210993	1	0	0
T8	289286	26	0	0
T9	5484	91	0	0
T10	4636	115	0	0
T11	2812	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	203088	0	0
T1	83523	224	0	0
T2	70351	136	0	0
T3	1392	14	0	0
T4	127964	69	0	0
T6	290409	764	0	0
T7	210993	0	0	0
T8	289286	6	0	0
T9	5484	95	0	0
T10	4636	14	0	0
T11	2812	12	0	0
T12	0	2150	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	203088	0	0
T1	83523	224	0	0
T2	70351	136	0	0
T3	1392	14	0	0
T4	127964	69	0	0
T6	290409	764	0	0
T7	210993	0	0	0
T8	289286	6	0	0
T9	5484	95	0	0
T10	4636	14	0	0
T11	2812	12	0	0
T12	0	2150	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	562722	0	0
T1	83523	363	0	0
T2	70351	204	0	0
T3	1392	14	0	0
T4	127964	1166	0	0
T6	290409	2285	0	0
T7	210993	0	0	0
T8	289286	6	0	0
T9	5484	100	0	0
T10	4636	14	0	0
T11	2812	12	0	0
T12	0	12067	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	203088	0	0
T1	83523	224	0	0
T2	70351	136	0	0
T3	1392	14	0	0
T4	127964	69	0	0
T6	290409	764	0	0
T7	210993	0	0	0
T8	289286	6	0	0
T9	5484	95	0	0
T10	4636	14	0	0
T11	2812	12	0	0
T12	0	2150	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	809115	0	0
GntImpliesValid_A	414178145	809115	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	809115	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	10597953	0	0
ReadyAndValidImplyGrant_A	414178145	809115	0	0
ReqAndReadyImplyGrant_A	414178145	809115	0	0
ReqImpliesValid_A	414178145	2186404	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	15884	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	809115	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	809115	0	0
T1	83523	818	0	0
T2	70351	484	0	0
T3	1392	43	0	0
T4	127964	331	0	0
T6	290409	2569	0	0
T7	210993	869	0	0
T8	289286	89	0	0
T9	5484	409	0	0
T10	4636	51	0	0
T11	2812	39	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	809115	0	0
T1	83523	818	0	0
T2	70351	484	0	0
T3	1392	43	0	0
T4	127964	331	0	0
T6	290409	2569	0	0
T7	210993	869	0	0
T8	289286	89	0	0
T9	5484	409	0	0
T10	4636	51	0	0
T11	2812	39	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	809115	0	0
T1	83523	818	0	0
T2	70351	484	0	0
T3	1392	43	0	0
T4	127964	331	0	0
T6	290409	2569	0	0
T7	210993	869	0	0
T8	289286	89	0	0
T9	5484	409	0	0
T10	4636	51	0	0
T11	2812	39	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	10597953	0	0
T1	83523	5377	0	0
T2	70351	3315	0	0
T3	1392	1	0	0
T4	127964	109781	0	0
T6	290409	13849	0	0
T7	210993	2376	0	0
T8	289286	256	0	0
T9	5484	1	0	0
T10	4636	314	0	0
T11	2812	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	809115	0	0
T1	83523	818	0	0
T2	70351	484	0	0
T3	1392	43	0	0
T4	127964	331	0	0
T6	290409	2569	0	0
T7	210993	869	0	0
T8	289286	89	0	0
T9	5484	409	0	0
T10	4636	51	0	0
T11	2812	39	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	809115	0	0
T1	83523	818	0	0
T2	70351	484	0	0
T3	1392	43	0	0
T4	127964	331	0	0
T6	290409	2569	0	0
T7	210993	869	0	0
T8	289286	89	0	0
T9	5484	409	0	0
T10	4636	51	0	0
T11	2812	39	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	2186404	0	0
T1	83523	1525	0	0
T2	70351	619	0	0
T3	1392	43	0	0
T4	127964	10375	0	0
T6	290409	8615	0	0
T7	210993	1868	0	0
T8	289286	113	0	0
T9	5484	409	0	0
T10	4636	55	0	0
T11	2812	39	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	15884	0	900
T3	1392	2	0	1
T4	127964	0	0	1
T5	0	1	0	0
T6	290409	12	0	1
T7	210993	12	0	1
T8	289286	0	0	1
T9	5484	4	0	1
T10	4636	0	0	1
T11	2812	0	0	1
T12	337929	8	0	1
T13	309526	0	0	1
T15	0	29	0	0
T16	0	16	0	0
T17	0	4	0	0
T18	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	809115	0	0
T1	83523	818	0	0
T2	70351	484	0	0
T3	1392	43	0	0
T4	127964	331	0	0
T6	290409	2569	0	0
T7	210993	869	0	0
T8	289286	89	0	0
T9	5484	409	0	0
T10	4636	51	0	0
T11	2812	39	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414178145	414050719	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414178145	797324	0	0
GntImpliesValid_A	414178145	797324	0	0
GrantKnown_A	414178145	414050719	0	0
IdxKnown_A	414178145	414050719	0	0
IndexIsCorrect_A	414178145	797324	0	0
LockArbDecision_A	414178145	0	0	0
NoReadyValidNoGrant_A	414178145	349026209	0	0
ReadyAndValidImplyGrant_A	414178145	797324	0	0
ReqAndReadyImplyGrant_A	414178145	797324	0	0
ReqImpliesValid_A	414178145	12361623	0	0
ReqStaysHighUntilGranted0_M	414178145	0	0	0
RoundRobin_A	414178145	22809	0	900
ValidKnown_A	414178145	414050719	0	0
gen_data_port_assertion.DataFlow_A	414178145	797324	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	797324	0	0
T1	83523	792	0	0
T2	70351	464	0	0
T3	1392	36	0	0
T4	127964	339	0	0
T6	290409	2632	0	0
T7	210993	937	0	0
T8	289286	45	0	0
T9	5484	362	0	0
T10	4636	69	0	0
T11	2812	48	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	797324	0	0
T1	83523	792	0	0
T2	70351	464	0	0
T3	1392	36	0	0
T4	127964	339	0	0
T6	290409	2632	0	0
T7	210993	937	0	0
T8	289286	45	0	0
T9	5484	362	0	0
T10	4636	69	0	0
T11	2812	48	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	797324	0	0
T1	83523	792	0	0
T2	70351	464	0	0
T3	1392	36	0	0
T4	127964	339	0	0
T6	290409	2632	0	0
T7	210993	937	0	0
T8	289286	45	0	0
T9	5484	362	0	0
T10	4636	69	0	0
T11	2812	48	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	349026209	0	0
T1	83523	68426	0	0
T2	70351	60691	0	0
T3	1392	1	0	0
T4	127964	115522	0	0
T6	290409	239581	0	0
T7	210993	175406	0	0
T8	289286	240920	0	0
T9	5484	1	0	0
T10	4636	3609	0	0
T11	2812	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	797324	0	0
T1	83523	792	0	0
T2	70351	464	0	0
T3	1392	36	0	0
T4	127964	339	0	0
T6	290409	2632	0	0
T7	210993	937	0	0
T8	289286	45	0	0
T9	5484	362	0	0
T10	4636	69	0	0
T11	2812	48	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	797324	0	0
T1	83523	792	0	0
T2	70351	464	0	0
T3	1392	36	0	0
T4	127964	339	0	0
T6	290409	2632	0	0
T7	210993	937	0	0
T8	289286	45	0	0
T9	5484	362	0	0
T10	4636	69	0	0
T11	2812	48	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	12361623	0	0
T1	83523	5877	0	0
T2	70351	3640	0	0
T3	1392	36	0	0
T4	127964	122137	0	0
T6	290409	18876	0	0
T7	210993	4365	0	0
T8	289286	222	0	0
T9	5484	362	0	0
T10	4636	611	0	0
T11	2812	48	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	22809	0	900
T1	83523	3	0	1
T2	70351	0	0	1
T3	1392	0	0	1
T4	127964	0	0	1
T6	290409	59	0	1
T7	210993	9	0	1
T8	289286	0	0	1
T9	5484	6	0	1
T10	4636	0	0	1
T11	2812	0	0	1
T12	0	2	0	0
T13	0	22	0	0
T14	0	1	0	0
T15	0	27	0	0
T16	0	18	0	0
T17	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	414050719	0	0
T1	83523	83464	0	0
T2	70351	70312	0	0
T3	1392	1336	0	0
T4	127964	127956	0	0
T6	290409	290282	0	0
T7	210993	210992	0	0
T8	289286	289220	0	0
T9	5484	5452	0	0
T10	4636	4572	0	0
T11	2812	2733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414178145	797324	0	0
T1	83523	792	0	0
T2	70351	464	0	0
T3	1392	36	0	0
T4	127964	339	0	0
T6	290409	2632	0	0
T7	210993	937	0	0
T8	289286	45	0	0
T9	5484	362	0	0
T10	4636	69	0	0
T11	2812	48	0	0