Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1487420 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 236345 1 T1 14 T2 852 T3 18


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 585529 1 T1 54 T2 2040 T3 78
values[0x0] 553071 1 T1 40 T2 2003 T3 12
values[0x1] 585165 1 T1 39 T2 2083 T3 69


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1149689 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 574076 1 T1 41 T2 2026 T3 63


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27194 1 T1 6 T2 98 T3 3
valid_sources[0x01] 28279 1 T1 42 T2 102 T7 3
valid_sources[0x02] 27414 1 T1 10 T2 78 T3 4
valid_sources[0x03] 26513 1 T2 104 T7 3 T8 60
valid_sources[0x04] 27243 1 T1 12 T2 89 T3 1
valid_sources[0x05] 26781 1 T2 86 T3 5 T7 2
valid_sources[0x06] 27109 1 T1 3 T2 85 T3 2
valid_sources[0x07] 26045 1 T1 5 T2 86 T3 5
valid_sources[0x08] 26178 1 T2 109 T7 4 T8 78
valid_sources[0x09] 26884 1 T2 85 T3 3 T8 61
valid_sources[0x0a] 27942 1 T2 111 T3 4 T7 2
valid_sources[0x0b] 27323 1 T2 107 T7 2 T8 54
valid_sources[0x0c] 26911 1 T2 93 T3 1 T7 1
valid_sources[0x0d] 26100 1 T2 99 T3 2 T7 2
valid_sources[0x0e] 26660 1 T2 102 T3 2 T7 1
valid_sources[0x0f] 26386 1 T2 98 T3 2 T7 2
valid_sources[0x10] 27216 1 T2 78 T3 4 T7 6
valid_sources[0x11] 26043 1 T2 109 T3 6 T7 1
valid_sources[0x12] 26901 1 T1 4 T2 105 T3 1
valid_sources[0x13] 27104 1 T2 82 T3 5 T8 97
valid_sources[0x14] 26924 1 T1 1 T2 87 T3 2
valid_sources[0x15] 27657 1 T1 10 T2 77 T7 6
valid_sources[0x16] 27829 1 T2 95 T3 4 T7 1
valid_sources[0x17] 25827 1 T1 7 T2 84 T3 3
valid_sources[0x18] 27485 1 T2 105 T3 6 T7 7
valid_sources[0x19] 27081 1 T2 97 T3 2 T7 5
valid_sources[0x1a] 26598 1 T2 108 T3 5 T7 1
valid_sources[0x1b] 28247 1 T1 3 T2 98 T7 2
valid_sources[0x1c] 27111 1 T2 104 T3 3 T7 3
valid_sources[0x1d] 26399 1 T2 94 T3 3 T7 2
valid_sources[0x1e] 26627 1 T2 96 T3 5 T7 2
valid_sources[0x1f] 27040 1 T2 94 T3 2 T7 2
valid_sources[0x20] 26265 1 T2 91 T3 2 T7 4


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24978 1 T1 2 T2 84 T3 9
values[0x0] all_enables biggest_size 186186 1 T1 12 T2 680 T3 6
values[0x1] all_enables biggest_size 25181 1 T2 88 T3 3 T7 2


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1504043 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 244498 1 T1 17 T2 783 T3 14


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 599119 1 T1 31 T2 1879 T3 72
values[0x0] 550360 1 T1 37 T2 1822 T3 16
values[0x1] 599062 1 T1 35 T2 1919 T3 61


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1153863 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 594678 1 T1 37 T2 1833 T3 56


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27970 1 T2 108 T3 3 T8 94
valid_sources[0x01] 26896 1 T2 102 T3 4 T7 4
valid_sources[0x02] 27689 1 T2 68 T3 4 T7 2
valid_sources[0x03] 27118 1 T1 4 T2 83 T3 2
valid_sources[0x04] 27428 1 T1 1 T2 111 T3 1
valid_sources[0x05] 27968 1 T2 184 T3 3 T8 73
valid_sources[0x06] 27856 1 T2 29 T3 1 T7 5
valid_sources[0x07] 26389 1 T1 3 T2 104 T3 4
valid_sources[0x08] 27393 1 T1 1 T2 91 T7 4
valid_sources[0x09] 27519 1 T1 6 T2 62 T8 89
valid_sources[0x0a] 26973 1 T1 2 T2 117 T3 4
valid_sources[0x0b] 27396 1 T1 6 T2 55 T3 4
valid_sources[0x0c] 27095 1 T1 8 T2 33 T7 5
valid_sources[0x0d] 27486 1 T1 8 T2 45 T3 3
valid_sources[0x0e] 27426 1 T1 1 T2 138 T3 2
valid_sources[0x0f] 27280 1 T1 1 T2 66 T3 2
valid_sources[0x10] 27350 1 T1 1 T2 56 T3 2
valid_sources[0x11] 27416 1 T1 6 T2 142 T3 1
valid_sources[0x12] 26446 1 T1 3 T2 101 T3 1
valid_sources[0x13] 27599 1 T1 1 T2 146 T3 2
valid_sources[0x14] 27154 1 T1 3 T2 74 T3 1
valid_sources[0x15] 27168 1 T1 5 T2 92 T3 4
valid_sources[0x16] 27655 1 T2 95 T3 3 T7 1
valid_sources[0x17] 27403 1 T2 104 T3 6 T8 103
valid_sources[0x18] 27931 1 T2 70 T3 2 T8 68
valid_sources[0x19] 26989 1 T2 25 T3 2 T7 7
valid_sources[0x1a] 26904 1 T1 1 T2 68 T3 1
valid_sources[0x1b] 27650 1 T1 3 T2 90 T3 1
valid_sources[0x1c] 27927 1 T1 3 T2 118 T3 5
valid_sources[0x1d] 26621 1 T2 92 T3 1 T7 3
valid_sources[0x1e] 27487 1 T2 172 T3 2 T7 1
valid_sources[0x1f] 27161 1 T2 84 T3 1 T7 6
valid_sources[0x20] 25879 1 T2 64 T3 2 T8 65


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25797 1 T1 4 T2 86 T3 4
values[0x0] all_enables biggest_size 192910 1 T1 13 T2 620 T3 6
values[0x1] all_enables biggest_size 25791 1 T2 77 T3 4 T7 2


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1496325 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 238466 1 T1 30 T2 832 T3 20


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 588771 1 T1 63 T2 1931 T3 83
values[0x0] 557603 1 T1 66 T2 1965 T3 18
values[0x1] 588417 1 T1 54 T2 1888 T3 84


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1155667 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 579124 1 T1 61 T2 1982 T3 79


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27036 1 T1 2 T2 71 T3 2
valid_sources[0x01] 26846 1 T2 88 T3 3 T7 7
valid_sources[0x02] 27237 1 T1 3 T2 71 T3 1
valid_sources[0x03] 26742 1 T1 1 T2 70 T3 1
valid_sources[0x04] 26888 1 T2 90 T3 1 T7 2
valid_sources[0x05] 26609 1 T1 2 T2 69 T3 8
valid_sources[0x06] 26879 1 T1 2 T2 107 T3 3
valid_sources[0x07] 27182 1 T1 11 T2 83 T3 2
valid_sources[0x08] 27232 1 T2 63 T3 2 T8 63
valid_sources[0x09] 27926 1 T1 6 T2 80 T3 3
valid_sources[0x0a] 27005 1 T1 5 T2 71 T3 3
valid_sources[0x0b] 27401 1 T1 1 T2 44 T3 3
valid_sources[0x0c] 26384 1 T1 2 T2 80 T3 3
valid_sources[0x0d] 27009 1 T2 125 T8 91 T9 12
valid_sources[0x0e] 27077 1 T1 2 T2 71 T3 3
valid_sources[0x0f] 27568 1 T2 87 T3 3 T8 91
valid_sources[0x10] 27318 1 T2 110 T8 84 T9 57
valid_sources[0x11] 28463 1 T1 1 T2 161 T3 5
valid_sources[0x12] 27180 1 T1 1 T2 151 T3 3
valid_sources[0x13] 27594 1 T1 1 T2 99 T3 4
valid_sources[0x14] 26074 1 T2 117 T3 1 T8 74
valid_sources[0x15] 26452 1 T1 10 T2 101 T3 4
valid_sources[0x16] 26930 1 T1 5 T2 116 T3 4
valid_sources[0x17] 26730 1 T1 13 T2 154 T3 6
valid_sources[0x18] 26776 1 T1 2 T2 56 T3 5
valid_sources[0x19] 26828 1 T1 4 T2 108 T3 4
valid_sources[0x1a] 26434 1 T1 4 T2 118 T3 3
valid_sources[0x1b] 27840 1 T1 2 T2 52 T3 3
valid_sources[0x1c] 26498 1 T1 5 T2 93 T3 7
valid_sources[0x1d] 26957 1 T2 121 T8 64 T9 16
valid_sources[0x1e] 26847 1 T1 3 T2 95 T3 2
valid_sources[0x1f] 26698 1 T1 5 T2 130 T8 78
valid_sources[0x20] 26777 1 T1 1 T2 72 T3 4


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24996 1 T1 2 T2 76 T3 8
values[0x0] all_enables biggest_size 188026 1 T1 23 T2 662 T3 7
values[0x1] all_enables biggest_size 25444 1 T1 5 T2 94 T3 5

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%