Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7641041	0	0
GntImpliesValid_A	2147483647	7641041	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7641041	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	462473754	0	0
ReadyAndValidImplyGrant_A	2147483647	7641041	0	0
ReqAndReadyImplyGrant_A	2147483647	7641041	0	0
ReqImpliesValid_A	2147483647	33285612	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	42531	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7641041	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	11320248	11318808	0	0
T2	3486840	3486072	0	0
T3	2467656	2467200	0	0
T7	8210808	8210304	0	0
T8	3402384	3401352	0	0
T9	2688552	2688384	0	0
T10	8166648	8165952	0	0
T11	5603640	5603568	0	0
T12	1267608	1264656	0	0
T13	381936	380760	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7641041	0	0
T1	11320248	419	0	0
T2	3486840	13709	0	0
T3	2467656	10752	0	0
T7	8210808	500	0	0
T8	3402384	14630	0	0
T9	2688552	7412	0	0
T10	8166648	505	0	0
T11	5603640	7031	0	0
T12	1267608	31350	0	0
T13	381936	8109	0	0
T14	0	759	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7641041	0	0
T1	11320248	419	0	0
T2	3486840	13709	0	0
T3	2467656	10752	0	0
T7	8210808	500	0	0
T8	3402384	14630	0	0
T9	2688552	7412	0	0
T10	8166648	505	0	0
T11	5603640	7031	0	0
T12	1267608	31350	0	0
T13	381936	8109	0	0
T14	0	759	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	11320248	11318808	0	0
T2	3486840	3486072	0	0
T3	2467656	2467200	0	0
T7	8210808	8210304	0	0
T8	3402384	3401352	0	0
T9	2688552	2688384	0	0
T10	8166648	8165952	0	0
T11	5603640	5603568	0	0
T12	1267608	1264656	0	0
T13	381936	380760	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	11320248	11318808	0	0
T2	3486840	3486072	0	0
T3	2467656	2467200	0	0
T7	8210808	8210304	0	0
T8	3402384	3401352	0	0
T9	2688552	2688384	0	0
T10	8166648	8165952	0	0
T11	5603640	5603568	0	0
T12	1267608	1264656	0	0
T13	381936	380760	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7641041	0	0
T1	11320248	419	0	0
T2	3486840	13709	0	0
T3	2467656	10752	0	0
T7	8210808	500	0	0
T8	3402384	14630	0	0
T9	2688552	7412	0	0
T10	8166648	505	0	0
T11	5603640	7031	0	0
T12	1267608	31350	0	0
T13	381936	8109	0	0
T14	0	759	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	462473754	0	0
T1	11320248	585727	0	0
T2	3486840	211384	0	0
T3	2467656	153768	0	0
T7	8210808	286950	0	0
T8	3402384	139896	0	0
T9	2688552	144460	0	0
T10	8166648	285361	0	0
T11	5603640	224812	0	0
T12	1267608	28717	0	0
T13	381936	11511	0	0
T14	0	912	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7641041	0	0
T1	11320248	419	0	0
T2	3486840	13709	0	0
T3	2467656	10752	0	0
T7	8210808	500	0	0
T8	3402384	14630	0	0
T9	2688552	7412	0	0
T10	8166648	505	0	0
T11	5603640	7031	0	0
T12	1267608	31350	0	0
T13	381936	8109	0	0
T14	0	759	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7641041	0	0
T1	11320248	419	0	0
T2	3486840	13709	0	0
T3	2467656	10752	0	0
T7	8210808	500	0	0
T8	3402384	14630	0	0
T9	2688552	7412	0	0
T10	8166648	505	0	0
T11	5603640	7031	0	0
T12	1267608	31350	0	0
T13	381936	8109	0	0
T14	0	759	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33285612	0	0
T1	11320248	24871	0	0
T2	3486840	30703	0	0
T3	2467656	22424	0	0
T7	8210808	807	0	0
T8	3402384	101612	0	0
T9	2688552	13725	0	0
T10	8166648	888	0	0
T11	5603640	11728	0	0
T12	1267608	40741	0	0
T13	381936	9645	0	0
T14	0	909	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42531	0	21600
T2	145285	3	0	1
T3	205638	1	0	2
T4	0	1	0	0
T7	684234	0	0	2
T8	283532	31	0	2
T9	224046	0	0	2
T10	680554	0	0	2
T11	466970	0	0	2
T12	105634	123	0	2
T13	31828	38	0	2
T14	14086	17	0	2
T15	0	5	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	23	0	0
T19	0	1	0	0
T20	0	17	0	0
T21	0	9	0	0
T22	0	12	0	0
T23	133957	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	11320248	11318808	0	0
T2	3486840	3486072	0	0
T3	2467656	2467200	0	0
T7	8210808	8210304	0	0
T8	3402384	3401352	0	0
T9	2688552	2688384	0	0
T10	8166648	8165952	0	0
T11	5603640	5603568	0	0
T12	1267608	1264656	0	0
T13	381936	380760	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7641041	0	0
T1	11320248	419	0	0
T2	3486840	13709	0	0
T3	2467656	10752	0	0
T7	8210808	500	0	0
T8	3402384	14630	0	0
T9	2688552	7412	0	0
T10	8166648	505	0	0
T11	5603640	7031	0	0
T12	1267608	31350	0	0
T13	381936	8109	0	0
T14	0	759	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	866280	0	0
GntImpliesValid_A	430352682	866280	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	866280	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	11787329	0	0
ReadyAndValidImplyGrant_A	430352682	866280	0	0
ReqAndReadyImplyGrant_A	430352682	866280	0	0
ReqImpliesValid_A	430352682	2383205	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	866280	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	866280	0	0
T1	471677	34	0	0
T2	145285	1480	0	0
T3	102819	1177	0	0
T7	342117	62	0	0
T8	141766	1093	0	0
T9	112023	769	0	0
T10	340277	54	0	0
T11	233485	794	0	0
T12	52817	3646	0	0
T13	15914	881	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	866280	0	0
T1	471677	34	0	0
T2	145285	1480	0	0
T3	102819	1177	0	0
T7	342117	62	0	0
T8	141766	1093	0	0
T9	112023	769	0	0
T10	340277	54	0	0
T11	233485	794	0	0
T12	52817	3646	0	0
T13	15914	881	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	866280	0	0
T1	471677	34	0	0
T2	145285	1480	0	0
T3	102819	1177	0	0
T7	342117	62	0	0
T8	141766	1093	0	0
T9	112023	769	0	0
T10	340277	54	0	0
T11	233485	794	0	0
T12	52817	3646	0	0
T13	15914	881	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	11787329	0	0
T1	471677	15193	0	0
T2	145285	11227	0	0
T3	102819	8142	0	0
T7	342117	217	0	0
T8	141766	7506	0	0
T9	112023	5535	0	0
T10	340277	203	0	0
T11	233485	3332	0	0
T12	52817	2334	0	0
T13	15914	664	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	866280	0	0
T1	471677	34	0	0
T2	145285	1480	0	0
T3	102819	1177	0	0
T7	342117	62	0	0
T8	141766	1093	0	0
T9	112023	769	0	0
T10	340277	54	0	0
T11	233485	794	0	0
T12	52817	3646	0	0
T13	15914	881	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	866280	0	0
T1	471677	34	0	0
T2	145285	1480	0	0
T3	102819	1177	0	0
T7	342117	62	0	0
T8	141766	1093	0	0
T9	112023	769	0	0
T10	340277	54	0	0
T11	233485	794	0	0
T12	52817	3646	0	0
T13	15914	881	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	2383205	0	0
T1	471677	1474	0	0
T2	145285	2441	0	0
T3	102819	1900	0	0
T7	342117	108	0	0
T8	141766	1733	0	0
T9	112023	933	0	0
T10	340277	64	0	0
T11	233485	1100	0	0
T12	52817	4960	0	0
T13	15914	1099	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	866280	0	0
T1	471677	34	0	0
T2	145285	1480	0	0
T3	102819	1177	0	0
T7	342117	62	0	0
T8	141766	1093	0	0
T9	112023	769	0	0
T10	340277	54	0	0
T11	233485	794	0	0
T12	52817	3646	0	0
T13	15914	881	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	840588	0	0
GntImpliesValid_A	430352682	840588	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	840588	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	11794606	0	0
ReadyAndValidImplyGrant_A	430352682	840588	0	0
ReqAndReadyImplyGrant_A	430352682	840588	0	0
ReqImpliesValid_A	430352682	2355445	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	840588	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	840588	0	0
T1	471677	42	0	0
T2	145285	1472	0	0
T3	102819	1180	0	0
T7	342117	41	0	0
T8	141766	1085	0	0
T9	112023	830	0	0
T10	340277	72	0	0
T11	233485	796	0	0
T12	52817	3610	0	0
T13	15914	874	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	840588	0	0
T1	471677	42	0	0
T2	145285	1472	0	0
T3	102819	1180	0	0
T7	342117	41	0	0
T8	141766	1085	0	0
T9	112023	830	0	0
T10	340277	72	0	0
T11	233485	796	0	0
T12	52817	3610	0	0
T13	15914	874	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	840588	0	0
T1	471677	42	0	0
T2	145285	1472	0	0
T3	102819	1180	0	0
T7	342117	41	0	0
T8	141766	1085	0	0
T9	112023	830	0	0
T10	340277	72	0	0
T11	233485	796	0	0
T12	52817	3610	0	0
T13	15914	874	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	11794606	0	0
T1	471677	11878	0	0
T2	145285	10300	0	0
T3	102819	8466	0	0
T7	342117	163	0	0
T8	141766	7957	0	0
T9	112023	5989	0	0
T10	340277	309	0	0
T11	233485	3323	0	0
T12	52817	2701	0	0
T13	15914	662	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	840588	0	0
T1	471677	42	0	0
T2	145285	1472	0	0
T3	102819	1180	0	0
T7	342117	41	0	0
T8	141766	1085	0	0
T9	112023	830	0	0
T10	340277	72	0	0
T11	233485	796	0	0
T12	52817	3610	0	0
T13	15914	874	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	840588	0	0
T1	471677	42	0	0
T2	145285	1472	0	0
T3	102819	1180	0	0
T7	342117	41	0	0
T8	141766	1085	0	0
T9	112023	830	0	0
T10	340277	72	0	0
T11	233485	796	0	0
T12	52817	3610	0	0
T13	15914	874	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	2355445	0	0
T1	471677	2099	0	0
T2	145285	2400	0	0
T3	102819	1950	0	0
T7	342117	48	0	0
T8	141766	1854	0	0
T9	112023	979	0	0
T10	340277	100	0	0
T11	233485	1099	0	0
T12	52817	4521	0	0
T13	15914	1087	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	840588	0	0
T1	471677	42	0	0
T2	145285	1472	0	0
T3	102819	1180	0	0
T7	342117	41	0	0
T8	141766	1085	0	0
T9	112023	830	0	0
T10	340277	72	0	0
T11	233485	796	0	0
T12	52817	3610	0	0
T13	15914	874	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	205961	0	0
GntImpliesValid_A	430352682	205961	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	205961	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	2985087	0	0
ReadyAndValidImplyGrant_A	430352682	205961	0	0
ReqAndReadyImplyGrant_A	430352682	205961	0	0
ReqImpliesValid_A	430352682	538611	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	205961	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	205961	0	0
T1	471677	12	0	0
T2	145285	330	0	0
T3	102819	311	0	0
T7	342117	24	0	0
T8	141766	508	0	0
T9	112023	178	0	0
T10	340277	20	0	0
T11	233485	234	0	0
T12	52817	464	0	0
T13	15914	230	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	205961	0	0
T1	471677	12	0	0
T2	145285	330	0	0
T3	102819	311	0	0
T7	342117	24	0	0
T8	141766	508	0	0
T9	112023	178	0	0
T10	340277	20	0	0
T11	233485	234	0	0
T12	52817	464	0	0
T13	15914	230	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	205961	0	0
T1	471677	12	0	0
T2	145285	330	0	0
T3	102819	311	0	0
T7	342117	24	0	0
T8	141766	508	0	0
T9	112023	178	0	0
T10	340277	20	0	0
T11	233485	234	0	0
T12	52817	464	0	0
T13	15914	230	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	2985087	0	0
T1	471677	3489	0	0
T2	145285	2296	0	0
T3	102819	2323	0	0
T7	342117	104	0	0
T8	141766	689	0	0
T9	112023	1427	0	0
T10	340277	80	0	0
T11	233485	1052	0	0
T12	52817	458	0	0
T13	15914	210	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	205961	0	0
T1	471677	12	0	0
T2	145285	330	0	0
T3	102819	311	0	0
T7	342117	24	0	0
T8	141766	508	0	0
T9	112023	178	0	0
T10	340277	20	0	0
T11	233485	234	0	0
T12	52817	464	0	0
T13	15914	230	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	205961	0	0
T1	471677	12	0	0
T2	145285	330	0	0
T3	102819	311	0	0
T7	342117	24	0	0
T8	141766	508	0	0
T9	112023	178	0	0
T10	340277	20	0	0
T11	233485	234	0	0
T12	52817	464	0	0
T13	15914	230	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	538611	0	0
T1	471677	12	0	0
T2	145285	405	0	0
T3	102819	439	0	0
T7	342117	33	0	0
T8	141766	5212	0	0
T9	112023	178	0	0
T10	340277	22	0	0
T11	233485	281	0	0
T12	52817	472	0	0
T13	15914	251	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	205961	0	0
T1	471677	12	0	0
T2	145285	330	0	0
T3	102819	311	0	0
T7	342117	24	0	0
T8	141766	508	0	0
T9	112023	178	0	0
T10	340277	20	0	0
T11	233485	234	0	0
T12	52817	464	0	0
T13	15914	230	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	214222	0	0
GntImpliesValid_A	430352682	214222	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	214222	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	2905633	0	0
ReadyAndValidImplyGrant_A	430352682	214222	0	0
ReqAndReadyImplyGrant_A	430352682	214222	0	0
ReqImpliesValid_A	430352682	594232	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	214222	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	214222	0	0
T1	471677	10	0	0
T2	145285	328	0	0
T3	102819	334	0	0
T7	342117	8	0	0
T8	141766	511	0	0
T9	112023	227	0	0
T10	340277	15	0	0
T11	233485	211	0	0
T12	52817	471	0	0
T13	15914	217	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	214222	0	0
T1	471677	10	0	0
T2	145285	328	0	0
T3	102819	334	0	0
T7	342117	8	0	0
T8	141766	511	0	0
T9	112023	227	0	0
T10	340277	15	0	0
T11	233485	211	0	0
T12	52817	471	0	0
T13	15914	217	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	214222	0	0
T1	471677	10	0	0
T2	145285	328	0	0
T3	102819	334	0	0
T7	342117	8	0	0
T8	141766	511	0	0
T9	112023	227	0	0
T10	340277	15	0	0
T11	233485	211	0	0
T12	52817	471	0	0
T13	15914	217	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	2905633	0	0
T1	471677	1882	0	0
T2	145285	2396	0	0
T3	102819	2662	0	0
T7	342117	36	0	0
T8	141766	1270	0	0
T9	112023	1714	0	0
T10	340277	72	0	0
T11	233485	921	0	0
T12	52817	467	0	0
T13	15914	203	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	214222	0	0
T1	471677	10	0	0
T2	145285	328	0	0
T3	102819	334	0	0
T7	342117	8	0	0
T8	141766	511	0	0
T9	112023	227	0	0
T10	340277	15	0	0
T11	233485	211	0	0
T12	52817	471	0	0
T13	15914	217	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	214222	0	0
T1	471677	10	0	0
T2	145285	328	0	0
T3	102819	334	0	0
T7	342117	8	0	0
T8	141766	511	0	0
T9	112023	227	0	0
T10	340277	15	0	0
T11	233485	211	0	0
T12	52817	471	0	0
T13	15914	217	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	594232	0	0
T1	471677	10	0	0
T2	145285	451	0	0
T3	102819	415	0	0
T7	342117	8	0	0
T8	141766	2186	0	0
T9	112023	258	0	0
T10	340277	15	0	0
T11	233485	259	0	0
T12	52817	477	0	0
T13	15914	232	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	214222	0	0
T1	471677	10	0	0
T2	145285	328	0	0
T3	102819	334	0	0
T7	342117	8	0	0
T8	141766	511	0	0
T9	112023	227	0	0
T10	340277	15	0	0
T11	233485	211	0	0
T12	52817	471	0	0
T13	15914	217	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	209967	0	0
GntImpliesValid_A	430352682	209967	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	209967	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	4630787	0	0
ReadyAndValidImplyGrant_A	430352682	209967	0	0
ReqAndReadyImplyGrant_A	430352682	209967	0	0
ReqImpliesValid_A	430352682	975051	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	209967	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209967	0	0
T1	471677	12	0	0
T2	145285	353	0	0
T3	102819	298	0	0
T7	342117	12	0	0
T8	141766	0	0	0
T9	112023	210	0	0
T10	340277	9	0	0
T11	233485	216	0	0
T12	52817	417	0	0
T13	15914	201	0	0
T14	0	117	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209967	0	0
T1	471677	12	0	0
T2	145285	353	0	0
T3	102819	298	0	0
T7	342117	12	0	0
T8	141766	0	0	0
T9	112023	210	0	0
T10	340277	9	0	0
T11	233485	216	0	0
T12	52817	417	0	0
T13	15914	201	0	0
T14	0	117	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209967	0	0
T1	471677	12	0	0
T2	145285	353	0	0
T3	102819	298	0	0
T7	342117	12	0	0
T8	141766	0	0	0
T9	112023	210	0	0
T10	340277	9	0	0
T11	233485	216	0	0
T12	52817	417	0	0
T13	15914	201	0	0
T14	0	117	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	4630787	0	0
T1	471677	3422	0	0
T2	145285	3227	0	0
T3	102819	1312	0	0
T7	342117	106	0	0
T8	141766	0	0	0
T9	112023	1725	0	0
T10	340277	72	0	0
T11	233485	2161	0	0
T12	52817	2182	0	0
T13	15914	1587	0	0
T14	0	504	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209967	0	0
T1	471677	12	0	0
T2	145285	353	0	0
T3	102819	298	0	0
T7	342117	12	0	0
T8	141766	0	0	0
T9	112023	210	0	0
T10	340277	9	0	0
T11	233485	216	0	0
T12	52817	417	0	0
T13	15914	201	0	0
T14	0	117	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209967	0	0
T1	471677	12	0	0
T2	145285	353	0	0
T3	102819	298	0	0
T7	342117	12	0	0
T8	141766	0	0	0
T9	112023	210	0	0
T10	340277	9	0	0
T11	233485	216	0	0
T12	52817	417	0	0
T13	15914	201	0	0
T14	0	117	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	975051	0	0
T1	471677	12	0	0
T2	145285	483	0	0
T3	102819	318	0	0
T7	342117	12	0	0
T8	141766	0	0	0
T9	112023	210	0	0
T10	340277	16	0	0
T11	233485	395	0	0
T12	52817	507	0	0
T13	15914	428	0	0
T14	0	183	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209967	0	0
T1	471677	12	0	0
T2	145285	353	0	0
T3	102819	298	0	0
T7	342117	12	0	0
T8	141766	0	0	0
T9	112023	210	0	0
T10	340277	9	0	0
T11	233485	216	0	0
T12	52817	417	0	0
T13	15914	201	0	0
T14	0	117	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	200717	0	0
GntImpliesValid_A	430352682	200717	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	200717	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	4719780	0	0
ReadyAndValidImplyGrant_A	430352682	200717	0	0
ReqAndReadyImplyGrant_A	430352682	200717	0	0
ReqImpliesValid_A	430352682	1067056	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	200717	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	200717	0	0
T1	471677	12	0	0
T2	145285	328	0	0
T3	102819	317	0	0
T7	342117	15	0	0
T8	141766	0	0	0
T9	112023	209	0	0
T10	340277	11	0	0
T11	233485	195	0	0
T12	52817	473	0	0
T13	15914	205	0	0
T14	0	130	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	200717	0	0
T1	471677	12	0	0
T2	145285	328	0	0
T3	102819	317	0	0
T7	342117	15	0	0
T8	141766	0	0	0
T9	112023	209	0	0
T10	340277	11	0	0
T11	233485	195	0	0
T12	52817	473	0	0
T13	15914	205	0	0
T14	0	130	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	200717	0	0
T1	471677	12	0	0
T2	145285	328	0	0
T3	102819	317	0	0
T7	342117	15	0	0
T8	141766	0	0	0
T9	112023	209	0	0
T10	340277	11	0	0
T11	233485	195	0	0
T12	52817	473	0	0
T13	15914	205	0	0
T14	0	130	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	4719780	0	0
T1	471677	8318	0	0
T2	145285	6101	0	0
T3	102819	2087	0	0
T7	342117	81	0	0
T8	141766	0	0	0
T9	112023	945	0	0
T10	340277	328	0	0
T11	233485	3069	0	0
T12	52817	3437	0	0
T13	15914	1947	0	0
T14	0	408	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	200717	0	0
T1	471677	12	0	0
T2	145285	328	0	0
T3	102819	317	0	0
T7	342117	15	0	0
T8	141766	0	0	0
T9	112023	209	0	0
T10	340277	11	0	0
T11	233485	195	0	0
T12	52817	473	0	0
T13	15914	205	0	0
T14	0	130	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	200717	0	0
T1	471677	12	0	0
T2	145285	328	0	0
T3	102819	317	0	0
T7	342117	15	0	0
T8	141766	0	0	0
T9	112023	209	0	0
T10	340277	11	0	0
T11	233485	195	0	0
T12	52817	473	0	0
T13	15914	205	0	0
T14	0	130	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	1067056	0	0
T1	471677	1292	0	0
T2	145285	852	0	0
T3	102819	354	0	0
T7	342117	23	0	0
T8	141766	0	0	0
T9	112023	209	0	0
T10	340277	11	0	0
T11	233485	475	0	0
T12	52817	627	0	0
T13	15914	361	0	0
T14	0	183	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	200717	0	0
T1	471677	12	0	0
T2	145285	328	0	0
T3	102819	317	0	0
T7	342117	15	0	0
T8	141766	0	0	0
T9	112023	209	0	0
T10	340277	11	0	0
T11	233485	195	0	0
T12	52817	473	0	0
T13	15914	205	0	0
T14	0	130	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	218033	0	0
GntImpliesValid_A	430352682	218033	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	218033	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	5051269	0	0
ReadyAndValidImplyGrant_A	430352682	218033	0	0
ReqAndReadyImplyGrant_A	430352682	218033	0	0
ReqImpliesValid_A	430352682	1090478	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	218033	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	218033	0	0
T1	471677	8	0	0
T2	145285	336	0	0
T3	102819	307	0	0
T7	342117	17	0	0
T8	141766	475	0	0
T9	112023	218	0	0
T10	340277	12	0	0
T11	233485	176	0	0
T12	52817	932	0	0
T13	15914	229	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	218033	0	0
T1	471677	8	0	0
T2	145285	336	0	0
T3	102819	307	0	0
T7	342117	17	0	0
T8	141766	475	0	0
T9	112023	218	0	0
T10	340277	12	0	0
T11	233485	176	0	0
T12	52817	932	0	0
T13	15914	229	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	218033	0	0
T1	471677	8	0	0
T2	145285	336	0	0
T3	102819	307	0	0
T7	342117	17	0	0
T8	141766	475	0	0
T9	112023	218	0	0
T10	340277	12	0	0
T11	233485	176	0	0
T12	52817	932	0	0
T13	15914	229	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	5051269	0	0
T1	471677	6142	0	0
T2	145285	3419	0	0
T3	102819	1254	0	0
T7	342117	237	0	0
T8	141766	543	0	0
T9	112023	2509	0	0
T10	340277	69	0	0
T11	233485	1280	0	0
T12	52817	3070	0	0
T13	15914	1821	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	218033	0	0
T1	471677	8	0	0
T2	145285	336	0	0
T3	102819	307	0	0
T7	342117	17	0	0
T8	141766	475	0	0
T9	112023	218	0	0
T10	340277	12	0	0
T11	233485	176	0	0
T12	52817	932	0	0
T13	15914	229	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	218033	0	0
T1	471677	8	0	0
T2	145285	336	0	0
T3	102819	307	0	0
T7	342117	17	0	0
T8	141766	475	0	0
T9	112023	218	0	0
T10	340277	12	0	0
T11	233485	176	0	0
T12	52817	932	0	0
T13	15914	229	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	1090478	0	0
T1	471677	8	0	0
T2	145285	447	0	0
T3	102819	331	0	0
T7	342117	51	0	0
T8	141766	3666	0	0
T9	112023	218	0	0
T10	340277	23	0	0
T11	233485	237	0	0
T12	52817	3803	0	0
T13	15914	517	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	218033	0	0
T1	471677	8	0	0
T2	145285	336	0	0
T3	102819	307	0	0
T7	342117	17	0	0
T8	141766	475	0	0
T9	112023	218	0	0
T10	340277	12	0	0
T11	233485	176	0	0
T12	52817	932	0	0
T13	15914	229	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	222084	0	0
GntImpliesValid_A	430352682	222084	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	222084	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	4881253	0	0
ReadyAndValidImplyGrant_A	430352682	222084	0	0
ReqAndReadyImplyGrant_A	430352682	222084	0	0
ReqImpliesValid_A	430352682	1078599	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	222084	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	222084	0	0
T1	471677	15	0	0
T2	145285	374	0	0
T3	102819	303	0	0
T7	342117	15	0	0
T8	141766	1396	0	0
T9	112023	216	0	0
T10	340277	14	0	0
T11	233485	193	0	0
T12	52817	488	0	0
T13	15914	252	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	222084	0	0
T1	471677	15	0	0
T2	145285	374	0	0
T3	102819	303	0	0
T7	342117	15	0	0
T8	141766	1396	0	0
T9	112023	216	0	0
T10	340277	14	0	0
T11	233485	193	0	0
T12	52817	488	0	0
T13	15914	252	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	222084	0	0
T1	471677	15	0	0
T2	145285	374	0	0
T3	102819	303	0	0
T7	342117	15	0	0
T8	141766	1396	0	0
T9	112023	216	0	0
T10	340277	14	0	0
T11	233485	193	0	0
T12	52817	488	0	0
T13	15914	252	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	4881253	0	0
T1	471677	7601	0	0
T2	145285	4823	0	0
T3	102819	2560	0	0
T7	342117	69	0	0
T8	141766	2133	0	0
T9	112023	939	0	0
T10	340277	138	0	0
T11	233485	1288	0	0
T12	52817	3521	0	0
T13	15914	1385	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	222084	0	0
T1	471677	15	0	0
T2	145285	374	0	0
T3	102819	303	0	0
T7	342117	15	0	0
T8	141766	1396	0	0
T9	112023	216	0	0
T10	340277	14	0	0
T11	233485	193	0	0
T12	52817	488	0	0
T13	15914	252	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	222084	0	0
T1	471677	15	0	0
T2	145285	374	0	0
T3	102819	303	0	0
T7	342117	15	0	0
T8	141766	1396	0	0
T9	112023	216	0	0
T10	340277	14	0	0
T11	233485	193	0	0
T12	52817	488	0	0
T13	15914	252	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	1078599	0	0
T1	471677	1166	0	0
T2	145285	548	0	0
T3	102819	399	0	0
T7	342117	23	0	0
T8	141766	9488	0	0
T9	112023	223	0	0
T10	340277	32	0	0
T11	233485	336	0	0
T12	52817	670	0	0
T13	15914	484	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	222084	0	0
T1	471677	15	0	0
T2	145285	374	0	0
T3	102819	303	0	0
T7	342117	15	0	0
T8	141766	1396	0	0
T9	112023	216	0	0
T10	340277	14	0	0
T11	233485	193	0	0
T12	52817	488	0	0
T13	15914	252	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	218559	0	0
GntImpliesValid_A	430352682	218559	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	218559	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	2932381	0	0
ReadyAndValidImplyGrant_A	430352682	218559	0	0
ReqAndReadyImplyGrant_A	430352682	218559	0	0
ReqImpliesValid_A	430352682	623202	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	218559	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	218559	0	0
T1	471677	19	0	0
T2	145285	323	0	0
T3	102819	299	0	0
T7	342117	18	0	0
T8	141766	994	0	0
T9	112023	202	0	0
T10	340277	14	0	0
T11	233485	196	0	0
T12	52817	464	0	0
T13	15914	258	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	218559	0	0
T1	471677	19	0	0
T2	145285	323	0	0
T3	102819	299	0	0
T7	342117	18	0	0
T8	141766	994	0	0
T9	112023	202	0	0
T10	340277	14	0	0
T11	233485	196	0	0
T12	52817	464	0	0
T13	15914	258	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	218559	0	0
T1	471677	19	0	0
T2	145285	323	0	0
T3	102819	299	0	0
T7	342117	18	0	0
T8	141766	994	0	0
T9	112023	202	0	0
T10	340277	14	0	0
T11	233485	196	0	0
T12	52817	464	0	0
T13	15914	258	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	2932381	0	0
T1	471677	5635	0	0
T2	145285	2256	0	0
T3	102819	2391	0	0
T7	342117	88	0	0
T8	141766	1069	0	0
T9	112023	1596	0	0
T10	340277	47	0	0
T11	233485	878	0	0
T12	52817	458	0	0
T13	15914	246	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	218559	0	0
T1	471677	19	0	0
T2	145285	323	0	0
T3	102819	299	0	0
T7	342117	18	0	0
T8	141766	994	0	0
T9	112023	202	0	0
T10	340277	14	0	0
T11	233485	196	0	0
T12	52817	464	0	0
T13	15914	258	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	218559	0	0
T1	471677	19	0	0
T2	145285	323	0	0
T3	102819	299	0	0
T7	342117	18	0	0
T8	141766	994	0	0
T9	112023	202	0	0
T10	340277	14	0	0
T11	233485	196	0	0
T12	52817	464	0	0
T13	15914	258	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	623202	0	0
T1	471677	169	0	0
T2	145285	482	0	0
T3	102819	345	0	0
T7	342117	18	0	0
T8	141766	10112	0	0
T9	112023	209	0	0
T10	340277	15	0	0
T11	233485	254	0	0
T12	52817	472	0	0
T13	15914	271	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	218559	0	0
T1	471677	19	0	0
T2	145285	323	0	0
T3	102819	299	0	0
T7	342117	18	0	0
T8	141766	994	0	0
T9	112023	202	0	0
T10	340277	14	0	0
T11	233485	196	0	0
T12	52817	464	0	0
T13	15914	258	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	203442	0	0
GntImpliesValid_A	430352682	203442	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	203442	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	2906633	0	0
ReadyAndValidImplyGrant_A	430352682	203442	0	0
ReqAndReadyImplyGrant_A	430352682	203442	0	0
ReqImpliesValid_A	430352682	510286	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	203442	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	203442	0	0
T1	471677	16	0	0
T2	145285	358	0	0
T3	102819	313	0	0
T7	342117	10	0	0
T8	141766	455	0	0
T9	112023	215	0	0
T10	340277	20	0	0
T11	233485	190	0	0
T12	52817	951	0	0
T13	15914	237	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	203442	0	0
T1	471677	16	0	0
T2	145285	358	0	0
T3	102819	313	0	0
T7	342117	10	0	0
T8	141766	455	0	0
T9	112023	215	0	0
T10	340277	20	0	0
T11	233485	190	0	0
T12	52817	951	0	0
T13	15914	237	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	203442	0	0
T1	471677	16	0	0
T2	145285	358	0	0
T3	102819	313	0	0
T7	342117	10	0	0
T8	141766	455	0	0
T9	112023	215	0	0
T10	340277	20	0	0
T11	233485	190	0	0
T12	52817	951	0	0
T13	15914	237	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	2906633	0	0
T1	471677	5362	0	0
T2	145285	2676	0	0
T3	102819	2379	0	0
T7	342117	55	0	0
T8	141766	770	0	0
T9	112023	1702	0	0
T10	340277	89	0	0
T11	233485	801	0	0
T12	52817	493	0	0
T13	15914	220	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	203442	0	0
T1	471677	16	0	0
T2	145285	358	0	0
T3	102819	313	0	0
T7	342117	10	0	0
T8	141766	455	0	0
T9	112023	215	0	0
T10	340277	20	0	0
T11	233485	190	0	0
T12	52817	951	0	0
T13	15914	237	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	203442	0	0
T1	471677	16	0	0
T2	145285	358	0	0
T3	102819	313	0	0
T7	342117	10	0	0
T8	141766	455	0	0
T9	112023	215	0	0
T10	340277	20	0	0
T11	233485	190	0	0
T12	52817	951	0	0
T13	15914	237	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	510286	0	0
T1	471677	1176	0	0
T2	145285	428	0	0
T3	102819	352	0	0
T7	342117	10	0	0
T8	141766	4226	0	0
T9	112023	216	0	0
T10	340277	32	0	0
T11	233485	225	0	0
T12	52817	1411	0	0
T13	15914	255	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	203442	0	0
T1	471677	16	0	0
T2	145285	358	0	0
T3	102819	313	0	0
T7	342117	10	0	0
T8	141766	455	0	0
T9	112023	215	0	0
T10	340277	20	0	0
T11	233485	190	0	0
T12	52817	951	0	0
T13	15914	237	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	211015	0	0
GntImpliesValid_A	430352682	211015	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	211015	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	2972521	0	0
ReadyAndValidImplyGrant_A	430352682	211015	0	0
ReqAndReadyImplyGrant_A	430352682	211015	0	0
ReqImpliesValid_A	430352682	550201	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	211015	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	211015	0	0
T1	471677	9	0	0
T2	145285	376	0	0
T3	102819	293	0	0
T7	342117	14	0	0
T8	141766	519	0	0
T9	112023	211	0	0
T10	340277	9	0	0
T11	233485	184	0	0
T12	52817	1447	0	0
T13	15914	231	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	211015	0	0
T1	471677	9	0	0
T2	145285	376	0	0
T3	102819	293	0	0
T7	342117	14	0	0
T8	141766	519	0	0
T9	112023	211	0	0
T10	340277	9	0	0
T11	233485	184	0	0
T12	52817	1447	0	0
T13	15914	231	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	211015	0	0
T1	471677	9	0	0
T2	145285	376	0	0
T3	102819	293	0	0
T7	342117	14	0	0
T8	141766	519	0	0
T9	112023	211	0	0
T10	340277	9	0	0
T11	233485	184	0	0
T12	52817	1447	0	0
T13	15914	231	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	2972521	0	0
T1	471677	3136	0	0
T2	145285	2762	0	0
T3	102819	2231	0	0
T7	342117	59	0	0
T8	141766	1094	0	0
T9	112023	1630	0	0
T10	340277	36	0	0
T11	233485	851	0	0
T12	52817	869	0	0
T13	15914	222	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	211015	0	0
T1	471677	9	0	0
T2	145285	376	0	0
T3	102819	293	0	0
T7	342117	14	0	0
T8	141766	519	0	0
T9	112023	211	0	0
T10	340277	9	0	0
T11	233485	184	0	0
T12	52817	1447	0	0
T13	15914	231	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	211015	0	0
T1	471677	9	0	0
T2	145285	376	0	0
T3	102819	293	0	0
T7	342117	14	0	0
T8	141766	519	0	0
T9	112023	211	0	0
T10	340277	9	0	0
T11	233485	184	0	0
T12	52817	1447	0	0
T13	15914	231	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	550201	0	0
T1	471677	9	0	0
T2	145285	516	0	0
T3	102819	341	0	0
T7	342117	14	0	0
T8	141766	2088	0	0
T9	112023	248	0	0
T10	340277	9	0	0
T11	233485	217	0	0
T12	52817	2027	0	0
T13	15914	241	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	211015	0	0
T1	471677	9	0	0
T2	145285	376	0	0
T3	102819	293	0	0
T7	342117	14	0	0
T8	141766	519	0	0
T9	112023	211	0	0
T10	340277	9	0	0
T11	233485	184	0	0
T12	52817	1447	0	0
T13	15914	231	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	215135	0	0
GntImpliesValid_A	430352682	215135	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	215135	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	2914038	0	0
ReadyAndValidImplyGrant_A	430352682	215135	0	0
ReqAndReadyImplyGrant_A	430352682	215135	0	0
ReqImpliesValid_A	430352682	550457	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	215135	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	215135	0	0
T1	471677	14	0	0
T2	145285	363	0	0
T3	102819	296	0	0
T7	342117	13	0	0
T8	141766	0	0	0
T9	112023	178	0	0
T10	340277	20	0	0
T11	233485	183	0	0
T12	52817	537	0	0
T13	15914	206	0	0
T14	0	137	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	215135	0	0
T1	471677	14	0	0
T2	145285	363	0	0
T3	102819	296	0	0
T7	342117	13	0	0
T8	141766	0	0	0
T9	112023	178	0	0
T10	340277	20	0	0
T11	233485	183	0	0
T12	52817	537	0	0
T13	15914	206	0	0
T14	0	137	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	215135	0	0
T1	471677	14	0	0
T2	145285	363	0	0
T3	102819	296	0	0
T7	342117	13	0	0
T8	141766	0	0	0
T9	112023	178	0	0
T10	340277	20	0	0
T11	233485	183	0	0
T12	52817	537	0	0
T13	15914	206	0	0
T14	0	137	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	2914038	0	0
T1	471677	4718	0	0
T2	145285	2605	0	0
T3	102819	2303	0	0
T7	342117	57	0	0
T8	141766	1	0	0
T9	112023	1242	0	0
T10	340277	96	0	0
T11	233485	771	0	0
T12	52817	532	0	0
T13	15914	196	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	215135	0	0
T1	471677	14	0	0
T2	145285	363	0	0
T3	102819	296	0	0
T7	342117	13	0	0
T8	141766	0	0	0
T9	112023	178	0	0
T10	340277	20	0	0
T11	233485	183	0	0
T12	52817	537	0	0
T13	15914	206	0	0
T14	0	137	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	215135	0	0
T1	471677	14	0	0
T2	145285	363	0	0
T3	102819	296	0	0
T7	342117	13	0	0
T8	141766	0	0	0
T9	112023	178	0	0
T10	340277	20	0	0
T11	233485	183	0	0
T12	52817	537	0	0
T13	15914	206	0	0
T14	0	137	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	550457	0	0
T1	471677	1014	0	0
T2	145285	486	0	0
T3	102819	330	0	0
T7	342117	13	0	0
T8	141766	0	0	0
T9	112023	182	0	0
T10	340277	20	0	0
T11	233485	196	0	0
T12	52817	544	0	0
T13	15914	217	0	0
T14	0	143	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	215135	0	0
T1	471677	14	0	0
T2	145285	363	0	0
T3	102819	296	0	0
T7	342117	13	0	0
T8	141766	0	0	0
T9	112023	178	0	0
T10	340277	20	0	0
T11	233485	183	0	0
T12	52817	537	0	0
T13	15914	206	0	0
T14	0	137	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	209901	0	0
GntImpliesValid_A	430352682	209901	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	209901	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	2923236	0	0
ReadyAndValidImplyGrant_A	430352682	209901	0	0
ReqAndReadyImplyGrant_A	430352682	209901	0	0
ReqImpliesValid_A	430352682	539912	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	209901	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209901	0	0
T1	471677	15	0	0
T2	145285	345	0	0
T3	102819	332	0	0
T7	342117	17	0	0
T8	141766	464	0	0
T9	112023	195	0	0
T10	340277	11	0	0
T11	233485	202	0	0
T12	52817	978	0	0
T13	15914	240	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209901	0	0
T1	471677	15	0	0
T2	145285	345	0	0
T3	102819	332	0	0
T7	342117	17	0	0
T8	141766	464	0	0
T9	112023	195	0	0
T10	340277	11	0	0
T11	233485	202	0	0
T12	52817	978	0	0
T13	15914	240	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209901	0	0
T1	471677	15	0	0
T2	145285	345	0	0
T3	102819	332	0	0
T7	342117	17	0	0
T8	141766	464	0	0
T9	112023	195	0	0
T10	340277	11	0	0
T11	233485	202	0	0
T12	52817	978	0	0
T13	15914	240	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	2923236	0	0
T1	471677	4983	0	0
T2	145285	2556	0	0
T3	102819	2502	0	0
T7	342117	68	0	0
T8	141766	604	0	0
T9	112023	1525	0	0
T10	340277	49	0	0
T11	233485	842	0	0
T12	52817	924	0	0
T13	15914	229	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209901	0	0
T1	471677	15	0	0
T2	145285	345	0	0
T3	102819	332	0	0
T7	342117	17	0	0
T8	141766	464	0	0
T9	112023	195	0	0
T10	340277	11	0	0
T11	233485	202	0	0
T12	52817	978	0	0
T13	15914	240	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209901	0	0
T1	471677	15	0	0
T2	145285	345	0	0
T3	102819	332	0	0
T7	342117	17	0	0
T8	141766	464	0	0
T9	112023	195	0	0
T10	340277	11	0	0
T11	233485	202	0	0
T12	52817	978	0	0
T13	15914	240	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	539912	0	0
T1	471677	15	0	0
T2	145285	486	0	0
T3	102819	418	0	0
T7	342117	18	0	0
T8	141766	4568	0	0
T9	112023	218	0	0
T10	340277	11	0	0
T11	233485	267	0	0
T12	52817	1034	0	0
T13	15914	252	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209901	0	0
T1	471677	15	0	0
T2	145285	345	0	0
T3	102819	332	0	0
T7	342117	17	0	0
T8	141766	464	0	0
T9	112023	195	0	0
T10	340277	11	0	0
T11	233485	202	0	0
T12	52817	978	0	0
T13	15914	240	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	209520	0	0
GntImpliesValid_A	430352682	209520	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	209520	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	2967718	0	0
ReadyAndValidImplyGrant_A	430352682	209520	0	0
ReqAndReadyImplyGrant_A	430352682	209520	0	0
ReqImpliesValid_A	430352682	564488	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	209520	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209520	0	0
T1	471677	13	0	0
T2	145285	356	0	0
T3	102819	306	0	0
T7	342117	10	0	0
T8	141766	505	0	0
T9	112023	209	0	0
T10	340277	18	0	0
T11	233485	189	0	0
T12	52817	470	0	0
T13	15914	209	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209520	0	0
T1	471677	13	0	0
T2	145285	356	0	0
T3	102819	306	0	0
T7	342117	10	0	0
T8	141766	505	0	0
T9	112023	209	0	0
T10	340277	18	0	0
T11	233485	189	0	0
T12	52817	470	0	0
T13	15914	209	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209520	0	0
T1	471677	13	0	0
T2	145285	356	0	0
T3	102819	306	0	0
T7	342117	10	0	0
T8	141766	505	0	0
T9	112023	209	0	0
T10	340277	18	0	0
T11	233485	189	0	0
T12	52817	470	0	0
T13	15914	209	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	2967718	0	0
T1	471677	4072	0	0
T2	145285	2679	0	0
T3	102819	2376	0	0
T7	342117	39	0	0
T8	141766	585	0	0
T9	112023	1444	0	0
T10	340277	91	0	0
T11	233485	787	0	0
T12	52817	468	0	0
T13	15914	196	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209520	0	0
T1	471677	13	0	0
T2	145285	356	0	0
T3	102819	306	0	0
T7	342117	10	0	0
T8	141766	505	0	0
T9	112023	209	0	0
T10	340277	18	0	0
T11	233485	189	0	0
T12	52817	470	0	0
T13	15914	209	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209520	0	0
T1	471677	13	0	0
T2	145285	356	0	0
T3	102819	306	0	0
T7	342117	10	0	0
T8	141766	505	0	0
T9	112023	209	0	0
T10	340277	18	0	0
T11	233485	189	0	0
T12	52817	470	0	0
T13	15914	209	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	564488	0	0
T1	471677	52	0	0
T2	145285	415	0	0
T3	102819	399	0	0
T7	342117	10	0	0
T8	141766	5248	0	0
T9	112023	234	0	0
T10	340277	38	0	0
T11	233485	238	0	0
T12	52817	474	0	0
T13	15914	223	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209520	0	0
T1	471677	13	0	0
T2	145285	356	0	0
T3	102819	306	0	0
T7	342117	10	0	0
T8	141766	505	0	0
T9	112023	209	0	0
T10	340277	18	0	0
T11	233485	189	0	0
T12	52817	470	0	0
T13	15914	209	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	209167	0	0
GntImpliesValid_A	430352682	209167	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	209167	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	2924597	0	0
ReadyAndValidImplyGrant_A	430352682	209167	0	0
ReqAndReadyImplyGrant_A	430352682	209167	0	0
ReqImpliesValid_A	430352682	572533	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	209167	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209167	0	0
T1	471677	9	0	0
T2	145285	318	0	0
T3	102819	308	0	0
T7	342117	18	0	0
T8	141766	462	0	0
T9	112023	220	0	0
T10	340277	14	0	0
T11	233485	207	0	0
T12	52817	1510	0	0
T13	15914	213	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209167	0	0
T1	471677	9	0	0
T2	145285	318	0	0
T3	102819	308	0	0
T7	342117	18	0	0
T8	141766	462	0	0
T9	112023	220	0	0
T10	340277	14	0	0
T11	233485	207	0	0
T12	52817	1510	0	0
T13	15914	213	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209167	0	0
T1	471677	9	0	0
T2	145285	318	0	0
T3	102819	308	0	0
T7	342117	18	0	0
T8	141766	462	0	0
T9	112023	220	0	0
T10	340277	14	0	0
T11	233485	207	0	0
T12	52817	1510	0	0
T13	15914	213	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	2924597	0	0
T1	471677	3206	0	0
T2	145285	2359	0	0
T3	102819	2356	0	0
T7	342117	92	0	0
T8	141766	1111	0	0
T9	112023	1835	0	0
T10	340277	68	0	0
T11	233485	835	0	0
T12	52817	1321	0	0
T13	15914	208	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209167	0	0
T1	471677	9	0	0
T2	145285	318	0	0
T3	102819	308	0	0
T7	342117	18	0	0
T8	141766	462	0	0
T9	112023	220	0	0
T10	340277	14	0	0
T11	233485	207	0	0
T12	52817	1510	0	0
T13	15914	213	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209167	0	0
T1	471677	9	0	0
T2	145285	318	0	0
T3	102819	308	0	0
T7	342117	18	0	0
T8	141766	462	0	0
T9	112023	220	0	0
T10	340277	14	0	0
T11	233485	207	0	0
T12	52817	1510	0	0
T13	15914	213	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	572533	0	0
T1	471677	9	0	0
T2	145285	449	0	0
T3	102819	335	0	0
T7	342117	19	0	0
T8	141766	1698	0	0
T9	112023	251	0	0
T10	340277	18	0	0
T11	233485	235	0	0
T12	52817	1701	0	0
T13	15914	219	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	209167	0	0
T1	471677	9	0	0
T2	145285	318	0	0
T3	102819	308	0	0
T7	342117	18	0	0
T8	141766	462	0	0
T9	112023	220	0	0
T10	340277	14	0	0
T11	233485	207	0	0
T12	52817	1510	0	0
T13	15914	213	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	205171	0	0
GntImpliesValid_A	430352682	205171	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	205171	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	3037786	0	0
ReadyAndValidImplyGrant_A	430352682	205171	0	0
ReqAndReadyImplyGrant_A	430352682	205171	0	0
ReqImpliesValid_A	430352682	523552	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	205171	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	205171	0	0
T1	471677	19	0	0
T2	145285	800	0	0
T3	102819	305	0	0
T7	342117	12	0	0
T8	141766	0	0	0
T9	112023	216	0	0
T10	340277	8	0	0
T11	233485	179	0	0
T12	52817	977	0	0
T13	15914	251	0	0
T14	0	138	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	205171	0	0
T1	471677	19	0	0
T2	145285	800	0	0
T3	102819	305	0	0
T7	342117	12	0	0
T8	141766	0	0	0
T9	112023	216	0	0
T10	340277	8	0	0
T11	233485	179	0	0
T12	52817	977	0	0
T13	15914	251	0	0
T14	0	138	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	205171	0	0
T1	471677	19	0	0
T2	145285	800	0	0
T3	102819	305	0	0
T7	342117	12	0	0
T8	141766	0	0	0
T9	112023	216	0	0
T10	340277	8	0	0
T11	233485	179	0	0
T12	52817	977	0	0
T13	15914	251	0	0
T14	0	138	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	3037786	0	0
T1	471677	6609	0	0
T2	145285	5103	0	0
T3	102819	2269	0	0
T7	342117	51	0	0
T8	141766	1	0	0
T9	112023	1553	0	0
T10	340277	38	0	0
T11	233485	775	0	0
T12	52817	900	0	0
T13	15914	237	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	205171	0	0
T1	471677	19	0	0
T2	145285	800	0	0
T3	102819	305	0	0
T7	342117	12	0	0
T8	141766	0	0	0
T9	112023	216	0	0
T10	340277	8	0	0
T11	233485	179	0	0
T12	52817	977	0	0
T13	15914	251	0	0
T14	0	138	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	205171	0	0
T1	471677	19	0	0
T2	145285	800	0	0
T3	102819	305	0	0
T7	342117	12	0	0
T8	141766	0	0	0
T9	112023	216	0	0
T10	340277	8	0	0
T11	233485	179	0	0
T12	52817	977	0	0
T13	15914	251	0	0
T14	0	138	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	523552	0	0
T1	471677	91	0	0
T2	145285	2364	0	0
T3	102819	375	0	0
T7	342117	16	0	0
T8	141766	0	0	0
T9	112023	222	0	0
T10	340277	8	0	0
T11	233485	218	0	0
T12	52817	1056	0	0
T13	15914	266	0	0
T14	0	147	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	205171	0	0
T1	471677	19	0	0
T2	145285	800	0	0
T3	102819	305	0	0
T7	342117	12	0	0
T8	141766	0	0	0
T9	112023	216	0	0
T10	340277	8	0	0
T11	233485	179	0	0
T12	52817	977	0	0
T13	15914	251	0	0
T14	0	138	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	231033	0	0
GntImpliesValid_A	430352682	231033	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	231033	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	3062787	0	0
ReadyAndValidImplyGrant_A	430352682	231033	0	0
ReqAndReadyImplyGrant_A	430352682	231033	0	0
ReqImpliesValid_A	430352682	588894	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	231033	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	231033	0	0
T1	471677	9	0	0
T2	145285	423	0	0
T3	102819	288	0	0
T7	342117	11	0	0
T8	141766	482	0	0
T9	112023	218	0	0
T10	340277	13	0	0
T11	233485	184	0	0
T12	52817	1492	0	0
T13	15914	220	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	231033	0	0
T1	471677	9	0	0
T2	145285	423	0	0
T3	102819	288	0	0
T7	342117	11	0	0
T8	141766	482	0	0
T9	112023	218	0	0
T10	340277	13	0	0
T11	233485	184	0	0
T12	52817	1492	0	0
T13	15914	220	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	231033	0	0
T1	471677	9	0	0
T2	145285	423	0	0
T3	102819	288	0	0
T7	342117	11	0	0
T8	141766	482	0	0
T9	112023	218	0	0
T10	340277	13	0	0
T11	233485	184	0	0
T12	52817	1492	0	0
T13	15914	220	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	3062787	0	0
T1	471677	3860	0	0
T2	145285	3279	0	0
T3	102819	2075	0	0
T7	342117	45	0	0
T8	141766	346	0	0
T9	112023	1594	0	0
T10	340277	50	0	0
T11	233485	813	0	0
T12	52817	933	0	0
T13	15914	211	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	231033	0	0
T1	471677	9	0	0
T2	145285	423	0	0
T3	102819	288	0	0
T7	342117	11	0	0
T8	141766	482	0	0
T9	112023	218	0	0
T10	340277	13	0	0
T11	233485	184	0	0
T12	52817	1492	0	0
T13	15914	220	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	231033	0	0
T1	471677	9	0	0
T2	145285	423	0	0
T3	102819	288	0	0
T7	342117	11	0	0
T8	141766	482	0	0
T9	112023	218	0	0
T10	340277	13	0	0
T11	233485	184	0	0
T12	52817	1492	0	0
T13	15914	220	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	588894	0	0
T1	471677	9	0	0
T2	145285	539	0	0
T3	102819	362	0	0
T7	342117	11	0	0
T8	141766	5340	0	0
T9	112023	243	0	0
T10	340277	21	0	0
T11	233485	200	0	0
T12	52817	2053	0	0
T13	15914	230	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	231033	0	0
T1	471677	9	0	0
T2	145285	423	0	0
T3	102819	288	0	0
T7	342117	11	0	0
T8	141766	482	0	0
T9	112023	218	0	0
T10	340277	13	0	0
T11	233485	184	0	0
T12	52817	1492	0	0
T13	15914	220	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	208931	0	0
GntImpliesValid_A	430352682	208931	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	208931	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	2956704	0	0
ReadyAndValidImplyGrant_A	430352682	208931	0	0
ReqAndReadyImplyGrant_A	430352682	208931	0	0
ReqImpliesValid_A	430352682	561166	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	208931	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	208931	0	0
T1	471677	15	0	0
T2	145285	353	0	0
T3	102819	312	0	0
T7	342117	15	0	0
T8	141766	904	0	0
T9	112023	211	0	0
T10	340277	13	0	0
T11	233485	196	0	0
T12	52817	498	0	0
T13	15914	236	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	208931	0	0
T1	471677	15	0	0
T2	145285	353	0	0
T3	102819	312	0	0
T7	342117	15	0	0
T8	141766	904	0	0
T9	112023	211	0	0
T10	340277	13	0	0
T11	233485	196	0	0
T12	52817	498	0	0
T13	15914	236	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	208931	0	0
T1	471677	15	0	0
T2	145285	353	0	0
T3	102819	312	0	0
T7	342117	15	0	0
T8	141766	904	0	0
T9	112023	211	0	0
T10	340277	13	0	0
T11	233485	196	0	0
T12	52817	498	0	0
T13	15914	236	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	2956704	0	0
T1	471677	5133	0	0
T2	145285	2607	0	0
T3	102819	2203	0	0
T7	342117	68	0	0
T8	141766	853	0	0
T9	112023	1661	0	0
T10	340277	43	0	0
T11	233485	849	0	0
T12	52817	491	0	0
T13	15914	224	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	208931	0	0
T1	471677	15	0	0
T2	145285	353	0	0
T3	102819	312	0	0
T7	342117	15	0	0
T8	141766	904	0	0
T9	112023	211	0	0
T10	340277	13	0	0
T11	233485	196	0	0
T12	52817	498	0	0
T13	15914	236	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	208931	0	0
T1	471677	15	0	0
T2	145285	353	0	0
T3	102819	312	0	0
T7	342117	15	0	0
T8	141766	904	0	0
T9	112023	211	0	0
T10	340277	13	0	0
T11	233485	196	0	0
T12	52817	498	0	0
T13	15914	236	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	561166	0	0
T1	471677	15	0	0
T2	145285	432	0	0
T3	102819	402	0	0
T7	342117	19	0	0
T8	141766	9339	0	0
T9	112023	226	0	0
T10	340277	13	0	0
T11	233485	228	0	0
T12	52817	507	0	0
T13	15914	249	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	208931	0	0
T1	471677	15	0	0
T2	145285	353	0	0
T3	102819	312	0	0
T7	342117	15	0	0
T8	141766	904	0	0
T9	112023	211	0	0
T10	340277	13	0	0
T11	233485	196	0	0
T12	52817	498	0	0
T13	15914	236	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	208352	0	0
GntImpliesValid_A	430352682	208352	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	208352	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	2939443	0	0
ReadyAndValidImplyGrant_A	430352682	208352	0	0
ReqAndReadyImplyGrant_A	430352682	208352	0	0
ReqImpliesValid_A	430352682	544164	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	208352	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	208352	0	0
T1	471677	10	0	0
T2	145285	344	0	0
T3	102819	277	0	0
T7	342117	19	0	0
T8	141766	518	0	0
T9	112023	205	0	0
T10	340277	9	0	0
T11	233485	196	0	0
T12	52817	906	0	0
T13	15914	221	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	208352	0	0
T1	471677	10	0	0
T2	145285	344	0	0
T3	102819	277	0	0
T7	342117	19	0	0
T8	141766	518	0	0
T9	112023	205	0	0
T10	340277	9	0	0
T11	233485	196	0	0
T12	52817	906	0	0
T13	15914	221	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	208352	0	0
T1	471677	10	0	0
T2	145285	344	0	0
T3	102819	277	0	0
T7	342117	19	0	0
T8	141766	518	0	0
T9	112023	205	0	0
T10	340277	9	0	0
T11	233485	196	0	0
T12	52817	906	0	0
T13	15914	221	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	2939443	0	0
T1	471677	4279	0	0
T2	145285	2497	0	0
T3	102819	2082	0	0
T7	342117	70	0	0
T8	141766	1157	0	0
T9	112023	1464	0	0
T10	340277	32	0	0
T11	233485	860	0	0
T12	52817	475	0	0
T13	15914	214	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	208352	0	0
T1	471677	10	0	0
T2	145285	344	0	0
T3	102819	277	0	0
T7	342117	19	0	0
T8	141766	518	0	0
T9	112023	205	0	0
T10	340277	9	0	0
T11	233485	196	0	0
T12	52817	906	0	0
T13	15914	221	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	208352	0	0
T1	471677	10	0	0
T2	145285	344	0	0
T3	102819	277	0	0
T7	342117	19	0	0
T8	141766	518	0	0
T9	112023	205	0	0
T10	340277	9	0	0
T11	233485	196	0	0
T12	52817	906	0	0
T13	15914	221	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	544164	0	0
T1	471677	10	0	0
T2	145285	523	0	0
T3	102819	328	0	0
T7	342117	26	0	0
T8	141766	2063	0	0
T9	112023	205	0	0
T10	340277	15	0	0
T11	233485	246	0	0
T12	52817	1339	0	0
T13	15914	229	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	208352	0	0
T1	471677	10	0	0
T2	145285	344	0	0
T3	102819	277	0	0
T7	342117	19	0	0
T8	141766	518	0	0
T9	112023	205	0	0
T10	340277	9	0	0
T11	233485	196	0	0
T12	52817	906	0	0
T13	15914	221	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	204980	0	0
GntImpliesValid_A	430352682	204980	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	204980	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	2993044	0	0
ReadyAndValidImplyGrant_A	430352682	204980	0	0
ReqAndReadyImplyGrant_A	430352682	204980	0	0
ReqImpliesValid_A	430352682	519726	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	204980	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	204980	0	0
T1	471677	22	0	0
T2	145285	835	0	0
T3	102819	329	0	0
T7	342117	14	0	0
T8	141766	0	0	0
T9	112023	211	0	0
T10	340277	12	0	0
T11	233485	209	0	0
T12	52817	1541	0	0
T13	15914	220	0	0
T14	0	127	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	204980	0	0
T1	471677	22	0	0
T2	145285	835	0	0
T3	102819	329	0	0
T7	342117	14	0	0
T8	141766	0	0	0
T9	112023	211	0	0
T10	340277	12	0	0
T11	233485	209	0	0
T12	52817	1541	0	0
T13	15914	220	0	0
T14	0	127	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	204980	0	0
T1	471677	22	0	0
T2	145285	835	0	0
T3	102819	329	0	0
T7	342117	14	0	0
T8	141766	0	0	0
T9	112023	211	0	0
T10	340277	12	0	0
T11	233485	209	0	0
T12	52817	1541	0	0
T13	15914	220	0	0
T14	0	127	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	2993044	0	0
T1	471677	6921	0	0
T2	145285	5405	0	0
T3	102819	2571	0	0
T7	342117	52	0	0
T8	141766	1	0	0
T9	112023	1615	0	0
T10	340277	55	0	0
T11	233485	962	0	0
T12	52817	881	0	0
T13	15914	209	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	204980	0	0
T1	471677	22	0	0
T2	145285	835	0	0
T3	102819	329	0	0
T7	342117	14	0	0
T8	141766	0	0	0
T9	112023	211	0	0
T10	340277	12	0	0
T11	233485	209	0	0
T12	52817	1541	0	0
T13	15914	220	0	0
T14	0	127	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	204980	0	0
T1	471677	22	0	0
T2	145285	835	0	0
T3	102819	329	0	0
T7	342117	14	0	0
T8	141766	0	0	0
T9	112023	211	0	0
T10	340277	12	0	0
T11	233485	209	0	0
T12	52817	1541	0	0
T13	15914	220	0	0
T14	0	127	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	519726	0	0
T1	471677	406	0	0
T2	145285	1411	0	0
T3	102819	411	0	0
T7	342117	20	0	0
T8	141766	0	0	0
T9	112023	211	0	0
T10	340277	12	0	0
T11	233485	237	0	0
T12	52817	2203	0	0
T13	15914	232	0	0
T14	0	136	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	204980	0	0
T1	471677	22	0	0
T2	145285	835	0	0
T3	102819	329	0	0
T7	342117	14	0	0
T8	141766	0	0	0
T9	112023	211	0	0
T10	340277	12	0	0
T11	233485	209	0	0
T12	52817	1541	0	0
T13	15914	220	0	0
T14	0	127	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	211356	0	0
GntImpliesValid_A	430352682	211356	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	211356	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	2926900	0	0
ReadyAndValidImplyGrant_A	430352682	211356	0	0
ReqAndReadyImplyGrant_A	430352682	211356	0	0
ReqImpliesValid_A	430352682	561649	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	211356	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	211356	0	0
T1	471677	13	0	0
T2	145285	282	0	0
T3	102819	307	0	0
T7	342117	18	0	0
T8	141766	456	0	0
T9	112023	196	0	0
T10	340277	7	0	0
T11	233485	195	0	0
T12	52817	1016	0	0
T13	15914	213	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	211356	0	0
T1	471677	13	0	0
T2	145285	282	0	0
T3	102819	307	0	0
T7	342117	18	0	0
T8	141766	456	0	0
T9	112023	196	0	0
T10	340277	7	0	0
T11	233485	195	0	0
T12	52817	1016	0	0
T13	15914	213	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	211356	0	0
T1	471677	13	0	0
T2	145285	282	0	0
T3	102819	307	0	0
T7	342117	18	0	0
T8	141766	456	0	0
T9	112023	196	0	0
T10	340277	7	0	0
T11	233485	195	0	0
T12	52817	1016	0	0
T13	15914	213	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	2926900	0	0
T1	471677	3188	0	0
T2	145285	1924	0	0
T3	102819	2406	0	0
T7	342117	79	0	0
T8	141766	412	0	0
T9	112023	1475	0	0
T10	340277	34	0	0
T11	233485	859	0	0
T12	52817	429	0	0
T13	15914	199	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	211356	0	0
T1	471677	13	0	0
T2	145285	282	0	0
T3	102819	307	0	0
T7	342117	18	0	0
T8	141766	456	0	0
T9	112023	196	0	0
T10	340277	7	0	0
T11	233485	195	0	0
T12	52817	1016	0	0
T13	15914	213	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	211356	0	0
T1	471677	13	0	0
T2	145285	282	0	0
T3	102819	307	0	0
T7	342117	18	0	0
T8	141766	456	0	0
T9	112023	196	0	0
T10	340277	7	0	0
T11	233485	195	0	0
T12	52817	1016	0	0
T13	15914	213	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	561649	0	0
T1	471677	13	0	0
T2	145285	377	0	0
T3	102819	362	0	0
T7	342117	21	0	0
T8	141766	5045	0	0
T9	112023	207	0	0
T10	340277	12	0	0
T11	233485	236	0	0
T12	52817	1605	0	0
T13	15914	228	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	211356	0	0
T1	471677	13	0	0
T2	145285	282	0	0
T3	102819	307	0	0
T7	342117	18	0	0
T8	141766	456	0	0
T9	112023	196	0	0
T10	340277	7	0	0
T11	233485	195	0	0
T12	52817	1016	0	0
T13	15914	213	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	217135	0	0
GntImpliesValid_A	430352682	217135	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	217135	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	3001069	0	0
ReadyAndValidImplyGrant_A	430352682	217135	0	0
ReqAndReadyImplyGrant_A	430352682	217135	0	0
ReqImpliesValid_A	430352682	547596	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	0	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	217135	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	217135	0	0
T1	471677	10	0	0
T2	145285	353	0	0
T3	102819	277	0	0
T7	342117	13	0	0
T8	141766	0	0	0
T9	112023	200	0	0
T10	340277	8	0	0
T11	233485	189	0	0
T12	52817	1584	0	0
T13	15914	227	0	0
T14	0	110	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	217135	0	0
T1	471677	10	0	0
T2	145285	353	0	0
T3	102819	277	0	0
T7	342117	13	0	0
T8	141766	0	0	0
T9	112023	200	0	0
T10	340277	8	0	0
T11	233485	189	0	0
T12	52817	1584	0	0
T13	15914	227	0	0
T14	0	110	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	217135	0	0
T1	471677	10	0	0
T2	145285	353	0	0
T3	102819	277	0	0
T7	342117	13	0	0
T8	141766	0	0	0
T9	112023	200	0	0
T10	340277	8	0	0
T11	233485	189	0	0
T12	52817	1584	0	0
T13	15914	227	0	0
T14	0	110	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	3001069	0	0
T1	471677	4290	0	0
T2	145285	2541	0	0
T3	102819	2044	0	0
T7	342117	45	0	0
T8	141766	1	0	0
T9	112023	1666	0	0
T10	340277	33	0	0
T11	233485	810	0	0
T12	52817	1370	0	0
T13	15914	219	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	217135	0	0
T1	471677	10	0	0
T2	145285	353	0	0
T3	102819	277	0	0
T7	342117	13	0	0
T8	141766	0	0	0
T9	112023	200	0	0
T10	340277	8	0	0
T11	233485	189	0	0
T12	52817	1584	0	0
T13	15914	227	0	0
T14	0	110	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	217135	0	0
T1	471677	10	0	0
T2	145285	353	0	0
T3	102819	277	0	0
T7	342117	13	0	0
T8	141766	0	0	0
T9	112023	200	0	0
T10	340277	8	0	0
T11	233485	189	0	0
T12	52817	1584	0	0
T13	15914	227	0	0
T14	0	110	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	547596	0	0
T1	471677	384	0	0
T2	145285	514	0	0
T3	102819	382	0	0
T7	342117	14	0	0
T8	141766	0	0	0
T9	112023	213	0	0
T10	340277	13	0	0
T11	233485	211	0	0
T12	52817	1800	0	0
T13	15914	236	0	0
T14	0	117	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	217135	0	0
T1	471677	10	0	0
T2	145285	353	0	0
T3	102819	277	0	0
T7	342117	13	0	0
T8	141766	0	0	0
T9	112023	200	0	0
T10	340277	8	0	0
T11	233485	189	0	0
T12	52817	1584	0	0
T13	15914	227	0	0
T14	0	110	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	857421	0	0
GntImpliesValid_A	430352682	857421	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	857421	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	11129117	0	0
ReadyAndValidImplyGrant_A	430352682	857421	0	0
ReqAndReadyImplyGrant_A	430352682	857421	0	0
ReqImpliesValid_A	430352682	2246383	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	16612	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	857421	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	857421	0	0
T1	471677	39	0	0
T2	145285	1402	0	0
T3	102819	1142	0	0
T7	342117	57	0	0
T8	141766	1073	0	0
T9	112023	846	0	0
T10	340277	63	0	0
T11	233485	760	0	0
T12	52817	3569	0	0
T13	15914	936	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	857421	0	0
T1	471677	39	0	0
T2	145285	1402	0	0
T3	102819	1142	0	0
T7	342117	57	0	0
T8	141766	1073	0	0
T9	112023	846	0	0
T10	340277	63	0	0
T11	233485	760	0	0
T12	52817	3569	0	0
T13	15914	936	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	857421	0	0
T1	471677	39	0	0
T2	145285	1402	0	0
T3	102819	1142	0	0
T7	342117	57	0	0
T8	141766	1073	0	0
T9	112023	846	0	0
T10	340277	63	0	0
T11	233485	760	0	0
T12	52817	3569	0	0
T13	15914	936	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	11129117	0	0
T1	471677	11557	0	0
T2	145285	8272	0	0
T3	102819	7510	0	0
T7	342117	163	0	0
T8	141766	6405	0	0
T9	112023	5485	0	0
T10	340277	217	0	0
T11	233485	2434	0	0
T12	52817	2	0	0
T13	15914	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	857421	0	0
T1	471677	39	0	0
T2	145285	1402	0	0
T3	102819	1142	0	0
T7	342117	57	0	0
T8	141766	1073	0	0
T9	112023	846	0	0
T10	340277	63	0	0
T11	233485	760	0	0
T12	52817	3569	0	0
T13	15914	936	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	857421	0	0
T1	471677	39	0	0
T2	145285	1402	0	0
T3	102819	1142	0	0
T7	342117	57	0	0
T8	141766	1073	0	0
T9	112023	846	0	0
T10	340277	63	0	0
T11	233485	760	0	0
T12	52817	3569	0	0
T13	15914	936	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	2246383	0	0
T1	471677	705	0	0
T2	145285	2180	0	0
T3	102819	1852	0	0
T7	342117	74	0	0
T8	141766	1589	0	0
T9	112023	1053	0	0
T10	340277	89	0	0
T11	233485	986	0	0
T12	52817	3569	0	0
T13	15914	936	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	16612	0	900
T3	102819	1	0	1
T7	342117	0	0	1
T8	141766	0	0	1
T9	112023	0	0	1
T10	340277	0	0	1
T11	233485	0	0	1
T12	52817	92	0	1
T13	15914	24	0	1
T14	7043	8	0	1
T15	0	1	0	0
T18	0	14	0	0
T19	0	1	0	0
T20	0	17	0	0
T21	0	9	0	0
T22	0	12	0	0
T23	133957	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	857421	0	0
T1	471677	39	0	0
T2	145285	1402	0	0
T3	102819	1142	0	0
T7	342117	57	0	0
T8	141766	1073	0	0
T9	112023	846	0	0
T10	340277	63	0	0
T11	233485	760	0	0
T12	52817	3569	0	0
T13	15914	936	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	430352682	430233804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	430352682	842071	0	0
GntImpliesValid_A	430352682	842071	0	0
GrantKnown_A	430352682	430233804	0	0
IdxKnown_A	430352682	430233804	0	0
IndexIsCorrect_A	430352682	842071	0	0
LockArbDecision_A	430352682	0	0	0
NoReadyValidNoGrant_A	430352682	361130036	0	0
ReadyAndValidImplyGrant_A	430352682	842071	0	0
ReqAndReadyImplyGrant_A	430352682	842071	0	0
ReqImpliesValid_A	430352682	13198726	0	0
ReqStaysHighUntilGranted0_M	430352682	0	0	0
RoundRobin_A	430352682	25919	0	900
ValidKnown_A	430352682	430233804	0	0
gen_data_port_assertion.DataFlow_A	430352682	842071	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	842071	0	0
T1	471677	42	0	0
T2	145285	1477	0	0
T3	102819	1141	0	0
T7	342117	47	0	0
T8	141766	2730	0	0
T9	112023	822	0	0
T10	340277	59	0	0
T11	233485	757	0	0
T12	52817	2909	0	0
T13	15914	902	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	842071	0	0
T1	471677	42	0	0
T2	145285	1477	0	0
T3	102819	1141	0	0
T7	342117	47	0	0
T8	141766	2730	0	0
T9	112023	822	0	0
T10	340277	59	0	0
T11	233485	757	0	0
T12	52817	2909	0	0
T13	15914	902	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	842071	0	0
T1	471677	42	0	0
T2	145285	1477	0	0
T3	102819	1141	0	0
T7	342117	47	0	0
T8	141766	2730	0	0
T9	112023	822	0	0
T10	340277	59	0	0
T11	233485	757	0	0
T12	52817	2909	0	0
T13	15914	902	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	361130036	0	0
T1	471677	450853	0	0
T2	145285	118074	0	0
T3	102819	85264	0	0
T7	342117	284906	0	0
T8	141766	105388	0	0
T9	112023	96190	0	0
T10	340277	283112	0	0
T11	233485	194259	0	0
T12	52817	1	0	0
T13	15914	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	842071	0	0
T1	471677	42	0	0
T2	145285	1477	0	0
T3	102819	1141	0	0
T7	342117	47	0	0
T8	141766	2730	0	0
T9	112023	822	0	0
T10	340277	59	0	0
T11	233485	757	0	0
T12	52817	2909	0	0
T13	15914	902	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	842071	0	0
T1	471677	42	0	0
T2	145285	1477	0	0
T3	102819	1141	0	0
T7	342117	47	0	0
T8	141766	2730	0	0
T9	112023	822	0	0
T10	340277	59	0	0
T11	233485	757	0	0
T12	52817	2909	0	0
T13	15914	902	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	13198726	0	0
T1	471677	14721	0	0
T2	145285	11074	0	0
T3	102819	9324	0	0
T7	342117	198	0	0
T8	141766	26157	0	0
T9	112023	6379	0	0
T10	340277	279	0	0
T11	233485	3352	0	0
T12	52817	2909	0	0
T13	15914	902	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	25919	0	900
T2	145285	3	0	1
T3	102819	0	0	1
T4	0	1	0	0
T7	342117	0	0	1
T8	141766	31	0	1
T9	112023	0	0	1
T10	340277	0	0	1
T11	233485	0	0	1
T12	52817	31	0	1
T13	15914	14	0	1
T14	7043	9	0	1
T15	0	4	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	9	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	430233804	0	0
T1	471677	471617	0	0
T2	145285	145253	0	0
T3	102819	102800	0	0
T7	342117	342096	0	0
T8	141766	141723	0	0
T9	112023	112016	0	0
T10	340277	340248	0	0
T11	233485	233482	0	0
T12	52817	52694	0	0
T13	15914	15865	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430352682	842071	0	0
T1	471677	42	0	0
T2	145285	1477	0	0
T3	102819	1141	0	0
T7	342117	47	0	0
T8	141766	2730	0	0
T9	112023	822	0	0
T10	340277	59	0	0
T11	233485	757	0	0
T12	52817	2909	0	0
T13	15914	902	0	0