Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1611768	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

256368

1

T1

19

T2

19

T3

1600

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	633244	1			T1	41		T2	42		T3	4025
values[0x0]	600427	1			T1	40		T2	36		T3	3926
values[0x1]	634465	1			T1	44		T2	35		T3	3996

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1245064	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

623072

1

T1

48

T2

44

T3

3916

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29060	1			T3	255		T4	20		T7	2
valid_sources[0x01]	28614	1			T1	2		T3	239		T4	13
valid_sources[0x02]	30007	1			T2	1		T3	191		T4	6
valid_sources[0x03]	29469	1			T2	1		T3	174		T4	7
valid_sources[0x04]	28976	1			T1	3		T2	3		T3	217
valid_sources[0x05]	28913	1			T1	4		T3	166		T4	15
valid_sources[0x06]	29449	1			T3	181		T4	22		T7	39
valid_sources[0x07]	29553	1			T2	5		T3	187		T4	11
valid_sources[0x08]	29438	1			T1	1		T3	202		T4	14
valid_sources[0x09]	28791	1			T1	1		T2	4		T3	167
valid_sources[0x0a]	28522	1			T1	2		T2	1		T3	197
valid_sources[0x0b]	29865	1			T2	3		T3	176		T4	14
valid_sources[0x0c]	29336	1			T1	2		T3	203		T4	7
valid_sources[0x0d]	28656	1			T2	4		T3	169		T4	6
valid_sources[0x0e]	30631	1			T3	173		T4	19		T7	42
valid_sources[0x0f]	29845	1			T1	4		T2	1		T3	190
valid_sources[0x10]	29242	1			T1	1		T2	1		T3	153
valid_sources[0x11]	29223	1			T1	1		T2	3		T3	205
valid_sources[0x12]	29752	1			T1	3		T2	2		T3	161
valid_sources[0x13]	28623	1			T2	3		T3	151		T4	12
valid_sources[0x14]	29714	1			T1	5		T2	1		T3	180
valid_sources[0x15]	28915	1			T2	2		T3	150		T4	15
valid_sources[0x16]	28862	1			T1	1		T2	1		T3	162
valid_sources[0x17]	29050	1			T1	1		T3	201		T4	9
valid_sources[0x18]	29170	1			T1	8		T2	2		T3	146
valid_sources[0x19]	29006	1			T3	218		T4	15		T7	11
valid_sources[0x1a]	28702	1			T1	4		T3	197		T4	16
valid_sources[0x1b]	28741	1			T1	5		T2	1		T3	218
valid_sources[0x1c]	28607	1			T1	6		T3	165		T4	19
valid_sources[0x1d]	29104	1			T1	1		T2	4		T3	168
valid_sources[0x1e]	29544	1			T1	1		T2	3		T3	236
valid_sources[0x1f]	28286	1			T1	1		T2	5		T3	172
valid_sources[0x20]	29350	1			T3	206		T4	19		T7	89

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26809

1

T1

1

T2

3

T3

161

values[0x0]

all_enables

biggest_size

202746

1

T1

15

T2

13

T3

1276

values[0x1]

all_enables

biggest_size

26813

1

T1

3

T2

3

T3

163

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1626139	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

264611

1

T1

39

T2

25

T3

1717

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	646383	1			T1	61		T2	58		T3	3917
values[0x0]	598718	1			T1	73		T2	53		T3	3918
values[0x1]	645649	1			T1	62		T2	55		T3	4115

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1249276	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

641474

1

T1

75

T2

62

T3

4121

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29873	1			T1	1		T2	6		T3	259
valid_sources[0x01]	29776	1			T2	5		T3	195		T4	8
valid_sources[0x02]	29465	1			T1	20		T2	2		T3	198
valid_sources[0x03]	30105	1			T1	2		T2	4		T3	129
valid_sources[0x04]	29940	1			T2	5		T3	242		T4	11
valid_sources[0x05]	29690	1			T1	4		T2	1		T3	214
valid_sources[0x06]	29849	1			T1	11		T2	2		T3	194
valid_sources[0x07]	29361	1			T1	4		T2	5		T3	191
valid_sources[0x08]	29487	1			T1	4		T2	1		T3	221
valid_sources[0x09]	29598	1			T1	1		T2	1		T3	163
valid_sources[0x0a]	29431	1			T1	3		T2	3		T3	187
valid_sources[0x0b]	29803	1			T1	5		T2	2		T3	146
valid_sources[0x0c]	30053	1			T2	2		T3	209		T4	11
valid_sources[0x0d]	29407	1			T1	18		T2	3		T3	182
valid_sources[0x0e]	29146	1			T1	6		T3	121		T4	9
valid_sources[0x0f]	28561	1			T1	1		T2	4		T3	200
valid_sources[0x10]	29454	1			T1	3		T2	5		T3	147
valid_sources[0x11]	29798	1			T1	9		T2	2		T3	170
valid_sources[0x12]	29956	1			T1	1		T2	4		T3	197
valid_sources[0x13]	29030	1			T2	2		T3	134		T4	6
valid_sources[0x14]	29002	1			T1	1		T2	3		T3	210
valid_sources[0x15]	29179	1			T2	1		T3	170		T4	18
valid_sources[0x16]	29097	1			T1	2		T2	1		T3	104
valid_sources[0x17]	29875	1			T1	5		T2	3		T3	183
valid_sources[0x18]	29477	1			T2	4		T3	139		T4	11
valid_sources[0x19]	29711	1			T1	9		T2	1		T3	242
valid_sources[0x1a]	29623	1			T2	4		T3	171		T4	9
valid_sources[0x1b]	29545	1			T1	12		T2	1		T3	210
valid_sources[0x1c]	29460	1			T1	2		T2	2		T3	194
valid_sources[0x1d]	29684	1			T2	3		T3	163		T4	14
valid_sources[0x1e]	29844	1			T2	1		T3	219		T4	19
valid_sources[0x1f]	29422	1			T1	3		T2	2		T3	214
valid_sources[0x20]	29389	1			T2	1		T3	230		T4	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27696

1

T1

4

T2

1

T3

179

values[0x0]

all_enables

biggest_size

209234

1

T1

32

T2

22

T3

1359

values[0x1]

all_enables

biggest_size

27681

1

T1

3

T2

2

T3

179

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1623714	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

257851

1

T1

20

T2

13

T3

1644

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	639431	1			T1	51		T2	61		T3	4152
values[0x0]	603922	1			T1	53		T2	40		T3	3983
values[0x1]	638212	1			T1	59		T2	48		T3	4113

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1254860	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

626705

1

T1

59

T2

40

T3

4011

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29035	1			T2	4		T3	224		T4	10
valid_sources[0x01]	29697	1			T2	3		T3	239		T4	10
valid_sources[0x02]	29760	1			T2	4		T3	178		T4	13
valid_sources[0x03]	29547	1			T2	3		T3	170		T4	10
valid_sources[0x04]	29298	1			T2	3		T3	202		T4	15
valid_sources[0x05]	29343	1			T2	1		T3	180		T4	17
valid_sources[0x06]	29654	1			T2	1		T3	205		T4	11
valid_sources[0x07]	29810	1			T1	3		T2	2		T3	194
valid_sources[0x08]	29326	1			T2	4		T3	182		T4	11
valid_sources[0x09]	29109	1			T2	1		T3	196		T4	12
valid_sources[0x0a]	29594	1			T2	3		T3	189		T4	11
valid_sources[0x0b]	29225	1			T1	1		T2	3		T3	168
valid_sources[0x0c]	29300	1			T2	3		T3	198		T4	8
valid_sources[0x0d]	29034	1			T3	213		T4	7		T7	29
valid_sources[0x0e]	29180	1			T1	21		T2	1		T3	150
valid_sources[0x0f]	29841	1			T2	1		T3	167		T4	7
valid_sources[0x10]	29556	1			T2	2		T3	155		T4	13
valid_sources[0x11]	28352	1			T1	11		T2	1		T3	189
valid_sources[0x12]	29082	1			T3	190		T4	13		T7	15
valid_sources[0x13]	29151	1			T2	5		T3	147		T4	9
valid_sources[0x14]	29111	1			T1	7		T2	5		T3	187
valid_sources[0x15]	29701	1			T2	2		T3	187		T4	6
valid_sources[0x16]	29142	1			T3	163		T4	15		T7	13
valid_sources[0x17]	29608	1			T2	2		T3	234		T4	12
valid_sources[0x18]	30101	1			T2	1		T3	144		T4	10
valid_sources[0x19]	29060	1			T3	252		T4	7		T7	23
valid_sources[0x1a]	29494	1			T2	5		T3	246		T4	10
valid_sources[0x1b]	30285	1			T2	3		T3	189		T4	13
valid_sources[0x1c]	28554	1			T2	1		T3	214		T4	10
valid_sources[0x1d]	29812	1			T2	6		T3	170		T4	18
valid_sources[0x1e]	29359	1			T2	2		T3	205		T4	6
valid_sources[0x1f]	29900	1			T2	4		T3	207		T4	9
valid_sources[0x20]	29841	1			T2	3		T3	240		T4	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27109

1

T1

3

T2

3

T3

156

values[0x0]

all_enables

biggest_size

203728

1

T1

16

T2

8

T3

1313

values[0x1]

all_enables

biggest_size

27014

1

T1

1

T2

2

T3

175