Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8026608	0	0
GntImpliesValid_A	2147483647	8026608	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8026608	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	485215098	0	0
ReadyAndValidImplyGrant_A	2147483647	8026608	0	0
ReqAndReadyImplyGrant_A	2147483647	8026608	0	0
ReqImpliesValid_A	2147483647	37008632	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	49091	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8026608	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	23304	22536	0	0
T2	264096	263496	0	0
T3	1724136	1722720	0	0
T4	11257008	11252400	0	0
T7	21455832	21455376	0	0
T8	404904	404064	0	0
T9	6283080	6283032	0	0
T10	229248	221568	0	0
T11	9779808	9779712	0	0
T12	548280	547104	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8026608	0	0
T1	23304	484	0	0
T2	264096	427	0	0
T3	1724136	35728	0	0
T4	11257008	44454	0	0
T7	21455832	4566	0	0
T8	404904	5667	0	0
T9	6283080	5882	0	0
T10	229248	3855	0	0
T11	9779808	9702	0	0
T12	548280	1975	0	0
T13	0	3143	0	0
T14	0	399	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8026608	0	0
T1	23304	484	0	0
T2	264096	427	0	0
T3	1724136	35728	0	0
T4	11257008	44454	0	0
T7	21455832	4566	0	0
T8	404904	5667	0	0
T9	6283080	5882	0	0
T10	229248	3855	0	0
T11	9779808	9702	0	0
T12	548280	1975	0	0
T13	0	3143	0	0
T14	0	399	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	23304	22536	0	0
T2	264096	263496	0	0
T3	1724136	1722720	0	0
T4	11257008	11252400	0	0
T7	21455832	21455376	0	0
T8	404904	404064	0	0
T9	6283080	6283032	0	0
T10	229248	221568	0	0
T11	9779808	9779712	0	0
T12	548280	547104	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	23304	22536	0	0
T2	264096	263496	0	0
T3	1724136	1722720	0	0
T4	11257008	11252400	0	0
T7	21455832	21455376	0	0
T8	404904	404064	0	0
T9	6283080	6283032	0	0
T10	229248	221568	0	0
T11	9779808	9779712	0	0
T12	548280	547104	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8026608	0	0
T1	23304	484	0	0
T2	264096	427	0	0
T3	1724136	35728	0	0
T4	11257008	44454	0	0
T7	21455832	4566	0	0
T8	404904	5667	0	0
T9	6283080	5882	0	0
T10	229248	3855	0	0
T11	9779808	9702	0	0
T12	548280	1975	0	0
T13	0	3143	0	0
T14	0	399	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	485215098	0	0
T1	23304	541	0	0
T2	264096	13160	0	0
T3	1724136	30366	0	0
T4	11257008	632939	0	0
T7	21455832	761324	0	0
T8	404904	8476	0	0
T9	6283080	236017	0	0
T10	229248	4850	0	0
T11	9779808	370054	0	0
T12	548280	36659	0	0
T13	0	2588	0	0
T14	0	821	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8026608	0	0
T1	23304	484	0	0
T2	264096	427	0	0
T3	1724136	35728	0	0
T4	11257008	44454	0	0
T7	21455832	4566	0	0
T8	404904	5667	0	0
T9	6283080	5882	0	0
T10	229248	3855	0	0
T11	9779808	9702	0	0
T12	548280	1975	0	0
T13	0	3143	0	0
T14	0	399	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8026608	0	0
T1	23304	484	0	0
T2	264096	427	0	0
T3	1724136	35728	0	0
T4	11257008	44454	0	0
T7	21455832	4566	0	0
T8	404904	5667	0	0
T9	6283080	5882	0	0
T10	229248	3855	0	0
T11	9779808	9702	0	0
T12	548280	1975	0	0
T13	0	3143	0	0
T14	0	399	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37008632	0	0
T1	23304	551	0	0
T2	264096	837	0	0
T3	1724136	47163	0	0
T4	11257008	182038	0	0
T7	21455832	7269	0	0
T8	404904	5820	0	0
T9	6283080	13826	0	0
T10	229248	5049	0	0
T11	9779808	22081	0	0
T12	548280	4565	0	0
T13	0	3197	0	0
T14	0	502	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49091	0	21600
T1	971	1	0	1
T2	11004	0	0	1
T3	143678	998	0	2
T4	938084	48	0	2
T7	1787986	0	0	2
T8	33742	21	0	2
T9	523590	20	0	2
T10	19104	283	0	2
T11	814984	13	0	2
T12	45690	1	0	2
T13	16672	26	0	1
T14	2554	6	0	1
T15	0	25	0	0
T16	0	2	0	0
T17	0	20	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	23304	22536	0	0
T2	264096	263496	0	0
T3	1724136	1722720	0	0
T4	11257008	11252400	0	0
T7	21455832	21455376	0	0
T8	404904	404064	0	0
T9	6283080	6283032	0	0
T10	229248	221568	0	0
T11	9779808	9779712	0	0
T12	548280	547104	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8026608	0	0
T1	23304	484	0	0
T2	264096	427	0	0
T3	1724136	35728	0	0
T4	11257008	44454	0	0
T7	21455832	4566	0	0
T8	404904	5667	0	0
T9	6283080	5882	0	0
T10	229248	3855	0	0
T11	9779808	9702	0	0
T12	548280	1975	0	0
T13	0	3143	0	0
T14	0	399	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	900720	0	0
GntImpliesValid_A	443640624	900720	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	900720	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	13062113	0	0
ReadyAndValidImplyGrant_A	443640624	900720	0	0
ReqAndReadyImplyGrant_A	443640624	900720	0	0
ReqImpliesValid_A	443640624	2734672	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	900720	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	900720	0	0
T1	971	66	0	0
T2	11004	66	0	0
T3	71839	3360	0	0
T4	469042	4112	0	0
T7	893993	494	0	0
T8	16871	633	0	0
T9	261795	982	0	0
T10	9552	331	0	0
T11	407492	604	0	0
T12	22845	179	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	900720	0	0
T1	971	66	0	0
T2	11004	66	0	0
T3	71839	3360	0	0
T4	469042	4112	0	0
T7	893993	494	0	0
T8	16871	633	0	0
T9	261795	982	0	0
T10	9552	331	0	0
T11	407492	604	0	0
T12	22845	179	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	900720	0	0
T1	971	66	0	0
T2	11004	66	0	0
T3	71839	3360	0	0
T4	469042	4112	0	0
T7	893993	494	0	0
T8	16871	633	0	0
T9	261795	982	0	0
T10	9552	331	0	0
T11	407492	604	0	0
T12	22845	179	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	13062113	0	0
T1	971	41	0	0
T2	11004	498	0	0
T3	71839	2820	0	0
T4	469042	29762	0	0
T7	893993	1985	0	0
T8	16871	613	0	0
T9	261795	3393	0	0
T10	9552	266	0	0
T11	407492	2473	0	0
T12	22845	1395	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	900720	0	0
T1	971	66	0	0
T2	11004	66	0	0
T3	71839	3360	0	0
T4	469042	4112	0	0
T7	893993	494	0	0
T8	16871	633	0	0
T9	261795	982	0	0
T10	9552	331	0	0
T11	407492	604	0	0
T12	22845	179	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	900720	0	0
T1	971	66	0	0
T2	11004	66	0	0
T3	71839	3360	0	0
T4	469042	4112	0	0
T7	893993	494	0	0
T8	16871	633	0	0
T9	261795	982	0	0
T10	9552	331	0	0
T11	407492	604	0	0
T12	22845	179	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	2734672	0	0
T1	971	92	0	0
T2	11004	147	0	0
T3	71839	3901	0	0
T4	469042	7233	0	0
T7	893993	669	0	0
T8	16871	654	0	0
T9	261795	2222	0	0
T10	9552	399	0	0
T11	407492	857	0	0
T12	22845	275	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	900720	0	0
T1	971	66	0	0
T2	11004	66	0	0
T3	71839	3360	0	0
T4	469042	4112	0	0
T7	893993	494	0	0
T8	16871	633	0	0
T9	261795	982	0	0
T10	9552	331	0	0
T11	407492	604	0	0
T12	22845	179	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	897417	0	0
GntImpliesValid_A	443640624	897417	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	897417	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	13252822	0	0
ReadyAndValidImplyGrant_A	443640624	897417	0	0
ReqAndReadyImplyGrant_A	443640624	897417	0	0
ReqImpliesValid_A	443640624	2676920	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	897417	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	897417	0	0
T1	971	43	0	0
T2	11004	53	0	0
T3	71839	3409	0	0
T4	469042	4765	0	0
T7	893993	516	0	0
T8	16871	630	0	0
T9	261795	297	0	0
T10	9552	333	0	0
T11	407492	2096	0	0
T12	22845	244	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	897417	0	0
T1	971	43	0	0
T2	11004	53	0	0
T3	71839	3409	0	0
T4	469042	4765	0	0
T7	893993	516	0	0
T8	16871	630	0	0
T9	261795	297	0	0
T10	9552	333	0	0
T11	407492	2096	0	0
T12	22845	244	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	897417	0	0
T1	971	43	0	0
T2	11004	53	0	0
T3	71839	3409	0	0
T4	469042	4765	0	0
T7	893993	516	0	0
T8	16871	630	0	0
T9	261795	297	0	0
T10	9552	333	0	0
T11	407492	2096	0	0
T12	22845	244	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	13252822	0	0
T1	971	37	0	0
T2	11004	428	0	0
T3	71839	2813	0	0
T4	469042	29972	0	0
T7	893993	2229	0	0
T8	16871	603	0	0
T9	261795	1268	0	0
T10	9552	268	0	0
T11	407492	7320	0	0
T12	22845	1582	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	897417	0	0
T1	971	43	0	0
T2	11004	53	0	0
T3	71839	3409	0	0
T4	469042	4765	0	0
T7	893993	516	0	0
T8	16871	630	0	0
T9	261795	297	0	0
T10	9552	333	0	0
T11	407492	2096	0	0
T12	22845	244	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	897417	0	0
T1	971	43	0	0
T2	11004	53	0	0
T3	71839	3409	0	0
T4	469042	4765	0	0
T7	893993	516	0	0
T8	16871	630	0	0
T9	261795	297	0	0
T10	9552	333	0	0
T11	407492	2096	0	0
T12	22845	244	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	2676920	0	0
T1	971	50	0	0
T2	11004	60	0	0
T3	71839	4006	0	0
T4	469042	9789	0	0
T7	893993	742	0	0
T8	16871	658	0	0
T9	261795	442	0	0
T10	9552	401	0	0
T11	407492	4500	0	0
T12	22845	405	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	897417	0	0
T1	971	43	0	0
T2	11004	53	0	0
T3	71839	3409	0	0
T4	469042	4765	0	0
T7	893993	516	0	0
T8	16871	630	0	0
T9	261795	297	0	0
T10	9552	333	0	0
T11	407492	2096	0	0
T12	22845	244	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	210908	0	0
GntImpliesValid_A	443640624	210908	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	210908	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	3305086	0	0
ReadyAndValidImplyGrant_A	443640624	210908	0	0
ReqAndReadyImplyGrant_A	443640624	210908	0	0
ReqImpliesValid_A	443640624	570320	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	210908	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	210908	0	0
T1	971	9	0	0
T2	11004	13	0	0
T3	71839	578	0	0
T4	469042	657	0	0
T7	893993	140	0	0
T8	16871	160	0	0
T9	261795	464	0	0
T10	9552	61	0	0
T11	407492	489	0	0
T12	22845	51	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	210908	0	0
T1	971	9	0	0
T2	11004	13	0	0
T3	71839	578	0	0
T4	469042	657	0	0
T7	893993	140	0	0
T8	16871	160	0	0
T9	261795	464	0	0
T10	9552	61	0	0
T11	407492	489	0	0
T12	22845	51	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	210908	0	0
T1	971	9	0	0
T2	11004	13	0	0
T3	71839	578	0	0
T4	469042	657	0	0
T7	893993	140	0	0
T8	16871	160	0	0
T9	261795	464	0	0
T10	9552	61	0	0
T11	407492	489	0	0
T12	22845	51	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	3305086	0	0
T1	971	10	0	0
T2	11004	118	0	0
T3	71839	569	0	0
T4	469042	4741	0	0
T7	893993	567	0	0
T8	16871	160	0	0
T9	261795	1395	0	0
T10	9552	60	0	0
T11	407492	1650	0	0
T12	22845	365	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	210908	0	0
T1	971	9	0	0
T2	11004	13	0	0
T3	71839	578	0	0
T4	469042	657	0	0
T7	893993	140	0	0
T8	16871	160	0	0
T9	261795	464	0	0
T10	9552	61	0	0
T11	407492	489	0	0
T12	22845	51	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	210908	0	0
T1	971	9	0	0
T2	11004	13	0	0
T3	71839	578	0	0
T4	469042	657	0	0
T7	893993	140	0	0
T8	16871	160	0	0
T9	261795	464	0	0
T10	9552	61	0	0
T11	407492	489	0	0
T12	22845	51	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	570320	0	0
T1	971	9	0	0
T2	11004	24	0	0
T3	71839	588	0	0
T4	469042	944	0	0
T7	893993	158	0	0
T8	16871	161	0	0
T9	261795	1160	0	0
T10	9552	65	0	0
T11	407492	1123	0	0
T12	22845	57	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	210908	0	0
T1	971	9	0	0
T2	11004	13	0	0
T3	71839	578	0	0
T4	469042	657	0	0
T7	893993	140	0	0
T8	16871	160	0	0
T9	261795	464	0	0
T10	9552	61	0	0
T11	407492	489	0	0
T12	22845	51	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	224213	0	0
GntImpliesValid_A	443640624	224213	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	224213	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	3232162	0	0
ReadyAndValidImplyGrant_A	443640624	224213	0	0
ReqAndReadyImplyGrant_A	443640624	224213	0	0
ReqImpliesValid_A	443640624	616190	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	224213	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	224213	0	0
T1	971	5	0	0
T2	11004	11	0	0
T3	71839	1138	0	0
T4	469042	676	0	0
T7	893993	122	0	0
T8	16871	154	0	0
T9	261795	0	0	0
T10	9552	640	0	0
T11	407492	533	0	0
T12	22845	58	0	0
T13	0	187	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	224213	0	0
T1	971	5	0	0
T2	11004	11	0	0
T3	71839	1138	0	0
T4	469042	676	0	0
T7	893993	122	0	0
T8	16871	154	0	0
T9	261795	0	0	0
T10	9552	640	0	0
T11	407492	533	0	0
T12	22845	58	0	0
T13	0	187	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	224213	0	0
T1	971	5	0	0
T2	11004	11	0	0
T3	71839	1138	0	0
T4	469042	676	0	0
T7	893993	122	0	0
T8	16871	154	0	0
T9	261795	0	0	0
T10	9552	640	0	0
T11	407492	533	0	0
T12	22845	58	0	0
T13	0	187	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	3232162	0	0
T1	971	6	0	0
T2	11004	81	0	0
T3	71839	602	0	0
T4	469042	4919	0	0
T7	893993	526	0	0
T8	16871	153	0	0
T9	261795	1	0	0
T10	9552	64	0	0
T11	407492	1766	0	0
T12	22845	452	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	224213	0	0
T1	971	5	0	0
T2	11004	11	0	0
T3	71839	1138	0	0
T4	469042	676	0	0
T7	893993	122	0	0
T8	16871	154	0	0
T9	261795	0	0	0
T10	9552	640	0	0
T11	407492	533	0	0
T12	22845	58	0	0
T13	0	187	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	224213	0	0
T1	971	5	0	0
T2	11004	11	0	0
T3	71839	1138	0	0
T4	469042	676	0	0
T7	893993	122	0	0
T8	16871	154	0	0
T9	261795	0	0	0
T10	9552	640	0	0
T11	407492	533	0	0
T12	22845	58	0	0
T13	0	187	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	616190	0	0
T1	971	5	0	0
T2	11004	11	0	0
T3	71839	1675	0	0
T4	469042	945	0	0
T7	893993	158	0	0
T8	16871	156	0	0
T9	261795	0	0	0
T10	9552	1218	0	0
T11	407492	1322	0	0
T12	22845	71	0	0
T13	0	190	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	224213	0	0
T1	971	5	0	0
T2	11004	11	0	0
T3	71839	1138	0	0
T4	469042	676	0	0
T7	893993	122	0	0
T8	16871	154	0	0
T9	261795	0	0	0
T10	9552	640	0	0
T11	407492	533	0	0
T12	22845	58	0	0
T13	0	187	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	231409	0	0
GntImpliesValid_A	443640624	231409	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	231409	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	5554248	0	0
ReadyAndValidImplyGrant_A	443640624	231409	0	0
ReqAndReadyImplyGrant_A	443640624	231409	0	0
ReqImpliesValid_A	443640624	1321021	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	231409	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	231409	0	0
T1	971	4	0	0
T2	11004	12	0	0
T3	71839	622	0	0
T4	469042	1525	0	0
T7	893993	135	0	0
T8	16871	143	0	0
T9	261795	0	0	0
T10	9552	50	0	0
T11	407492	0	0	0
T12	22845	58	0	0
T13	0	203	0	0
T14	0	48	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	231409	0	0
T1	971	4	0	0
T2	11004	12	0	0
T3	71839	622	0	0
T4	469042	1525	0	0
T7	893993	135	0	0
T8	16871	143	0	0
T9	261795	0	0	0
T10	9552	50	0	0
T11	407492	0	0	0
T12	22845	58	0	0
T13	0	203	0	0
T14	0	48	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	231409	0	0
T1	971	4	0	0
T2	11004	12	0	0
T3	71839	622	0	0
T4	469042	1525	0	0
T7	893993	135	0	0
T8	16871	143	0	0
T9	261795	0	0	0
T10	9552	50	0	0
T11	407492	0	0	0
T12	22845	58	0	0
T13	0	203	0	0
T14	0	48	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	5554248	0	0
T1	971	24	0	0
T2	11004	534	0	0
T3	71839	3063	0	0
T4	469042	9601	0	0
T7	893993	795	0	0
T8	16871	1285	0	0
T9	261795	0	0	0
T10	9552	561	0	0
T11	407492	0	0	0
T12	22845	2288	0	0
T13	0	707	0	0
T14	0	151	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	231409	0	0
T1	971	4	0	0
T2	11004	12	0	0
T3	71839	622	0	0
T4	469042	1525	0	0
T7	893993	135	0	0
T8	16871	143	0	0
T9	261795	0	0	0
T10	9552	50	0	0
T11	407492	0	0	0
T12	22845	58	0	0
T13	0	203	0	0
T14	0	48	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	231409	0	0
T1	971	4	0	0
T2	11004	12	0	0
T3	71839	622	0	0
T4	469042	1525	0	0
T7	893993	135	0	0
T8	16871	143	0	0
T9	261795	0	0	0
T10	9552	50	0	0
T11	407492	0	0	0
T12	22845	58	0	0
T13	0	203	0	0
T14	0	48	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	1321021	0	0
T1	971	4	0	0
T2	11004	12	0	0
T3	71839	735	0	0
T4	469042	11888	0	0
T7	893993	197	0	0
T8	16871	151	0	0
T9	261795	0	0	0
T10	9552	103	0	0
T11	407492	0	0	0
T12	22845	337	0	0
T13	0	208	0	0
T14	0	71	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	231409	0	0
T1	971	4	0	0
T2	11004	12	0	0
T3	71839	622	0	0
T4	469042	1525	0	0
T7	893993	135	0	0
T8	16871	143	0	0
T9	261795	0	0	0
T10	9552	50	0	0
T11	407492	0	0	0
T12	22845	58	0	0
T13	0	203	0	0
T14	0	48	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	214653	0	0
GntImpliesValid_A	443640624	214653	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	214653	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	5391808	0	0
ReadyAndValidImplyGrant_A	443640624	214653	0	0
ReqAndReadyImplyGrant_A	443640624	214653	0	0
ReqImpliesValid_A	443640624	1156323	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	214653	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	214653	0	0
T1	971	17	0	0
T2	11004	10	0	0
T3	71839	1093	0	0
T4	469042	831	0	0
T7	893993	140	0	0
T8	16871	181	0	0
T9	261795	0	0	0
T10	9552	63	0	0
T11	407492	0	0	0
T12	22845	60	0	0
T13	0	178	0	0
T14	0	35	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	214653	0	0
T1	971	17	0	0
T2	11004	10	0	0
T3	71839	1093	0	0
T4	469042	831	0	0
T7	893993	140	0	0
T8	16871	181	0	0
T9	261795	0	0	0
T10	9552	63	0	0
T11	407492	0	0	0
T12	22845	60	0	0
T13	0	178	0	0
T14	0	35	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	214653	0	0
T1	971	17	0	0
T2	11004	10	0	0
T3	71839	1093	0	0
T4	469042	831	0	0
T7	893993	140	0	0
T8	16871	181	0	0
T9	261795	0	0	0
T10	9552	63	0	0
T11	407492	0	0	0
T12	22845	60	0	0
T13	0	178	0	0
T14	0	35	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	5391808	0	0
T1	971	75	0	0
T2	11004	148	0	0
T3	71839	3579	0	0
T4	469042	11980	0	0
T7	893993	1086	0	0
T8	16871	1438	0	0
T9	261795	0	0	0
T10	9552	681	0	0
T11	407492	0	0	0
T12	22845	897	0	0
T13	0	608	0	0
T14	0	125	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	214653	0	0
T1	971	17	0	0
T2	11004	10	0	0
T3	71839	1093	0	0
T4	469042	831	0	0
T7	893993	140	0	0
T8	16871	181	0	0
T9	261795	0	0	0
T10	9552	63	0	0
T11	407492	0	0	0
T12	22845	60	0	0
T13	0	178	0	0
T14	0	35	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	214653	0	0
T1	971	17	0	0
T2	11004	10	0	0
T3	71839	1093	0	0
T4	469042	831	0	0
T7	893993	140	0	0
T8	16871	181	0	0
T9	261795	0	0	0
T10	9552	63	0	0
T11	407492	0	0	0
T12	22845	60	0	0
T13	0	178	0	0
T14	0	35	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	1156323	0	0
T1	971	23	0	0
T2	11004	10	0	0
T3	71839	4219	0	0
T4	469042	6186	0	0
T7	893993	210	0	0
T8	16871	230	0	0
T9	261795	0	0	0
T10	9552	170	0	0
T11	407492	0	0	0
T12	22845	71	0	0
T13	0	197	0	0
T14	0	39	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	214653	0	0
T1	971	17	0	0
T2	11004	10	0	0
T3	71839	1093	0	0
T4	469042	831	0	0
T7	893993	140	0	0
T8	16871	181	0	0
T9	261795	0	0	0
T10	9552	63	0	0
T11	407492	0	0	0
T12	22845	60	0	0
T13	0	178	0	0
T14	0	35	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	211422	0	0
GntImpliesValid_A	443640624	211422	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	211422	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	5168551	0	0
ReadyAndValidImplyGrant_A	443640624	211422	0	0
ReqAndReadyImplyGrant_A	443640624	211422	0	0
ReqImpliesValid_A	443640624	1207253	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	211422	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	211422	0	0
T1	971	11	0	0
T2	11004	7	0	0
T3	71839	599	0	0
T4	469042	620	0	0
T7	893993	144	0	0
T8	16871	170	0	0
T9	261795	0	0	0
T10	9552	68	0	0
T11	407492	0	0	0
T12	22845	49	0	0
T13	0	188	0	0
T14	0	49	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	211422	0	0
T1	971	11	0	0
T2	11004	7	0	0
T3	71839	599	0	0
T4	469042	620	0	0
T7	893993	144	0	0
T8	16871	170	0	0
T9	261795	0	0	0
T10	9552	68	0	0
T11	407492	0	0	0
T12	22845	49	0	0
T13	0	188	0	0
T14	0	49	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	211422	0	0
T1	971	11	0	0
T2	11004	7	0	0
T3	71839	599	0	0
T4	469042	620	0	0
T7	893993	144	0	0
T8	16871	170	0	0
T9	261795	0	0	0
T10	9552	68	0	0
T11	407492	0	0	0
T12	22845	49	0	0
T13	0	188	0	0
T14	0	49	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	5168551	0	0
T1	971	42	0	0
T2	11004	61	0	0
T3	71839	2762	0	0
T4	469042	12931	0	0
T7	893993	813	0	0
T8	16871	870	0	0
T9	261795	0	0	0
T10	9552	1352	0	0
T11	407492	0	0	0
T12	22845	527	0	0
T13	0	657	0	0
T14	0	369	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	211422	0	0
T1	971	11	0	0
T2	11004	7	0	0
T3	71839	599	0	0
T4	469042	620	0	0
T7	893993	144	0	0
T8	16871	170	0	0
T9	261795	0	0	0
T10	9552	68	0	0
T11	407492	0	0	0
T12	22845	49	0	0
T13	0	188	0	0
T14	0	49	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	211422	0	0
T1	971	11	0	0
T2	11004	7	0	0
T3	71839	599	0	0
T4	469042	620	0	0
T7	893993	144	0	0
T8	16871	170	0	0
T9	261795	0	0	0
T10	9552	68	0	0
T11	407492	0	0	0
T12	22845	49	0	0
T13	0	188	0	0
T14	0	49	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	1207253	0	0
T1	971	21	0	0
T2	11004	7	0	0
T3	71839	704	0	0
T4	469042	1245	0	0
T7	893993	170	0	0
T8	16871	174	0	0
T9	261795	0	0	0
T10	9552	278	0	0
T11	407492	0	0	0
T12	22845	95	0	0
T13	0	192	0	0
T14	0	85	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	211422	0	0
T1	971	11	0	0
T2	11004	7	0	0
T3	71839	599	0	0
T4	469042	620	0	0
T7	893993	144	0	0
T8	16871	170	0	0
T9	261795	0	0	0
T10	9552	68	0	0
T11	407492	0	0	0
T12	22845	49	0	0
T13	0	188	0	0
T14	0	49	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	225835	0	0
GntImpliesValid_A	443640624	225835	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	225835	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	5652181	0	0
ReadyAndValidImplyGrant_A	443640624	225835	0	0
ReqAndReadyImplyGrant_A	443640624	225835	0	0
ReqImpliesValid_A	443640624	1405891	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	225835	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	225835	0	0
T1	971	17	0	0
T2	11004	16	0	0
T3	71839	1128	0	0
T4	469042	1192	0	0
T7	893993	131	0	0
T8	16871	170	0	0
T9	261795	0	0	0
T10	9552	48	0	0
T11	407492	0	0	0
T12	22845	57	0	0
T13	0	179	0	0
T14	0	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	225835	0	0
T1	971	17	0	0
T2	11004	16	0	0
T3	71839	1128	0	0
T4	469042	1192	0	0
T7	893993	131	0	0
T8	16871	170	0	0
T9	261795	0	0	0
T10	9552	48	0	0
T11	407492	0	0	0
T12	22845	57	0	0
T13	0	179	0	0
T14	0	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	225835	0	0
T1	971	17	0	0
T2	11004	16	0	0
T3	71839	1128	0	0
T4	469042	1192	0	0
T7	893993	131	0	0
T8	16871	170	0	0
T9	261795	0	0	0
T10	9552	48	0	0
T11	407492	0	0	0
T12	22845	57	0	0
T13	0	179	0	0
T14	0	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	5652181	0	0
T1	971	112	0	0
T2	11004	117	0	0
T3	71839	4120	0	0
T4	469042	14794	0	0
T7	893993	657	0	0
T8	16871	1169	0	0
T9	261795	0	0	0
T10	9552	708	0	0
T11	407492	0	0	0
T12	22845	2879	0	0
T13	0	616	0	0
T14	0	176	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	225835	0	0
T1	971	17	0	0
T2	11004	16	0	0
T3	71839	1128	0	0
T4	469042	1192	0	0
T7	893993	131	0	0
T8	16871	170	0	0
T9	261795	0	0	0
T10	9552	48	0	0
T11	407492	0	0	0
T12	22845	57	0	0
T13	0	179	0	0
T14	0	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	225835	0	0
T1	971	17	0	0
T2	11004	16	0	0
T3	71839	1128	0	0
T4	469042	1192	0	0
T7	893993	131	0	0
T8	16871	170	0	0
T9	261795	0	0	0
T10	9552	48	0	0
T11	407492	0	0	0
T12	22845	57	0	0
T13	0	179	0	0
T14	0	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	1405891	0	0
T1	971	29	0	0
T2	11004	20	0	0
T3	71839	2778	0	0
T4	469042	10368	0	0
T7	893993	153	0	0
T8	16871	192	0	0
T9	261795	0	0	0
T10	9552	131	0	0
T11	407492	0	0	0
T12	22845	231	0	0
T13	0	193	0	0
T14	0	69	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	225835	0	0
T1	971	17	0	0
T2	11004	16	0	0
T3	71839	1128	0	0
T4	469042	1192	0	0
T7	893993	131	0	0
T8	16871	170	0	0
T9	261795	0	0	0
T10	9552	48	0	0
T11	407492	0	0	0
T12	22845	57	0	0
T13	0	179	0	0
T14	0	40	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	209830	0	0
GntImpliesValid_A	443640624	209830	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	209830	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	3192665	0	0
ReadyAndValidImplyGrant_A	443640624	209830	0	0
ReqAndReadyImplyGrant_A	443640624	209830	0	0
ReqImpliesValid_A	443640624	520242	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	209830	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	209830	0	0
T1	971	5	0	0
T2	11004	13	0	0
T3	71839	585	0	0
T4	469042	1150	0	0
T7	893993	152	0	0
T8	16871	164	0	0
T9	261795	0	0	0
T10	9552	57	0	0
T11	407492	0	0	0
T12	22845	68	0	0
T13	0	173	0	0
T14	0	37	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	209830	0	0
T1	971	5	0	0
T2	11004	13	0	0
T3	71839	585	0	0
T4	469042	1150	0	0
T7	893993	152	0	0
T8	16871	164	0	0
T9	261795	0	0	0
T10	9552	57	0	0
T11	407492	0	0	0
T12	22845	68	0	0
T13	0	173	0	0
T14	0	37	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	209830	0	0
T1	971	5	0	0
T2	11004	13	0	0
T3	71839	585	0	0
T4	469042	1150	0	0
T7	893993	152	0	0
T8	16871	164	0	0
T9	261795	0	0	0
T10	9552	57	0	0
T11	407492	0	0	0
T12	22845	68	0	0
T13	0	173	0	0
T14	0	37	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	3192665	0	0
T1	971	6	0	0
T2	11004	77	0	0
T3	71839	573	0	0
T4	469042	5680	0	0
T7	893993	597	0	0
T8	16871	162	0	0
T9	261795	1	0	0
T10	9552	59	0	0
T11	407492	1	0	0
T12	22845	632	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	209830	0	0
T1	971	5	0	0
T2	11004	13	0	0
T3	71839	585	0	0
T4	469042	1150	0	0
T7	893993	152	0	0
T8	16871	164	0	0
T9	261795	0	0	0
T10	9552	57	0	0
T11	407492	0	0	0
T12	22845	68	0	0
T13	0	173	0	0
T14	0	37	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	209830	0	0
T1	971	5	0	0
T2	11004	13	0	0
T3	71839	585	0	0
T4	469042	1150	0	0
T7	893993	152	0	0
T8	16871	164	0	0
T9	261795	0	0	0
T10	9552	57	0	0
T11	407492	0	0	0
T12	22845	68	0	0
T13	0	173	0	0
T14	0	37	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	520242	0	0
T1	971	5	0	0
T2	11004	14	0	0
T3	71839	598	0	0
T4	469042	3015	0	0
T7	893993	231	0	0
T8	16871	167	0	0
T9	261795	0	0	0
T10	9552	58	0	0
T11	407492	0	0	0
T12	22845	80	0	0
T13	0	173	0	0
T14	0	39	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	209830	0	0
T1	971	5	0	0
T2	11004	13	0	0
T3	71839	585	0	0
T4	469042	1150	0	0
T7	893993	152	0	0
T8	16871	164	0	0
T9	261795	0	0	0
T10	9552	57	0	0
T11	407492	0	0	0
T12	22845	68	0	0
T13	0	173	0	0
T14	0	37	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	213324	0	0
GntImpliesValid_A	443640624	213324	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	213324	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	3257365	0	0
ReadyAndValidImplyGrant_A	443640624	213324	0	0
ReqAndReadyImplyGrant_A	443640624	213324	0	0
ReqImpliesValid_A	443640624	562364	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	213324	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	213324	0	0
T1	971	11	0	0
T2	11004	7	0	0
T3	71839	1021	0	0
T4	469042	1148	0	0
T7	893993	118	0	0
T8	16871	154	0	0
T9	261795	0	0	0
T10	9552	63	0	0
T11	407492	986	0	0
T12	22845	62	0	0
T13	0	172	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	213324	0	0
T1	971	11	0	0
T2	11004	7	0	0
T3	71839	1021	0	0
T4	469042	1148	0	0
T7	893993	118	0	0
T8	16871	154	0	0
T9	261795	0	0	0
T10	9552	63	0	0
T11	407492	986	0	0
T12	22845	62	0	0
T13	0	172	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	213324	0	0
T1	971	11	0	0
T2	11004	7	0	0
T3	71839	1021	0	0
T4	469042	1148	0	0
T7	893993	118	0	0
T8	16871	154	0	0
T9	261795	0	0	0
T10	9552	63	0	0
T11	407492	986	0	0
T12	22845	62	0	0
T13	0	172	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	3257365	0	0
T1	971	12	0	0
T2	11004	49	0	0
T3	71839	909	0	0
T4	469042	5283	0	0
T7	893993	492	0	0
T8	16871	154	0	0
T9	261795	1	0	0
T10	9552	66	0	0
T11	407492	3265	0	0
T12	22845	498	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	213324	0	0
T1	971	11	0	0
T2	11004	7	0	0
T3	71839	1021	0	0
T4	469042	1148	0	0
T7	893993	118	0	0
T8	16871	154	0	0
T9	261795	0	0	0
T10	9552	63	0	0
T11	407492	986	0	0
T12	22845	62	0	0
T13	0	172	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	213324	0	0
T1	971	11	0	0
T2	11004	7	0	0
T3	71839	1021	0	0
T4	469042	1148	0	0
T7	893993	118	0	0
T8	16871	154	0	0
T9	261795	0	0	0
T10	9552	63	0	0
T11	407492	986	0	0
T12	22845	62	0	0
T13	0	172	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	562364	0	0
T1	971	11	0	0
T2	11004	7	0	0
T3	71839	1134	0	0
T4	469042	6256	0	0
T7	893993	138	0	0
T8	16871	155	0	0
T9	261795	0	0	0
T10	9552	63	0	0
T11	407492	2310	0	0
T12	22845	95	0	0
T13	0	172	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	213324	0	0
T1	971	11	0	0
T2	11004	7	0	0
T3	71839	1021	0	0
T4	469042	1148	0	0
T7	893993	118	0	0
T8	16871	154	0	0
T9	261795	0	0	0
T10	9552	63	0	0
T11	407492	986	0	0
T12	22845	62	0	0
T13	0	172	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	232099	0	0
GntImpliesValid_A	443640624	232099	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	232099	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	3311894	0	0
ReadyAndValidImplyGrant_A	443640624	232099	0	0
ReqAndReadyImplyGrant_A	443640624	232099	0	0
ReqImpliesValid_A	443640624	651405	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	232099	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	232099	0	0
T1	971	16	0	0
T2	11004	13	0	0
T3	71839	584	0	0
T4	469042	2154	0	0
T7	893993	130	0	0
T8	16871	166	0	0
T9	261795	489	0	0
T10	9552	65	0	0
T11	407492	469	0	0
T12	22845	65	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	232099	0	0
T1	971	16	0	0
T2	11004	13	0	0
T3	71839	584	0	0
T4	469042	2154	0	0
T7	893993	130	0	0
T8	16871	166	0	0
T9	261795	489	0	0
T10	9552	65	0	0
T11	407492	469	0	0
T12	22845	65	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	232099	0	0
T1	971	16	0	0
T2	11004	13	0	0
T3	71839	584	0	0
T4	469042	2154	0	0
T7	893993	130	0	0
T8	16871	166	0	0
T9	261795	489	0	0
T10	9552	65	0	0
T11	407492	469	0	0
T12	22845	65	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	3311894	0	0
T1	971	16	0	0
T2	11004	125	0	0
T3	71839	572	0	0
T4	469042	8525	0	0
T7	893993	531	0	0
T8	16871	166	0	0
T9	261795	1698	0	0
T10	9552	66	0	0
T11	407492	1541	0	0
T12	22845	434	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	232099	0	0
T1	971	16	0	0
T2	11004	13	0	0
T3	71839	584	0	0
T4	469042	2154	0	0
T7	893993	130	0	0
T8	16871	166	0	0
T9	261795	489	0	0
T10	9552	65	0	0
T11	407492	469	0	0
T12	22845	65	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	232099	0	0
T1	971	16	0	0
T2	11004	13	0	0
T3	71839	584	0	0
T4	469042	2154	0	0
T7	893993	130	0	0
T8	16871	166	0	0
T9	261795	489	0	0
T10	9552	65	0	0
T11	407492	469	0	0
T12	22845	65	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	651405	0	0
T1	971	17	0	0
T2	11004	23	0	0
T3	71839	597	0	0
T4	469042	13700	0	0
T7	893993	159	0	0
T8	16871	167	0	0
T9	261795	1163	0	0
T10	9552	67	0	0
T11	407492	1073	0	0
T12	22845	97	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	232099	0	0
T1	971	16	0	0
T2	11004	13	0	0
T3	71839	584	0	0
T4	469042	2154	0	0
T7	893993	130	0	0
T8	16871	166	0	0
T9	261795	489	0	0
T10	9552	65	0	0
T11	407492	469	0	0
T12	22845	65	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	225850	0	0
GntImpliesValid_A	443640624	225850	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	225850	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	3304873	0	0
ReadyAndValidImplyGrant_A	443640624	225850	0	0
ReqAndReadyImplyGrant_A	443640624	225850	0	0
ReqImpliesValid_A	443640624	610461	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	225850	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	225850	0	0
T1	971	14	0	0
T2	11004	18	0	0
T3	71839	580	0	0
T4	469042	626	0	0
T7	893993	146	0	0
T8	16871	147	0	0
T9	261795	508	0	0
T10	9552	45	0	0
T11	407492	0	0	0
T12	22845	53	0	0
T13	0	186	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	225850	0	0
T1	971	14	0	0
T2	11004	18	0	0
T3	71839	580	0	0
T4	469042	626	0	0
T7	893993	146	0	0
T8	16871	147	0	0
T9	261795	508	0	0
T10	9552	45	0	0
T11	407492	0	0	0
T12	22845	53	0	0
T13	0	186	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	225850	0	0
T1	971	14	0	0
T2	11004	18	0	0
T3	71839	580	0	0
T4	469042	626	0	0
T7	893993	146	0	0
T8	16871	147	0	0
T9	261795	508	0	0
T10	9552	45	0	0
T11	407492	0	0	0
T12	22845	53	0	0
T13	0	186	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	3304873	0	0
T1	971	15	0	0
T2	11004	153	0	0
T3	71839	565	0	0
T4	469042	4730	0	0
T7	893993	540	0	0
T8	16871	147	0	0
T9	261795	1681	0	0
T10	9552	48	0	0
T11	407492	1	0	0
T12	22845	323	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	225850	0	0
T1	971	14	0	0
T2	11004	18	0	0
T3	71839	580	0	0
T4	469042	626	0	0
T7	893993	146	0	0
T8	16871	147	0	0
T9	261795	508	0	0
T10	9552	45	0	0
T11	407492	0	0	0
T12	22845	53	0	0
T13	0	186	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	225850	0	0
T1	971	14	0	0
T2	11004	18	0	0
T3	71839	580	0	0
T4	469042	626	0	0
T7	893993	146	0	0
T8	16871	147	0	0
T9	261795	508	0	0
T10	9552	45	0	0
T11	407492	0	0	0
T12	22845	53	0	0
T13	0	186	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	610461	0	0
T1	971	14	0	0
T2	11004	24	0	0
T3	71839	596	0	0
T4	469042	859	0	0
T7	893993	212	0	0
T8	16871	148	0	0
T9	261795	1243	0	0
T10	9552	45	0	0
T11	407492	0	0	0
T12	22845	57	0	0
T13	0	187	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	225850	0	0
T1	971	14	0	0
T2	11004	18	0	0
T3	71839	580	0	0
T4	469042	626	0	0
T7	893993	146	0	0
T8	16871	147	0	0
T9	261795	508	0	0
T10	9552	45	0	0
T11	407492	0	0	0
T12	22845	53	0	0
T13	0	186	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	222598	0	0
GntImpliesValid_A	443640624	222598	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	222598	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	3283853	0	0
ReadyAndValidImplyGrant_A	443640624	222598	0	0
ReqAndReadyImplyGrant_A	443640624	222598	0	0
ReqImpliesValid_A	443640624	557402	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	222598	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	222598	0	0
T1	971	11	0	0
T2	11004	10	0	0
T3	71839	1078	0	0
T4	469042	2576	0	0
T7	893993	111	0	0
T8	16871	177	0	0
T9	261795	0	0	0
T10	9552	65	0	0
T11	407492	0	0	0
T12	22845	71	0	0
T13	0	204	0	0
T14	0	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	222598	0	0
T1	971	11	0	0
T2	11004	10	0	0
T3	71839	1078	0	0
T4	469042	2576	0	0
T7	893993	111	0	0
T8	16871	177	0	0
T9	261795	0	0	0
T10	9552	65	0	0
T11	407492	0	0	0
T12	22845	71	0	0
T13	0	204	0	0
T14	0	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	222598	0	0
T1	971	11	0	0
T2	11004	10	0	0
T3	71839	1078	0	0
T4	469042	2576	0	0
T7	893993	111	0	0
T8	16871	177	0	0
T9	261795	0	0	0
T10	9552	65	0	0
T11	407492	0	0	0
T12	22845	71	0	0
T13	0	204	0	0
T14	0	38	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	3283853	0	0
T1	971	11	0	0
T2	11004	82	0	0
T3	71839	971	0	0
T4	469042	10226	0	0
T7	893993	422	0	0
T8	16871	177	0	0
T9	261795	1	0	0
T10	9552	67	0	0
T11	407492	1	0	0
T12	22845	537	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	222598	0	0
T1	971	11	0	0
T2	11004	10	0	0
T3	71839	1078	0	0
T4	469042	2576	0	0
T7	893993	111	0	0
T8	16871	177	0	0
T9	261795	0	0	0
T10	9552	65	0	0
T11	407492	0	0	0
T12	22845	71	0	0
T13	0	204	0	0
T14	0	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	222598	0	0
T1	971	11	0	0
T2	11004	10	0	0
T3	71839	1078	0	0
T4	469042	2576	0	0
T7	893993	111	0	0
T8	16871	177	0	0
T9	261795	0	0	0
T10	9552	65	0	0
T11	407492	0	0	0
T12	22845	71	0	0
T13	0	204	0	0
T14	0	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	557402	0	0
T1	971	12	0	0
T2	11004	18	0	0
T3	71839	1186	0	0
T4	469042	7619	0	0
T7	893993	166	0	0
T8	16871	178	0	0
T9	261795	0	0	0
T10	9552	66	0	0
T11	407492	0	0	0
T12	22845	94	0	0
T13	0	204	0	0
T14	0	39	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	222598	0	0
T1	971	11	0	0
T2	11004	10	0	0
T3	71839	1078	0	0
T4	469042	2576	0	0
T7	893993	111	0	0
T8	16871	177	0	0
T9	261795	0	0	0
T10	9552	65	0	0
T11	407492	0	0	0
T12	22845	71	0	0
T13	0	204	0	0
T14	0	38	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	227210	0	0
GntImpliesValid_A	443640624	227210	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	227210	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	3250284	0	0
ReadyAndValidImplyGrant_A	443640624	227210	0	0
ReqAndReadyImplyGrant_A	443640624	227210	0	0
ReqImpliesValid_A	443640624	613097	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	227210	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	227210	0	0
T1	971	10	0	0
T2	11004	6	0	0
T3	71839	1047	0	0
T4	469042	1126	0	0
T7	893993	143	0	0
T8	16871	155	0	0
T9	261795	0	0	0
T10	9552	60	0	0
T11	407492	969	0	0
T12	22845	53	0	0
T13	0	184	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	227210	0	0
T1	971	10	0	0
T2	11004	6	0	0
T3	71839	1047	0	0
T4	469042	1126	0	0
T7	893993	143	0	0
T8	16871	155	0	0
T9	261795	0	0	0
T10	9552	60	0	0
T11	407492	969	0	0
T12	22845	53	0	0
T13	0	184	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	227210	0	0
T1	971	10	0	0
T2	11004	6	0	0
T3	71839	1047	0	0
T4	469042	1126	0	0
T7	893993	143	0	0
T8	16871	155	0	0
T9	261795	0	0	0
T10	9552	60	0	0
T11	407492	969	0	0
T12	22845	53	0	0
T13	0	184	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	3250284	0	0
T1	971	11	0	0
T2	11004	57	0	0
T3	71839	606	0	0
T4	469042	7321	0	0
T7	893993	568	0	0
T8	16871	155	0	0
T9	261795	1	0	0
T10	9552	62	0	0
T11	407492	3223	0	0
T12	22845	373	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	227210	0	0
T1	971	10	0	0
T2	11004	6	0	0
T3	71839	1047	0	0
T4	469042	1126	0	0
T7	893993	143	0	0
T8	16871	155	0	0
T9	261795	0	0	0
T10	9552	60	0	0
T11	407492	969	0	0
T12	22845	53	0	0
T13	0	184	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	227210	0	0
T1	971	10	0	0
T2	11004	6	0	0
T3	71839	1047	0	0
T4	469042	1126	0	0
T7	893993	143	0	0
T8	16871	155	0	0
T9	261795	0	0	0
T10	9552	60	0	0
T11	407492	969	0	0
T12	22845	53	0	0
T13	0	184	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	613097	0	0
T1	971	10	0	0
T2	11004	6	0	0
T3	71839	1489	0	0
T4	469042	1832	0	0
T7	893993	194	0	0
T8	16871	156	0	0
T9	261795	0	0	0
T10	9552	61	0	0
T11	407492	2264	0	0
T12	22845	84	0	0
T13	0	186	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	227210	0	0
T1	971	10	0	0
T2	11004	6	0	0
T3	71839	1047	0	0
T4	469042	1126	0	0
T7	893993	143	0	0
T8	16871	155	0	0
T9	261795	0	0	0
T10	9552	60	0	0
T11	407492	969	0	0
T12	22845	53	0	0
T13	0	184	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	225356	0	0
GntImpliesValid_A	443640624	225356	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	225356	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	3268466	0	0
ReadyAndValidImplyGrant_A	443640624	225356	0	0
ReqAndReadyImplyGrant_A	443640624	225356	0	0
ReqImpliesValid_A	443640624	604128	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	225356	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	225356	0	0
T1	971	19	0	0
T2	11004	7	0	0
T3	71839	1656	0	0
T4	469042	1591	0	0
T7	893993	132	0	0
T8	16871	172	0	0
T9	261795	0	0	0
T10	9552	65	0	0
T11	407492	0	0	0
T12	22845	54	0	0
T13	0	199	0	0
T14	0	36	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	225356	0	0
T1	971	19	0	0
T2	11004	7	0	0
T3	71839	1656	0	0
T4	469042	1591	0	0
T7	893993	132	0	0
T8	16871	172	0	0
T9	261795	0	0	0
T10	9552	65	0	0
T11	407492	0	0	0
T12	22845	54	0	0
T13	0	199	0	0
T14	0	36	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	225356	0	0
T1	971	19	0	0
T2	11004	7	0	0
T3	71839	1656	0	0
T4	469042	1591	0	0
T7	893993	132	0	0
T8	16871	172	0	0
T9	261795	0	0	0
T10	9552	65	0	0
T11	407492	0	0	0
T12	22845	54	0	0
T13	0	199	0	0
T14	0	36	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	3268466	0	0
T1	971	20	0	0
T2	11004	28	0	0
T3	71839	878	0	0
T4	469042	10389	0	0
T7	893993	564	0	0
T8	16871	171	0	0
T9	261795	1	0	0
T10	9552	65	0	0
T11	407492	1	0	0
T12	22845	368	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	225356	0	0
T1	971	19	0	0
T2	11004	7	0	0
T3	71839	1656	0	0
T4	469042	1591	0	0
T7	893993	132	0	0
T8	16871	172	0	0
T9	261795	0	0	0
T10	9552	65	0	0
T11	407492	0	0	0
T12	22845	54	0	0
T13	0	199	0	0
T14	0	36	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	225356	0	0
T1	971	19	0	0
T2	11004	7	0	0
T3	71839	1656	0	0
T4	469042	1591	0	0
T7	893993	132	0	0
T8	16871	172	0	0
T9	261795	0	0	0
T10	9552	65	0	0
T11	407492	0	0	0
T12	22845	54	0	0
T13	0	199	0	0
T14	0	36	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	604128	0	0
T1	971	19	0	0
T2	11004	7	0	0
T3	71839	2435	0	0
T4	469042	3132	0	0
T7	893993	154	0	0
T8	16871	174	0	0
T9	261795	0	0	0
T10	9552	68	0	0
T11	407492	0	0	0
T12	22845	80	0	0
T13	0	203	0	0
T14	0	37	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	225356	0	0
T1	971	19	0	0
T2	11004	7	0	0
T3	71839	1656	0	0
T4	469042	1591	0	0
T7	893993	132	0	0
T8	16871	172	0	0
T9	261795	0	0	0
T10	9552	65	0	0
T11	407492	0	0	0
T12	22845	54	0	0
T13	0	199	0	0
T14	0	36	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	213414	0	0
GntImpliesValid_A	443640624	213414	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	213414	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	3305260	0	0
ReadyAndValidImplyGrant_A	443640624	213414	0	0
ReqAndReadyImplyGrant_A	443640624	213414	0	0
ReqImpliesValid_A	443640624	586571	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	213414	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	213414	0	0
T1	971	10	0	0
T2	11004	7	0	0
T3	71839	1492	0	0
T4	469042	1573	0	0
T7	893993	142	0	0
T8	16871	146	0	0
T9	261795	555	0	0
T10	9552	66	0	0
T11	407492	0	0	0
T12	22845	48	0	0
T13	0	181	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	213414	0	0
T1	971	10	0	0
T2	11004	7	0	0
T3	71839	1492	0	0
T4	469042	1573	0	0
T7	893993	142	0	0
T8	16871	146	0	0
T9	261795	555	0	0
T10	9552	66	0	0
T11	407492	0	0	0
T12	22845	48	0	0
T13	0	181	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	213414	0	0
T1	971	10	0	0
T2	11004	7	0	0
T3	71839	1492	0	0
T4	469042	1573	0	0
T7	893993	142	0	0
T8	16871	146	0	0
T9	261795	555	0	0
T10	9552	66	0	0
T11	407492	0	0	0
T12	22845	48	0	0
T13	0	181	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	3305260	0	0
T1	971	11	0	0
T2	11004	64	0	0
T3	71839	614	0	0
T4	469042	6782	0	0
T7	893993	620	0	0
T8	16871	146	0	0
T9	261795	1945	0	0
T10	9552	63	0	0
T11	407492	1	0	0
T12	22845	369	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	213414	0	0
T1	971	10	0	0
T2	11004	7	0	0
T3	71839	1492	0	0
T4	469042	1573	0	0
T7	893993	142	0	0
T8	16871	146	0	0
T9	261795	555	0	0
T10	9552	66	0	0
T11	407492	0	0	0
T12	22845	48	0	0
T13	0	181	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	213414	0	0
T1	971	10	0	0
T2	11004	7	0	0
T3	71839	1492	0	0
T4	469042	1573	0	0
T7	893993	142	0	0
T8	16871	146	0	0
T9	261795	555	0	0
T10	9552	66	0	0
T11	407492	0	0	0
T12	22845	48	0	0
T13	0	181	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	586571	0	0
T1	971	10	0	0
T2	11004	7	0	0
T3	71839	2371	0	0
T4	469042	4368	0	0
T7	893993	182	0	0
T8	16871	147	0	0
T9	261795	1221	0	0
T10	9552	72	0	0
T11	407492	0	0	0
T12	22845	57	0	0
T13	0	182	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	213414	0	0
T1	971	10	0	0
T2	11004	7	0	0
T3	71839	1492	0	0
T4	469042	1573	0	0
T7	893993	142	0	0
T8	16871	146	0	0
T9	261795	555	0	0
T10	9552	66	0	0
T11	407492	0	0	0
T12	22845	48	0	0
T13	0	181	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	248412	0	0
GntImpliesValid_A	443640624	248412	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	248412	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	3375533	0	0
ReadyAndValidImplyGrant_A	443640624	248412	0	0
ReqAndReadyImplyGrant_A	443640624	248412	0	0
ReqImpliesValid_A	443640624	648264	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	248412	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	248412	0	0
T1	971	14	0	0
T2	11004	4	0	0
T3	71839	1083	0	0
T4	469042	1549	0	0
T7	893993	142	0	0
T8	16871	143	0	0
T9	261795	506	0	0
T10	9552	81	0	0
T11	407492	540	0	0
T12	22845	61	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	248412	0	0
T1	971	14	0	0
T2	11004	4	0	0
T3	71839	1083	0	0
T4	469042	1549	0	0
T7	893993	142	0	0
T8	16871	143	0	0
T9	261795	506	0	0
T10	9552	81	0	0
T11	407492	540	0	0
T12	22845	61	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	248412	0	0
T1	971	14	0	0
T2	11004	4	0	0
T3	71839	1083	0	0
T4	469042	1549	0	0
T7	893993	142	0	0
T8	16871	143	0	0
T9	261795	506	0	0
T10	9552	81	0	0
T11	407492	540	0	0
T12	22845	61	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	3375533	0	0
T1	971	15	0	0
T2	11004	34	0	0
T3	71839	984	0	0
T4	469042	8654	0	0
T7	893993	583	0	0
T8	16871	144	0	0
T9	261795	1680	0	0
T10	9552	83	0	0
T11	407492	1790	0	0
T12	22845	512	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	248412	0	0
T1	971	14	0	0
T2	11004	4	0	0
T3	71839	1083	0	0
T4	469042	1549	0	0
T7	893993	142	0	0
T8	16871	143	0	0
T9	261795	506	0	0
T10	9552	81	0	0
T11	407492	540	0	0
T12	22845	61	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	248412	0	0
T1	971	14	0	0
T2	11004	4	0	0
T3	71839	1083	0	0
T4	469042	1549	0	0
T7	893993	142	0	0
T8	16871	143	0	0
T9	261795	506	0	0
T10	9552	81	0	0
T11	407492	540	0	0
T12	22845	61	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	648264	0	0
T1	971	14	0	0
T2	11004	4	0	0
T3	71839	1183	0	0
T4	469042	6621	0	0
T7	893993	179	0	0
T8	16871	143	0	0
T9	261795	1211	0	0
T10	9552	82	0	0
T11	407492	1189	0	0
T12	22845	88	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	248412	0	0
T1	971	14	0	0
T2	11004	4	0	0
T3	71839	1083	0	0
T4	469042	1549	0	0
T7	893993	142	0	0
T8	16871	143	0	0
T9	261795	506	0	0
T10	9552	81	0	0
T11	407492	540	0	0
T12	22845	61	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	222834	0	0
GntImpliesValid_A	443640624	222834	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	222834	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	3271866	0	0
ReadyAndValidImplyGrant_A	443640624	222834	0	0
ReqAndReadyImplyGrant_A	443640624	222834	0	0
ReqImpliesValid_A	443640624	596052	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	222834	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	222834	0	0
T1	971	16	0	0
T2	11004	10	0	0
T3	71839	1138	0	0
T4	469042	1058	0	0
T7	893993	148	0	0
T8	16871	157	0	0
T9	261795	0	0	0
T10	9552	52	0	0
T11	407492	0	0	0
T12	22845	65	0	0
T13	0	183	0	0
T14	0	49	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	222834	0	0
T1	971	16	0	0
T2	11004	10	0	0
T3	71839	1138	0	0
T4	469042	1058	0	0
T7	893993	148	0	0
T8	16871	157	0	0
T9	261795	0	0	0
T10	9552	52	0	0
T11	407492	0	0	0
T12	22845	65	0	0
T13	0	183	0	0
T14	0	49	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	222834	0	0
T1	971	16	0	0
T2	11004	10	0	0
T3	71839	1138	0	0
T4	469042	1058	0	0
T7	893993	148	0	0
T8	16871	157	0	0
T9	261795	0	0	0
T10	9552	52	0	0
T11	407492	0	0	0
T12	22845	65	0	0
T13	0	183	0	0
T14	0	49	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	3271866	0	0
T1	971	16	0	0
T2	11004	86	0	0
T3	71839	585	0	0
T4	469042	5321	0	0
T7	893993	678	0	0
T8	16871	157	0	0
T9	261795	1	0	0
T10	9552	55	0	0
T11	407492	1	0	0
T12	22845	472	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	222834	0	0
T1	971	16	0	0
T2	11004	10	0	0
T3	71839	1138	0	0
T4	469042	1058	0	0
T7	893993	148	0	0
T8	16871	157	0	0
T9	261795	0	0	0
T10	9552	52	0	0
T11	407492	0	0	0
T12	22845	65	0	0
T13	0	183	0	0
T14	0	49	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	222834	0	0
T1	971	16	0	0
T2	11004	10	0	0
T3	71839	1138	0	0
T4	469042	1058	0	0
T7	893993	148	0	0
T8	16871	157	0	0
T9	261795	0	0	0
T10	9552	52	0	0
T11	407492	0	0	0
T12	22845	65	0	0
T13	0	183	0	0
T14	0	49	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	596052	0	0
T1	971	17	0	0
T2	11004	10	0	0
T3	71839	1692	0	0
T4	469042	5168	0	0
T7	893993	195	0	0
T8	16871	158	0	0
T9	261795	0	0	0
T10	9552	52	0	0
T11	407492	0	0	0
T12	22845	126	0	0
T13	0	183	0	0
T14	0	53	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	222834	0	0
T1	971	16	0	0
T2	11004	10	0	0
T3	71839	1138	0	0
T4	469042	1058	0	0
T7	893993	148	0	0
T8	16871	157	0	0
T9	261795	0	0	0
T10	9552	52	0	0
T11	407492	0	0	0
T12	22845	65	0	0
T13	0	183	0	0
T14	0	49	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	216066	0	0
GntImpliesValid_A	443640624	216066	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	216066	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	3245602	0	0
ReadyAndValidImplyGrant_A	443640624	216066	0	0
ReqAndReadyImplyGrant_A	443640624	216066	0	0
ReqImpliesValid_A	443640624	547473	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	216066	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	216066	0	0
T1	971	12	0	0
T2	11004	10	0	0
T3	71839	1642	0	0
T4	469042	1121	0	0
T7	893993	125	0	0
T8	16871	167	0	0
T9	261795	0	0	0
T10	9552	63	0	0
T11	407492	577	0	0
T12	22845	49	0	0
T13	0	188	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	216066	0	0
T1	971	12	0	0
T2	11004	10	0	0
T3	71839	1642	0	0
T4	469042	1121	0	0
T7	893993	125	0	0
T8	16871	167	0	0
T9	261795	0	0	0
T10	9552	63	0	0
T11	407492	577	0	0
T12	22845	49	0	0
T13	0	188	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	216066	0	0
T1	971	12	0	0
T2	11004	10	0	0
T3	71839	1642	0	0
T4	469042	1121	0	0
T7	893993	125	0	0
T8	16871	167	0	0
T9	261795	0	0	0
T10	9552	63	0	0
T11	407492	577	0	0
T12	22845	49	0	0
T13	0	188	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	3245602	0	0
T1	971	13	0	0
T2	11004	93	0	0
T3	71839	1006	0	0
T4	469042	5189	0	0
T7	893993	535	0	0
T8	16871	165	0	0
T9	261795	1	0	0
T10	9552	64	0	0
T11	407492	1944	0	0
T12	22845	406	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	216066	0	0
T1	971	12	0	0
T2	11004	10	0	0
T3	71839	1642	0	0
T4	469042	1121	0	0
T7	893993	125	0	0
T8	16871	167	0	0
T9	261795	0	0	0
T10	9552	63	0	0
T11	407492	577	0	0
T12	22845	49	0	0
T13	0	188	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	216066	0	0
T1	971	12	0	0
T2	11004	10	0	0
T3	71839	1642	0	0
T4	469042	1121	0	0
T7	893993	125	0	0
T8	16871	167	0	0
T9	261795	0	0	0
T10	9552	63	0	0
T11	407492	577	0	0
T12	22845	49	0	0
T13	0	188	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	547473	0	0
T1	971	12	0	0
T2	11004	13	0	0
T3	71839	2279	0	0
T4	469042	6138	0	0
T7	893993	140	0	0
T8	16871	170	0	0
T9	261795	0	0	0
T10	9552	65	0	0
T11	407492	1267	0	0
T12	22845	75	0	0
T13	0	188	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	216066	0	0
T1	971	12	0	0
T2	11004	10	0	0
T3	71839	1642	0	0
T4	469042	1121	0	0
T7	893993	125	0	0
T8	16871	167	0	0
T9	261795	0	0	0
T10	9552	63	0	0
T11	407492	577	0	0
T12	22845	49	0	0
T13	0	188	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	211726	0	0
GntImpliesValid_A	443640624	211726	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	211726	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	3219594	0	0
ReadyAndValidImplyGrant_A	443640624	211726	0	0
ReqAndReadyImplyGrant_A	443640624	211726	0	0
ReqImpliesValid_A	443640624	568872	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	211726	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	211726	0	0
T1	971	16	0	0
T2	11004	16	0	0
T3	71839	1124	0	0
T4	469042	616	0	0
T7	893993	127	0	0
T8	16871	157	0	0
T9	261795	0	0	0
T10	9552	54	0	0
T11	407492	509	0	0
T12	22845	52	0	0
T13	0	197	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	211726	0	0
T1	971	16	0	0
T2	11004	16	0	0
T3	71839	1124	0	0
T4	469042	616	0	0
T7	893993	127	0	0
T8	16871	157	0	0
T9	261795	0	0	0
T10	9552	54	0	0
T11	407492	509	0	0
T12	22845	52	0	0
T13	0	197	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	211726	0	0
T1	971	16	0	0
T2	11004	16	0	0
T3	71839	1124	0	0
T4	469042	616	0	0
T7	893993	127	0	0
T8	16871	157	0	0
T9	261795	0	0	0
T10	9552	54	0	0
T11	407492	509	0	0
T12	22845	52	0	0
T13	0	197	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	3219594	0	0
T1	971	15	0	0
T2	11004	102	0	0
T3	71839	622	0	0
T4	469042	4605	0	0
T7	893993	546	0	0
T8	16871	157	0	0
T9	261795	1	0	0
T10	9552	56	0	0
T11	407492	1791	0	0
T12	22845	348	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	211726	0	0
T1	971	16	0	0
T2	11004	16	0	0
T3	71839	1124	0	0
T4	469042	616	0	0
T7	893993	127	0	0
T8	16871	157	0	0
T9	261795	0	0	0
T10	9552	54	0	0
T11	407492	509	0	0
T12	22845	52	0	0
T13	0	197	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	211726	0	0
T1	971	16	0	0
T2	11004	16	0	0
T3	71839	1124	0	0
T4	469042	616	0	0
T7	893993	127	0	0
T8	16871	157	0	0
T9	261795	0	0	0
T10	9552	54	0	0
T11	407492	509	0	0
T12	22845	52	0	0
T13	0	197	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	568872	0	0
T1	971	18	0	0
T2	11004	30	0	0
T3	71839	1627	0	0
T4	469042	758	0	0
T7	893993	151	0	0
T8	16871	158	0	0
T9	261795	0	0	0
T10	9552	55	0	0
T11	407492	1154	0	0
T12	22845	69	0	0
T13	0	197	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	211726	0	0
T1	971	16	0	0
T2	11004	16	0	0
T3	71839	1124	0	0
T4	469042	616	0	0
T7	893993	127	0	0
T8	16871	157	0	0
T9	261795	0	0	0
T10	9552	54	0	0
T11	407492	509	0	0
T12	22845	52	0	0
T13	0	197	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	232682	0	0
GntImpliesValid_A	443640624	232682	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	232682	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	3257101	0	0
ReadyAndValidImplyGrant_A	443640624	232682	0	0
ReqAndReadyImplyGrant_A	443640624	232682	0	0
ReqImpliesValid_A	443640624	668161	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	232682	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	232682	0	0
T1	971	14	0	0
T2	11004	6	0	0
T3	71839	1177	0	0
T4	469042	2099	0	0
T7	893993	123	0	0
T8	16871	140	0	0
T9	261795	0	0	0
T10	9552	76	0	0
T11	407492	0	0	0
T12	22845	53	0	0
T13	0	166	0	0
T14	0	41	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	232682	0	0
T1	971	14	0	0
T2	11004	6	0	0
T3	71839	1177	0	0
T4	469042	2099	0	0
T7	893993	123	0	0
T8	16871	140	0	0
T9	261795	0	0	0
T10	9552	76	0	0
T11	407492	0	0	0
T12	22845	53	0	0
T13	0	166	0	0
T14	0	41	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	232682	0	0
T1	971	14	0	0
T2	11004	6	0	0
T3	71839	1177	0	0
T4	469042	2099	0	0
T7	893993	123	0	0
T8	16871	140	0	0
T9	261795	0	0	0
T10	9552	76	0	0
T11	407492	0	0	0
T12	22845	53	0	0
T13	0	166	0	0
T14	0	41	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	3257101	0	0
T1	971	15	0	0
T2	11004	56	0	0
T3	71839	590	0	0
T4	469042	10273	0	0
T7	893993	517	0	0
T8	16871	139	0	0
T9	261795	1	0	0
T10	9552	76	0	0
T11	407492	1	0	0
T12	22845	389	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	232682	0	0
T1	971	14	0	0
T2	11004	6	0	0
T3	71839	1177	0	0
T4	469042	2099	0	0
T7	893993	123	0	0
T8	16871	140	0	0
T9	261795	0	0	0
T10	9552	76	0	0
T11	407492	0	0	0
T12	22845	53	0	0
T13	0	166	0	0
T14	0	41	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	232682	0	0
T1	971	14	0	0
T2	11004	6	0	0
T3	71839	1177	0	0
T4	469042	2099	0	0
T7	893993	123	0	0
T8	16871	140	0	0
T9	261795	0	0	0
T10	9552	76	0	0
T11	407492	0	0	0
T12	22845	53	0	0
T13	0	166	0	0
T14	0	41	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	668161	0	0
T1	971	14	0	0
T2	11004	6	0	0
T3	71839	1765	0	0
T4	469042	10910	0	0
T7	893993	163	0	0
T8	16871	142	0	0
T9	261795	0	0	0
T10	9552	79	0	0
T11	407492	0	0	0
T12	22845	62	0	0
T13	0	166	0	0
T14	0	43	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	232682	0	0
T1	971	14	0	0
T2	11004	6	0	0
T3	71839	1177	0	0
T4	469042	2099	0	0
T7	893993	123	0	0
T8	16871	140	0	0
T9	261795	0	0	0
T10	9552	76	0	0
T11	407492	0	0	0
T12	22845	53	0	0
T13	0	166	0	0
T14	0	41	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	209636	0	0
GntImpliesValid_A	443640624	209636	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	209636	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	3235627	0	0
ReadyAndValidImplyGrant_A	443640624	209636	0	0
ReqAndReadyImplyGrant_A	443640624	209636	0	0
ReqImpliesValid_A	443640624	528038	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	0	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	209636	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	209636	0	0
T1	971	16	0	0
T2	11004	13	0	0
T3	71839	571	0	0
T4	469042	1113	0	0
T7	893993	121	0	0
T8	16871	142	0	0
T9	261795	0	0	0
T10	9552	55	0	0
T11	407492	0	0	0
T12	22845	47	0	0
T13	0	175	0	0
T14	0	26	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	209636	0	0
T1	971	16	0	0
T2	11004	13	0	0
T3	71839	571	0	0
T4	469042	1113	0	0
T7	893993	121	0	0
T8	16871	142	0	0
T9	261795	0	0	0
T10	9552	55	0	0
T11	407492	0	0	0
T12	22845	47	0	0
T13	0	175	0	0
T14	0	26	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	209636	0	0
T1	971	16	0	0
T2	11004	13	0	0
T3	71839	571	0	0
T4	469042	1113	0	0
T7	893993	121	0	0
T8	16871	142	0	0
T9	261795	0	0	0
T10	9552	55	0	0
T11	407492	0	0	0
T12	22845	47	0	0
T13	0	175	0	0
T14	0	26	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	3235627	0	0
T1	971	16	0	0
T2	11004	83	0	0
T3	71839	561	0	0
T4	469042	7599	0	0
T7	893993	469	0	0
T8	16871	143	0	0
T9	261795	1	0	0
T10	9552	56	0	0
T11	407492	1	0	0
T12	22845	341	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	209636	0	0
T1	971	16	0	0
T2	11004	13	0	0
T3	71839	571	0	0
T4	469042	1113	0	0
T7	893993	121	0	0
T8	16871	142	0	0
T9	261795	0	0	0
T10	9552	55	0	0
T11	407492	0	0	0
T12	22845	47	0	0
T13	0	175	0	0
T14	0	26	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	209636	0	0
T1	971	16	0	0
T2	11004	13	0	0
T3	71839	571	0	0
T4	469042	1113	0	0
T7	893993	121	0	0
T8	16871	142	0	0
T9	261795	0	0	0
T10	9552	55	0	0
T11	407492	0	0	0
T12	22845	47	0	0
T13	0	175	0	0
T14	0	26	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	528038	0	0
T1	971	17	0	0
T2	11004	23	0	0
T3	71839	582	0	0
T4	469042	2699	0	0
T7	893993	138	0	0
T8	16871	142	0	0
T9	261795	0	0	0
T10	9552	57	0	0
T11	407492	0	0	0
T12	22845	51	0	0
T13	0	176	0	0
T14	0	27	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	209636	0	0
T1	971	16	0	0
T2	11004	13	0	0
T3	71839	571	0	0
T4	469042	1113	0	0
T7	893993	121	0	0
T8	16871	142	0	0
T9	261795	0	0	0
T10	9552	55	0	0
T11	407492	0	0	0
T12	22845	47	0	0
T13	0	175	0	0
T14	0	26	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	905374	0	0
GntImpliesValid_A	443640624	905374	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	905374	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	12493512	0	0
ReadyAndValidImplyGrant_A	443640624	905374	0	0
ReqAndReadyImplyGrant_A	443640624	905374	0	0
ReqImpliesValid_A	443640624	2496448	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	19961	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	905374	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	905374	0	0
T1	971	62	0	0
T2	11004	55	0	0
T3	71839	4922	0	0
T4	469042	4984	0	0
T7	893993	457	0	0
T8	16871	640	0	0
T9	261795	1810	0	0
T10	9552	1053	0	0
T11	407492	1357	0	0
T12	22845	213	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	905374	0	0
T1	971	62	0	0
T2	11004	55	0	0
T3	71839	4922	0	0
T4	469042	4984	0	0
T7	893993	457	0	0
T8	16871	640	0	0
T9	261795	1810	0	0
T10	9552	1053	0	0
T11	407492	1357	0	0
T12	22845	213	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	905374	0	0
T1	971	62	0	0
T2	11004	55	0	0
T3	71839	4922	0	0
T4	469042	4984	0	0
T7	893993	457	0	0
T8	16871	640	0	0
T9	261795	1810	0	0
T10	9552	1053	0	0
T11	407492	1357	0	0
T12	22845	213	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	12493512	0	0
T1	971	1	0	0
T2	11004	335	0	0
T3	71839	1	0	0
T4	469042	30699	0	0
T7	893993	1479	0	0
T8	16871	1	0	0
T9	261795	4898	0	0
T10	9552	3	0	0
T11	407492	3877	0	0
T12	22845	1307	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	905374	0	0
T1	971	62	0	0
T2	11004	55	0	0
T3	71839	4922	0	0
T4	469042	4984	0	0
T7	893993	457	0	0
T8	16871	640	0	0
T9	261795	1810	0	0
T10	9552	1053	0	0
T11	407492	1357	0	0
T12	22845	213	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	905374	0	0
T1	971	62	0	0
T2	11004	55	0	0
T3	71839	4922	0	0
T4	469042	4984	0	0
T7	893993	457	0	0
T8	16871	640	0	0
T9	261795	1810	0	0
T10	9552	1053	0	0
T11	407492	1357	0	0
T12	22845	213	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	2496448	0	0
T1	971	62	0	0
T2	11004	81	0	0
T3	71839	4922	0	0
T4	469042	11495	0	0
T7	893993	595	0	0
T8	16871	640	0	0
T9	261795	3939	0	0
T10	9552	1053	0	0
T11	407492	2527	0	0
T12	22845	377	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	19961	0	900
T3	71839	486	0	1
T4	469042	4	0	1
T7	893993	0	0	1
T8	16871	9	0	1
T9	261795	20	0	1
T10	9552	280	0	1
T11	407492	13	0	1
T12	22845	1	0	1
T13	16672	12	0	1
T14	2554	5	0	1
T15	0	9	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	905374	0	0
T1	971	62	0	0
T2	11004	55	0	0
T3	71839	4922	0	0
T4	469042	4984	0	0
T7	893993	457	0	0
T8	16871	640	0	0
T9	261795	1810	0	0
T10	9552	1053	0	0
T11	407492	1357	0	0
T12	22845	213	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443640624	443515803	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443640624	893620	0	0
GntImpliesValid_A	443640624	893620	0	0
GrantKnown_A	443640624	443515803	0	0
IdxKnown_A	443640624	443515803	0	0
IndexIsCorrect_A	443640624	893620	0	0
LockArbDecision_A	443640624	0	0	0
NoReadyValidNoGrant_A	443640624	372322632	0	0
ReadyAndValidImplyGrant_A	443640624	893620	0	0
ReqAndReadyImplyGrant_A	443640624	893620	0	0
ReqImpliesValid_A	443640624	14561064	0	0
ReqStaysHighUntilGranted0_M	443640624	0	0	0
RoundRobin_A	443640624	29130	0	900
ValidKnown_A	443640624	443515803	0	0
gen_data_port_assertion.DataFlow_A	443640624	893620	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	893620	0	0
T1	971	66	0	0
T2	11004	44	0	0
T3	71839	4101	0	0
T4	469042	5592	0	0
T7	893993	427	0	0
T8	16871	599	0	0
T9	261795	271	0	0
T10	9552	341	0	0
T11	407492	573	0	0
T12	22845	205	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	893620	0	0
T1	971	66	0	0
T2	11004	44	0	0
T3	71839	4101	0	0
T4	469042	5592	0	0
T7	893993	427	0	0
T8	16871	599	0	0
T9	261795	271	0	0
T10	9552	341	0	0
T11	407492	573	0	0
T12	22845	205	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	893620	0	0
T1	971	66	0	0
T2	11004	44	0	0
T3	71839	4101	0	0
T4	469042	5592	0	0
T7	893993	427	0	0
T8	16871	599	0	0
T9	261795	271	0	0
T10	9552	341	0	0
T11	407492	573	0	0
T12	22845	205	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	372322632	0	0
T1	971	1	0	0
T2	11004	9751	0	0
T3	71839	1	0	0
T4	469042	382963	0	0
T7	893993	743525	0	0
T8	16871	1	0	0
T9	261795	218048	0	0
T10	9552	1	0	0
T11	407492	339406	0	0
T12	22845	18965	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	893620	0	0
T1	971	66	0	0
T2	11004	44	0	0
T3	71839	4101	0	0
T4	469042	5592	0	0
T7	893993	427	0	0
T8	16871	599	0	0
T9	261795	271	0	0
T10	9552	341	0	0
T11	407492	573	0	0
T12	22845	205	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	893620	0	0
T1	971	66	0	0
T2	11004	44	0	0
T3	71839	4101	0	0
T4	469042	5592	0	0
T7	893993	427	0	0
T8	16871	599	0	0
T9	261795	271	0	0
T10	9552	341	0	0
T11	407492	573	0	0
T12	22845	205	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	14561064	0	0
T1	971	66	0	0
T2	11004	273	0	0
T3	71839	4101	0	0
T4	469042	48870	0	0
T7	893993	1815	0	0
T8	16871	599	0	0
T9	261795	1225	0	0
T10	9552	341	0	0
T11	407492	2495	0	0
T12	22845	1531	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	29130	0	900
T1	971	1	0	1
T2	11004	0	0	1
T3	71839	512	0	1
T4	469042	44	0	1
T7	893993	0	0	1
T8	16871	12	0	1
T9	261795	0	0	1
T10	9552	3	0	1
T11	407492	0	0	1
T12	22845	0	0	1
T13	0	14	0	0
T14	0	1	0	0
T15	0	16	0	0
T16	0	2	0	0
T17	0	20	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	443515803	0	0
T1	971	939	0	0
T2	11004	10979	0	0
T3	71839	71780	0	0
T4	469042	468850	0	0
T7	893993	893974	0	0
T8	16871	16836	0	0
T9	261795	261793	0	0
T10	9552	9232	0	0
T11	407492	407488	0	0
T12	22845	22796	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443640624	893620	0	0
T1	971	66	0	0
T2	11004	44	0	0
T3	71839	4101	0	0
T4	469042	5592	0	0
T7	893993	427	0	0
T8	16871	599	0	0
T9	261795	271	0	0
T10	9552	341	0	0
T11	407492	573	0	0
T12	22845	205	0	0