Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[1] 2352499 1 T1 1823 T2 95 T3 145
values[2] 165522 1 T1 58 T2 4 T3 11
values[3] 34652 1 T1 4 T2 1 T7 3
values[4] 21128 1 T12 1 T47 28 T15 11
values[5] 15262 1 T47 21 T15 11 T50 3
values[6] 12075 1 T47 14 T15 11 T50 3
values[7] 9933 1 T47 12 T15 11 T50 3
values[8] 8803 1 T47 3 T15 11 T50 3
values[9] 7708 1 T15 11 T50 3 T16 101
values[10] 6694 1 T15 11 T50 3 T16 114
values[11] 6033 1 T15 12 T50 3 T16 88
values[12] 5375 1 T15 11 T50 3 T16 49
values[13] 4946 1 T15 11 T50 3 T16 48
values[14] 4509 1 T15 11 T50 3 T16 56
values[15] 4165 1 T15 11 T50 3 T16 56
values[16] 3665 1 T15 11 T50 3 T16 45
values[17] 3288 1 T15 11 T50 3 T16 41
values[18] 3234 1 T15 11 T50 3 T16 46
values[19] 3253 1 T15 11 T50 3 T16 36
values[20] 3321 1 T15 11 T50 3 T16 29
values[21] 3108 1 T15 11 T50 3 T16 25
values[22] 2819 1 T15 11 T50 3 T16 24
values[23] 2548 1 T15 11 T50 3 T16 13
values[24] 2468 1 T15 11 T50 3 T16 17
values[25] 2247 1 T15 11 T50 3 T16 16
values[26] 2230 1 T15 11 T50 3 T16 9
values[27] 2136 1 T15 11 T50 3 T16 6
values[28] 2004 1 T15 11 T50 3 T16 12
values[29] 1959 1 T15 12 T50 3 T16 9
values[30] 1966 1 T15 11 T50 3 T16 22
values[31] 1812 1 T15 11 T50 3 T16 36
values[32] 1743 1 T15 11 T50 3 T16 43
values[33] 1617 1 T15 11 T50 3 T16 30
values[34] 1623 1 T15 11 T50 3 T16 12
values[35] 1548 1 T15 11 T50 3 T16 16
values[36] 1524 1 T15 11 T50 3 T16 11
values[37] 1492 1 T15 11 T50 4 T16 11
values[38] 1459 1 T15 11 T50 3 T16 6
values[39] 1479 1 T15 12 T50 3 T16 3
values[40] 1410 1 T15 11 T50 3 T16 6
values[41] 1421 1 T15 11 T50 3 T16 8
values[42] 1353 1 T15 11 T50 4 T16 8
values[43] 1337 1 T15 11 T50 3 T16 18
values[44] 1314 1 T15 11 T50 3 T16 16
values[45] 1273 1 T15 11 T50 3 T16 11
values[46] 1267 1 T15 11 T50 3 T16 6
values[47] 1333 1 T15 11 T50 3 T16 3
values[48] 1274 1 T15 12 T50 3 T16 2
values[49] 1256 1 T15 13 T50 3 T16 3
values[50] 1252 1 T15 11 T50 3 T16 3
values[51] 1247 1 T15 11 T50 3 T16 2
values[52] 1223 1 T15 11 T50 3 T16 3
values[53] 1211 1 T15 11 T50 3 T16 5
values[54] 1287 1 T15 11 T50 3 T16 10
values[55] 1208 1 T15 11 T50 3 T16 7
values[56] 1156 1 T15 11 T50 3 T16 5
values[57] 1131 1 T15 11 T50 3 T16 6
values[58] 1152 1 T15 11 T50 3 T16 2
values[59] 1116 1 T15 12 T50 3 T16 3
values[60] 1166 1 T15 12 T50 3 T16 7
values[61] 1385 1 T15 12 T50 3 T16 6
values[62] 2346 1 T15 11 T50 3 T16 6
values[63] 6965 1 T15 13 T50 5 T16 39
values[64] 109239 1 T15 1966 T50 549 T16 170


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[1] 2383416 1 T1 1823 T2 82 T3 138
values[2] 401039 1 T1 118 T2 24 T3 29
values[3] 37337 1 T1 8 T2 6 T7 42
values[4] 7153 1 T2 5 T7 4 T8 1
values[5] 3180 1 T12 1 T26 1 T15 12
values[6] 2404 1 T15 6 T50 4 T16 11
values[7] 1894 1 T15 5 T16 17 T105 1
values[8] 1639 1 T15 4 T16 15 T91 3
values[9] 1581 1 T15 3 T16 22 T91 7
values[10] 1509 1 T15 2 T16 23 T91 2
values[11] 1364 1 T15 2 T16 34 T91 6
values[12] 1183 1 T15 2 T16 28 T91 2
values[13] 1063 1 T15 2 T16 16 T91 2
values[14] 1087 1 T15 2 T16 18 T91 2
values[15] 1042 1 T15 2 T16 5 T91 2
values[16] 982 1 T15 2 T16 4 T91 8
values[17] 914 1 T15 2 T16 1 T91 4
values[18] 906 1 T15 2 T16 1 T91 4
values[19] 840 1 T15 2 T16 1 T91 8
values[20] 772 1 T15 2 T16 1 T91 3
values[21] 725 1 T15 2 T16 1 T91 3
values[22] 664 1 T15 2 T16 2 T91 2
values[23] 737 1 T15 2 T16 2 T91 10
values[24] 710 1 T15 2 T16 1 T91 3
values[25] 706 1 T15 2 T16 2 T91 3
values[26] 707 1 T15 2 T16 1 T91 3
values[27] 726 1 T15 2 T16 1 T91 2
values[28] 606 1 T15 2 T16 3 T91 2
values[29] 545 1 T15 2 T16 2 T91 7
values[30] 561 1 T15 2 T16 2 T91 7
values[31] 523 1 T15 2 T16 2 T91 2
values[32] 562 1 T15 2 T16 1 T91 3
values[33] 562 1 T15 2 T16 2 T91 4
values[34] 507 1 T15 2 T16 1 T91 4
values[35] 495 1 T15 2 T16 6 T91 2
values[36] 540 1 T15 2 T16 1 T91 8
values[37] 493 1 T15 2 T16 2 T91 4
values[38] 452 1 T15 2 T16 1 T91 5
values[39] 469 1 T15 2 T16 1 T91 6
values[40] 436 1 T15 2 T16 2 T91 2
values[41] 462 1 T15 2 T16 1 T91 2
values[42] 438 1 T15 2 T16 2 T91 3
values[43] 419 1 T15 2 T16 2 T91 3
values[44] 420 1 T15 2 T16 1 T91 2
values[45] 410 1 T15 2 T16 1 T91 2
values[46] 430 1 T15 2 T16 1 T91 2
values[47] 418 1 T15 2 T16 2 T91 5
values[48] 398 1 T15 2 T16 2 T91 3
values[49] 424 1 T15 2 T16 1 T91 4
values[50] 385 1 T15 2 T16 1 T91 2
values[51] 375 1 T15 2 T16 1 T91 3
values[52] 391 1 T15 2 T16 1 T91 6
values[53] 383 1 T15 2 T16 1 T91 8
values[54] 361 1 T15 2 T16 1 T91 3
values[55] 393 1 T15 2 T16 1 T91 5
values[56] 379 1 T15 2 T16 1 T91 3
values[57] 354 1 T15 2 T16 1 T91 4
values[58] 354 1 T15 2 T16 1 T91 5
values[59] 333 1 T15 2 T16 1 T91 3
values[60] 353 1 T15 2 T16 1 T91 4
values[61] 341 1 T15 2 T16 1 T91 3
values[62] 546 1 T15 2 T16 4 T91 3
values[63] 2122 1 T15 2 T16 39 T91 13
values[64] 26685 1 T15 329 T16 111 T91 222


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[1] 291879 1 T1 242 T2 2 T3 1
values[2] 1697634 1 T1 1378 T2 114 T3 124
values[3] 479671 1 T1 236 T2 24 T3 15
values[4] 46243 1 T1 1 T7 7 T10 4
values[5] 29293 1 T23 2 T47 18 T15 11
values[6] 22260 1 T23 4 T47 32 T15 11
values[7] 17648 1 T23 5 T47 46 T15 11
values[8] 14712 1 T23 4 T47 38 T15 11
values[9] 12838 1 T23 4 T47 22 T15 11
values[10] 10525 1 T23 4 T47 10 T15 11
values[11] 9721 1 T23 1 T15 12 T50 3
values[12] 8426 1 T15 11 T50 3 T16 93
values[13] 7758 1 T15 11 T50 3 T16 95
values[14] 6923 1 T15 11 T50 3 T16 75
values[15] 6310 1 T15 11 T50 3 T16 60
values[16] 5518 1 T15 11 T50 3 T16 53
values[17] 4904 1 T15 11 T50 3 T16 41
values[18] 4673 1 T15 11 T50 3 T16 42
values[19] 4407 1 T15 11 T50 3 T16 34
values[20] 4033 1 T15 11 T50 3 T16 30
values[21] 3677 1 T15 11 T50 3 T16 31
values[22] 3491 1 T15 12 T50 3 T16 63
values[23] 3071 1 T15 11 T50 3 T16 54
values[24] 2786 1 T15 11 T50 3 T16 43
values[25] 2533 1 T15 11 T50 3 T16 28
values[26] 2456 1 T15 11 T50 4 T16 13
values[27] 2408 1 T15 11 T50 3 T16 11
values[28] 2145 1 T15 11 T50 3 T16 9
values[29] 2110 1 T15 11 T50 3 T16 9
values[30] 1900 1 T15 11 T50 3 T16 6
values[31] 1827 1 T15 12 T50 3 T16 10
values[32] 1816 1 T15 12 T50 3 T16 12
values[33] 1707 1 T15 11 T50 3 T16 11
values[34] 1699 1 T15 11 T50 3 T16 6
values[35] 1706 1 T15 11 T50 3 T16 6
values[36] 1567 1 T15 11 T50 3 T16 4
values[37] 1486 1 T15 11 T50 3 T16 10
values[38] 1482 1 T15 11 T50 3 T16 9
values[39] 1411 1 T15 11 T50 3 T16 12
values[40] 1382 1 T15 12 T50 3 T16 8
values[41] 1372 1 T15 12 T50 3 T16 17
values[42] 1430 1 T15 11 T50 3 T16 17
values[43] 1352 1 T15 11 T50 3 T16 11
values[44] 1372 1 T15 11 T50 3 T16 10
values[45] 1416 1 T15 11 T50 3 T16 3
values[46] 1360 1 T15 11 T50 3 T16 7
values[47] 1343 1 T15 11 T50 3 T16 4
values[48] 1365 1 T15 11 T50 3 T16 3
values[49] 1299 1 T15 11 T50 3 T16 3
values[50] 1320 1 T15 11 T50 3 T16 3
values[51] 1274 1 T15 11 T50 3 T16 9
values[52] 1218 1 T15 11 T50 3 T16 6
values[53] 1209 1 T15 12 T50 3 T16 2
values[54] 1278 1 T15 11 T50 3 T16 4
values[55] 1222 1 T15 11 T50 3 T16 5
values[56] 1229 1 T15 12 T50 3 T16 2
values[57] 1218 1 T15 11 T50 3 T16 3
values[58] 1176 1 T15 11 T50 3 T16 5
values[59] 1208 1 T15 11 T50 3 T16 5
values[60] 1198 1 T15 12 T50 3 T16 3
values[61] 1284 1 T15 11 T50 4 T16 2
values[62] 2110 1 T15 11 T50 3 T16 3
values[63] 6573 1 T15 38 T50 3 T16 56
values[64] 110082 1 T15 2058 T50 567 T16 182

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