Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1518989	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

241921

1

T1

251

T2

12

T3

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	597539	1			T1	648		T2	37		T3	52
values[0x0]	565155	1			T1	583		T2	23		T3	51
values[0x1]	598216	1			T1	654		T2	40		T3	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1173667	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

587243

1

T1

660

T2

33

T3

50

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27206	1			T1	18		T3	1		T7	1
valid_sources[0x01]	27977	1			T1	32		T3	3		T7	1
valid_sources[0x02]	27889	1			T1	26		T3	2		T7	1
valid_sources[0x03]	27450	1			T1	38		T7	4		T8	40
valid_sources[0x04]	28257	1			T1	50		T3	9		T7	3
valid_sources[0x05]	26861	1			T1	36		T3	1		T8	20
valid_sources[0x06]	28127	1			T1	26		T3	3		T7	1
valid_sources[0x07]	27567	1			T1	15		T3	6		T7	4
valid_sources[0x08]	27610	1			T1	42		T3	2		T7	3
valid_sources[0x09]	27151	1			T1	41		T7	3		T8	24
valid_sources[0x0a]	27379	1			T1	32		T3	1		T7	2
valid_sources[0x0b]	27713	1			T1	39		T7	2		T8	54
valid_sources[0x0c]	27606	1			T1	20		T8	6		T9	6
valid_sources[0x0d]	28294	1			T1	24		T7	3		T8	26
valid_sources[0x0e]	28153	1			T1	23		T3	3		T7	1
valid_sources[0x0f]	29103	1			T1	15		T2	2		T7	1
valid_sources[0x10]	27186	1			T1	34		T3	1		T7	6
valid_sources[0x11]	26900	1			T1	28		T8	30		T11	2
valid_sources[0x12]	27735	1			T1	33		T3	4		T7	1
valid_sources[0x13]	28293	1			T1	39		T3	2		T7	2
valid_sources[0x14]	27734	1			T1	33		T3	3		T7	5
valid_sources[0x15]	28559	1			T1	18		T3	6		T7	2
valid_sources[0x16]	28030	1			T1	39		T8	17		T9	4
valid_sources[0x17]	27298	1			T1	44		T2	4		T3	2
valid_sources[0x18]	27529	1			T1	17		T7	2		T8	33
valid_sources[0x19]	27371	1			T1	29		T3	1		T7	1
valid_sources[0x1a]	27538	1			T1	24		T3	11		T7	1
valid_sources[0x1b]	27583	1			T1	33		T7	3		T8	30
valid_sources[0x1c]	26959	1			T1	15		T3	6		T7	1
valid_sources[0x1d]	28528	1			T1	17		T2	7		T3	4
valid_sources[0x1e]	25655	1			T1	41		T3	3		T7	2
valid_sources[0x1f]	27547	1			T1	16		T3	3		T7	1
valid_sources[0x20]	27484	1			T1	15		T3	10		T7	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25417

1

T1

23

T2

1

T3

1

values[0x0]

all_enables

biggest_size

191084

1

T1

197

T2

7

T3

16

values[0x1]

all_enables

biggest_size

25420

1

T1

31

T2

4

T3

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1533072	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

249816

1

T1

281

T2

14

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	611272	1			T1	641		T2	44		T3	48
values[0x0]	561998	1			T1	664		T2	35		T3	55
values[0x1]	609618	1			T1	644		T2	38		T3	64

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1175713	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

607175

1

T1

672

T2

37

T3

54

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27659	1			T2	2		T3	4		T7	2
valid_sources[0x01]	27691	1			T1	30		T2	1		T3	5
valid_sources[0x02]	28155	1			T1	22		T2	1		T3	3
valid_sources[0x03]	27340	1			T1	23		T2	5		T3	2
valid_sources[0x04]	27897	1			T1	46		T2	3		T3	2
valid_sources[0x05]	27897	1			T1	47		T2	2		T7	3
valid_sources[0x06]	27771	1			T2	1		T3	1		T7	1
valid_sources[0x07]	27197	1			T2	2		T3	7		T7	2
valid_sources[0x08]	27788	1			T1	7		T2	3		T3	3
valid_sources[0x09]	28005	1			T1	22		T2	2		T3	3
valid_sources[0x0a]	28196	1			T1	118		T2	1		T3	2
valid_sources[0x0b]	27711	1			T1	41		T2	2		T3	1
valid_sources[0x0c]	27996	1			T1	9		T2	2		T3	2
valid_sources[0x0d]	28377	1			T1	8		T2	2		T3	6
valid_sources[0x0e]	27384	1			T1	9		T2	2		T3	1
valid_sources[0x0f]	27439	1			T1	11		T2	1		T7	3
valid_sources[0x10]	28079	1			T1	34		T2	1		T3	2
valid_sources[0x11]	27366	1			T1	2		T2	3		T3	3
valid_sources[0x12]	27742	1			T1	49		T2	3		T3	1
valid_sources[0x13]	27872	1			T1	66		T3	3		T8	64
valid_sources[0x14]	27813	1			T3	2		T7	1		T8	46
valid_sources[0x15]	28657	1			T1	41		T8	50		T10	1
valid_sources[0x16]	28091	1			T1	23		T7	3		T8	18
valid_sources[0x17]	27710	1			T1	38		T2	2		T3	6
valid_sources[0x18]	26713	1			T2	1		T3	2		T7	5
valid_sources[0x19]	28106	1			T1	19		T2	1		T7	3
valid_sources[0x1a]	27842	1			T3	2		T8	35		T13	3
valid_sources[0x1b]	27951	1			T1	20		T3	3		T7	3
valid_sources[0x1c]	26942	1			T1	4		T2	4		T3	2
valid_sources[0x1d]	28337	1			T1	20		T3	2		T7	3
valid_sources[0x1e]	27157	1			T2	2		T3	4		T7	2
valid_sources[0x1f]	27524	1			T1	56		T3	1		T7	3
valid_sources[0x20]	28411	1			T1	15		T3	3		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26265

1

T1

29

T2

2

T3

4

values[0x0]

all_enables

biggest_size

197049

1

T1

228

T2

10

T3

22

values[0x1]

all_enables

biggest_size

26502

1

T1

24

T2

2

T7

6

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1524095	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

242452

1

T1

287

T2

12

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	599194	1			T1	648		T2	55		T3	50
values[0x0]	566468	1			T1	592		T2	38		T3	38
values[0x1]	600885	1			T1	617		T2	47		T3	52

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1177725	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

588822

1

T1

672

T2

39

T3

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26878	1			T1	34		T2	1		T7	2
valid_sources[0x01]	27489	1			T1	38		T2	3		T7	1
valid_sources[0x02]	27720	1			T1	22		T2	1		T7	1
valid_sources[0x03]	27193	1			T1	31		T2	4		T7	2
valid_sources[0x04]	28349	1			T1	26		T2	2		T7	1
valid_sources[0x05]	26903	1			T1	43		T2	2		T3	5
valid_sources[0x06]	27627	1			T1	23		T2	1		T7	1
valid_sources[0x07]	27805	1			T1	25		T7	1		T8	41
valid_sources[0x08]	27641	1			T1	55		T7	2		T8	22
valid_sources[0x09]	27574	1			T1	29		T2	3		T7	5
valid_sources[0x0a]	28094	1			T1	29		T2	5		T7	2
valid_sources[0x0b]	27194	1			T1	27		T3	4		T7	2
valid_sources[0x0c]	27446	1			T1	37		T8	28		T23	2
valid_sources[0x0d]	28221	1			T1	25		T2	1		T3	6
valid_sources[0x0e]	27473	1			T1	22		T2	1		T8	68
valid_sources[0x0f]	27592	1			T1	33		T2	3		T7	1
valid_sources[0x10]	28117	1			T1	28		T2	1		T3	10
valid_sources[0x11]	27516	1			T1	21		T2	1		T8	28
valid_sources[0x12]	26587	1			T1	22		T2	2		T3	2
valid_sources[0x13]	27189	1			T1	19		T2	6		T7	1
valid_sources[0x14]	27081	1			T1	22		T2	1		T8	14
valid_sources[0x15]	27790	1			T1	32		T2	2		T8	22
valid_sources[0x16]	27784	1			T1	37		T2	1		T3	24
valid_sources[0x17]	27345	1			T1	20		T2	6		T3	12
valid_sources[0x18]	26845	1			T1	25		T7	1		T8	41
valid_sources[0x19]	27266	1			T1	36		T2	7		T3	2
valid_sources[0x1a]	27305	1			T1	22		T2	4		T3	1
valid_sources[0x1b]	27863	1			T1	30		T2	2		T3	6
valid_sources[0x1c]	26661	1			T1	30		T2	1		T7	2
valid_sources[0x1d]	27786	1			T1	36		T2	2		T7	2
valid_sources[0x1e]	27258	1			T1	40		T7	5		T8	80
valid_sources[0x1f]	27638	1			T1	30		T2	1		T8	1
valid_sources[0x20]	27726	1			T1	24		T2	1		T3	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25665

1

T1

32

T2

2

T7

1

values[0x0]

all_enables

biggest_size

191301

1

T1

221

T2

9

T3

9

values[0x1]

all_enables

biggest_size

25486

1

T1

34

T2

1

T3

2