Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7751785	0	0
GntImpliesValid_A	2147483647	7751785	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7751785	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	418257029	0	0
ReadyAndValidImplyGrant_A	2147483647	7751785	0	0
ReqAndReadyImplyGrant_A	2147483647	7751785	0	0
ReqImpliesValid_A	2147483647	32797334	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	48526	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7751785	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1176792	1174632	0	0
T2	214296	213504	0	0
T3	52944	52056	0	0
T7	1591008	1589760	0	0
T8	290424	289008	0	0
T9	54264	53040	0	0
T10	11831568	11830320	0	0
T11	110856	109416	0	0
T12	7173024	7172064	0	0
T13	162456	161280	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7751785	0	0
T1	1176792	2953	0	0
T2	214296	357	0	0
T3	52944	463	0	0
T7	1591008	6093	0	0
T8	290424	6610	0	0
T9	54264	481	0	0
T10	11831568	467	0	0
T11	110856	1706	0	0
T12	7173024	416	0	0
T13	162456	3654	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7751785	0	0
T1	1176792	2953	0	0
T2	214296	357	0	0
T3	52944	463	0	0
T7	1591008	6093	0	0
T8	290424	6610	0	0
T9	54264	481	0	0
T10	11831568	467	0	0
T11	110856	1706	0	0
T12	7173024	416	0	0
T13	162456	3654	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1176792	1174632	0	0
T2	214296	213504	0	0
T3	52944	52056	0	0
T7	1591008	1589760	0	0
T8	290424	289008	0	0
T9	54264	53040	0	0
T10	11831568	11830320	0	0
T11	110856	109416	0	0
T12	7173024	7172064	0	0
T13	162456	161280	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1176792	1174632	0	0
T2	214296	213504	0	0
T3	52944	52056	0	0
T7	1591008	1589760	0	0
T8	290424	289008	0	0
T9	54264	53040	0	0
T10	11831568	11830320	0	0
T11	110856	109416	0	0
T12	7173024	7172064	0	0
T13	162456	161280	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7751785	0	0
T1	1176792	2953	0	0
T2	214296	357	0	0
T3	52944	463	0	0
T7	1591008	6093	0	0
T8	290424	6610	0	0
T9	54264	481	0	0
T10	11831568	467	0	0
T11	110856	1706	0	0
T12	7173024	416	0	0
T13	162456	3654	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	418257029	0	0
T1	1176792	67633	0	0
T2	214296	10363	0	0
T3	52944	605	0	0
T7	1591008	98513	0	0
T8	290424	8615	0	0
T9	54264	632	0	0
T10	11831568	602583	0	0
T11	110856	2186	0	0
T12	7173024	250670	0	0
T13	162456	3061	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7751785	0	0
T1	1176792	2953	0	0
T2	214296	357	0	0
T3	52944	463	0	0
T7	1591008	6093	0	0
T8	290424	6610	0	0
T9	54264	481	0	0
T10	11831568	467	0	0
T11	110856	1706	0	0
T12	7173024	416	0	0
T13	162456	3654	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7751785	0	0
T1	1176792	2953	0	0
T2	214296	357	0	0
T3	52944	463	0	0
T7	1591008	6093	0	0
T8	290424	6610	0	0
T9	54264	481	0	0
T10	11831568	467	0	0
T11	110856	1706	0	0
T12	7173024	416	0	0
T13	162456	3654	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32797334	0	0
T1	1176792	7069	0	0
T2	214296	724	0	0
T3	52944	552	0	0
T7	1591008	14318	0	0
T8	290424	7723	0	0
T9	54264	547	0	0
T10	11831568	29040	0	0
T11	110856	1886	0	0
T12	7173024	669	0	0
T13	162456	4377	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48526	0	21600
T8	24202	29	0	2
T9	4522	0	0	2
T10	985964	0	0	2
T11	9238	2	0	2
T12	597752	0	0	2
T13	13538	1	0	2
T14	12106	8	0	2
T15	0	32	0	0
T16	0	68	0	0
T17	0	30	0	0
T18	0	4	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	37	0	0
T22	0	2	0	0
T23	19986	0	0	2
T24	64972	0	0	2
T25	30452	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1176792	1174632	0	0
T2	214296	213504	0	0
T3	52944	52056	0	0
T7	1591008	1589760	0	0
T8	290424	289008	0	0
T9	54264	53040	0	0
T10	11831568	11830320	0	0
T11	110856	109416	0	0
T12	7173024	7172064	0	0
T13	162456	161280	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7751785	0	0
T1	1176792	2953	0	0
T2	214296	357	0	0
T3	52944	463	0	0
T7	1591008	6093	0	0
T8	290424	6610	0	0
T9	54264	481	0	0
T10	11831568	467	0	0
T11	110856	1706	0	0
T12	7173024	416	0	0
T13	162456	3654	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	859732	0	0
GntImpliesValid_A	380337288	859732	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	859732	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	11528866	0	0
ReadyAndValidImplyGrant_A	380337288	859732	0	0
ReqAndReadyImplyGrant_A	380337288	859732	0	0
ReqImpliesValid_A	380337288	2331733	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	859732	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	859732	0	0
T1	49033	312	0	0
T2	8929	36	0	0
T3	2206	43	0	0
T7	66292	663	0	0
T8	12101	741	0	0
T9	2261	59	0	0
T10	492982	58	0	0
T11	4619	203	0	0
T12	298876	37	0	0
T13	6769	882	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	859732	0	0
T1	49033	312	0	0
T2	8929	36	0	0
T3	2206	43	0	0
T7	66292	663	0	0
T8	12101	741	0	0
T9	2261	59	0	0
T10	492982	58	0	0
T11	4619	203	0	0
T12	298876	37	0	0
T13	6769	882	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	859732	0	0
T1	49033	312	0	0
T2	8929	36	0	0
T3	2206	43	0	0
T7	66292	663	0	0
T8	12101	741	0	0
T9	2261	59	0	0
T10	492982	58	0	0
T11	4619	203	0	0
T12	298876	37	0	0
T13	6769	882	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	11528866	0	0
T1	49033	1983	0	0
T2	8929	234	0	0
T3	2206	35	0	0
T7	66292	4861	0	0
T8	12101	561	0	0
T9	2261	41	0	0
T10	492982	17734	0	0
T11	4619	169	0	0
T12	298876	141	0	0
T13	6769	450	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	859732	0	0
T1	49033	312	0	0
T2	8929	36	0	0
T3	2206	43	0	0
T7	66292	663	0	0
T8	12101	741	0	0
T9	2261	59	0	0
T10	492982	58	0	0
T11	4619	203	0	0
T12	298876	37	0	0
T13	6769	882	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	859732	0	0
T1	49033	312	0	0
T2	8929	36	0	0
T3	2206	43	0	0
T7	66292	663	0	0
T8	12101	741	0	0
T9	2261	59	0	0
T10	492982	58	0	0
T11	4619	203	0	0
T12	298876	37	0	0
T13	6769	882	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	2331733	0	0
T1	49033	448	0	0
T2	8929	43	0	0
T3	2206	52	0	0
T7	66292	1163	0	0
T8	12101	922	0	0
T9	2261	78	0	0
T10	492982	982	0	0
T11	4619	238	0	0
T12	298876	46	0	0
T13	6769	1316	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	859732	0	0
T1	49033	312	0	0
T2	8929	36	0	0
T3	2206	43	0	0
T7	66292	663	0	0
T8	12101	741	0	0
T9	2261	59	0	0
T10	492982	58	0	0
T11	4619	203	0	0
T12	298876	37	0	0
T13	6769	882	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	863205	0	0
GntImpliesValid_A	380337288	863205	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	863205	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	11619829	0	0
ReadyAndValidImplyGrant_A	380337288	863205	0	0
ReqAndReadyImplyGrant_A	380337288	863205	0	0
ReqImpliesValid_A	380337288	2355473	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	863205	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	863205	0	0
T1	49033	325	0	0
T2	8929	48	0	0
T3	2206	55	0	0
T7	66292	652	0	0
T8	12101	733	0	0
T9	2261	46	0	0
T10	492982	45	0	0
T11	4619	172	0	0
T12	298876	47	0	0
T13	6769	299	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	863205	0	0
T1	49033	325	0	0
T2	8929	48	0	0
T3	2206	55	0	0
T7	66292	652	0	0
T8	12101	733	0	0
T9	2261	46	0	0
T10	492982	45	0	0
T11	4619	172	0	0
T12	298876	47	0	0
T13	6769	299	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	863205	0	0
T1	49033	325	0	0
T2	8929	48	0	0
T3	2206	55	0	0
T7	66292	652	0	0
T8	12101	733	0	0
T9	2261	46	0	0
T10	492982	45	0	0
T11	4619	172	0	0
T12	298876	47	0	0
T13	6769	299	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	11619829	0	0
T1	49033	2421	0	0
T2	8929	341	0	0
T3	2206	45	0	0
T7	66292	4860	0	0
T8	12101	564	0	0
T9	2261	42	0	0
T10	492982	13708	0	0
T11	4619	145	0	0
T12	298876	174	0	0
T13	6769	259	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	863205	0	0
T1	49033	325	0	0
T2	8929	48	0	0
T3	2206	55	0	0
T7	66292	652	0	0
T8	12101	733	0	0
T9	2261	46	0	0
T10	492982	45	0	0
T11	4619	172	0	0
T12	298876	47	0	0
T13	6769	299	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	863205	0	0
T1	49033	325	0	0
T2	8929	48	0	0
T3	2206	55	0	0
T7	66292	652	0	0
T8	12101	733	0	0
T9	2261	46	0	0
T10	492982	45	0	0
T11	4619	172	0	0
T12	298876	47	0	0
T13	6769	299	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	2355473	0	0
T1	49033	527	0	0
T2	8929	92	0	0
T3	2206	66	0	0
T7	66292	1139	0	0
T8	12101	903	0	0
T9	2261	51	0	0
T10	492982	1816	0	0
T11	4619	200	0	0
T12	298876	73	0	0
T13	6769	341	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	863205	0	0
T1	49033	325	0	0
T2	8929	48	0	0
T3	2206	55	0	0
T7	66292	652	0	0
T8	12101	733	0	0
T9	2261	46	0	0
T10	492982	45	0	0
T11	4619	172	0	0
T12	298876	47	0	0
T13	6769	299	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	216522	0	0
GntImpliesValid_A	380337288	216522	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	216522	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	2789320	0	0
ReadyAndValidImplyGrant_A	380337288	216522	0	0
ReqAndReadyImplyGrant_A	380337288	216522	0	0
ReqImpliesValid_A	380337288	542107	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	216522	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	216522	0	0
T1	49033	77	0	0
T2	8929	7	0	0
T3	2206	11	0	0
T7	66292	193	0	0
T8	12101	172	0	0
T9	2261	12	0	0
T10	492982	13	0	0
T11	4619	59	0	0
T12	298876	15	0	0
T13	6769	43	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	216522	0	0
T1	49033	77	0	0
T2	8929	7	0	0
T3	2206	11	0	0
T7	66292	193	0	0
T8	12101	172	0	0
T9	2261	12	0	0
T10	492982	13	0	0
T11	4619	59	0	0
T12	298876	15	0	0
T13	6769	43	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	216522	0	0
T1	49033	77	0	0
T2	8929	7	0	0
T3	2206	11	0	0
T7	66292	193	0	0
T8	12101	172	0	0
T9	2261	12	0	0
T10	492982	13	0	0
T11	4619	59	0	0
T12	298876	15	0	0
T13	6769	43	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	2789320	0	0
T1	49033	560	0	0
T2	8929	52	0	0
T3	2206	12	0	0
T7	66292	1381	0	0
T8	12101	163	0	0
T9	2261	13	0	0
T10	492982	4392	0	0
T11	4619	58	0	0
T12	298876	50	0	0
T13	6769	43	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	216522	0	0
T1	49033	77	0	0
T2	8929	7	0	0
T3	2206	11	0	0
T7	66292	193	0	0
T8	12101	172	0	0
T9	2261	12	0	0
T10	492982	13	0	0
T11	4619	59	0	0
T12	298876	15	0	0
T13	6769	43	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	216522	0	0
T1	49033	77	0	0
T2	8929	7	0	0
T3	2206	11	0	0
T7	66292	193	0	0
T8	12101	172	0	0
T9	2261	12	0	0
T10	492982	13	0	0
T11	4619	59	0	0
T12	298876	15	0	0
T13	6769	43	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	542107	0	0
T1	49033	94	0	0
T2	8929	7	0	0
T3	2206	11	0	0
T7	66292	320	0	0
T8	12101	182	0	0
T9	2261	12	0	0
T10	492982	13	0	0
T11	4619	61	0	0
T12	298876	31	0	0
T13	6769	45	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	216522	0	0
T1	49033	77	0	0
T2	8929	7	0	0
T3	2206	11	0	0
T7	66292	193	0	0
T8	12101	172	0	0
T9	2261	12	0	0
T10	492982	13	0	0
T11	4619	59	0	0
T12	298876	15	0	0
T13	6769	43	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	213924	0	0
GntImpliesValid_A	380337288	213924	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	213924	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	2819975	0	0
ReadyAndValidImplyGrant_A	380337288	213924	0	0
ReqAndReadyImplyGrant_A	380337288	213924	0	0
ReqImpliesValid_A	380337288	529910	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	213924	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	213924	0	0
T1	49033	95	0	0
T2	8929	14	0	0
T3	2206	14	0	0
T7	66292	176	0	0
T8	12101	184	0	0
T9	2261	18	0	0
T10	492982	14	0	0
T11	4619	45	0	0
T12	298876	10	0	0
T13	6769	43	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	213924	0	0
T1	49033	95	0	0
T2	8929	14	0	0
T3	2206	14	0	0
T7	66292	176	0	0
T8	12101	184	0	0
T9	2261	18	0	0
T10	492982	14	0	0
T11	4619	45	0	0
T12	298876	10	0	0
T13	6769	43	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	213924	0	0
T1	49033	95	0	0
T2	8929	14	0	0
T3	2206	14	0	0
T7	66292	176	0	0
T8	12101	184	0	0
T9	2261	18	0	0
T10	492982	14	0	0
T11	4619	45	0	0
T12	298876	10	0	0
T13	6769	43	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	2819975	0	0
T1	49033	667	0	0
T2	8929	112	0	0
T3	2206	15	0	0
T7	66292	1409	0	0
T8	12101	174	0	0
T9	2261	19	0	0
T10	492982	4900	0	0
T11	4619	43	0	0
T12	298876	61	0	0
T13	6769	44	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	213924	0	0
T1	49033	95	0	0
T2	8929	14	0	0
T3	2206	14	0	0
T7	66292	176	0	0
T8	12101	184	0	0
T9	2261	18	0	0
T10	492982	14	0	0
T11	4619	45	0	0
T12	298876	10	0	0
T13	6769	43	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	213924	0	0
T1	49033	95	0	0
T2	8929	14	0	0
T3	2206	14	0	0
T7	66292	176	0	0
T8	12101	184	0	0
T9	2261	18	0	0
T10	492982	14	0	0
T11	4619	45	0	0
T12	298876	10	0	0
T13	6769	43	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	529910	0	0
T1	49033	158	0	0
T2	8929	14	0	0
T3	2206	14	0	0
T7	66292	267	0	0
T8	12101	195	0	0
T9	2261	18	0	0
T10	492982	14	0	0
T11	4619	48	0	0
T12	298876	10	0	0
T13	6769	44	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	213924	0	0
T1	49033	95	0	0
T2	8929	14	0	0
T3	2206	14	0	0
T7	66292	176	0	0
T8	12101	184	0	0
T9	2261	18	0	0
T10	492982	14	0	0
T11	4619	45	0	0
T12	298876	10	0	0
T13	6769	43	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	216418	0	0
GntImpliesValid_A	380337288	216418	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	216418	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	5196894	0	0
ReadyAndValidImplyGrant_A	380337288	216418	0	0
ReqAndReadyImplyGrant_A	380337288	216418	0	0
ReqImpliesValid_A	380337288	1172707	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	216418	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	216418	0	0
T1	49033	87	0	0
T2	8929	14	0	0
T3	2206	15	0	0
T7	66292	176	0	0
T8	12101	156	0	0
T9	2261	17	0	0
T10	492982	19	0	0
T11	4619	47	0	0
T12	298876	13	0	0
T13	6769	41	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	216418	0	0
T1	49033	87	0	0
T2	8929	14	0	0
T3	2206	15	0	0
T7	66292	176	0	0
T8	12101	156	0	0
T9	2261	17	0	0
T10	492982	19	0	0
T11	4619	47	0	0
T12	298876	13	0	0
T13	6769	41	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	216418	0	0
T1	49033	87	0	0
T2	8929	14	0	0
T3	2206	15	0	0
T7	66292	176	0	0
T8	12101	156	0	0
T9	2261	17	0	0
T10	492982	19	0	0
T11	4619	47	0	0
T12	298876	13	0	0
T13	6769	41	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	5196894	0	0
T1	49033	1112	0	0
T2	8929	193	0	0
T3	2206	72	0	0
T7	66292	1961	0	0
T8	12101	1549	0	0
T9	2261	94	0	0
T10	492982	5639	0	0
T11	4619	307	0	0
T12	298876	81	0	0
T13	6769	197	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	216418	0	0
T1	49033	87	0	0
T2	8929	14	0	0
T3	2206	15	0	0
T7	66292	176	0	0
T8	12101	156	0	0
T9	2261	17	0	0
T10	492982	19	0	0
T11	4619	47	0	0
T12	298876	13	0	0
T13	6769	41	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	216418	0	0
T1	49033	87	0	0
T2	8929	14	0	0
T3	2206	15	0	0
T7	66292	176	0	0
T8	12101	156	0	0
T9	2261	17	0	0
T10	492982	19	0	0
T11	4619	47	0	0
T12	298876	13	0	0
T13	6769	41	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	1172707	0	0
T1	49033	132	0	0
T2	8929	14	0	0
T3	2206	19	0	0
T7	66292	331	0	0
T8	12101	335	0	0
T9	2261	17	0	0
T10	492982	733	0	0
T11	4619	75	0	0
T12	298876	31	0	0
T13	6769	53	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	216418	0	0
T1	49033	87	0	0
T2	8929	14	0	0
T3	2206	15	0	0
T7	66292	176	0	0
T8	12101	156	0	0
T9	2261	17	0	0
T10	492982	19	0	0
T11	4619	47	0	0
T12	298876	13	0	0
T13	6769	41	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	215442	0	0
GntImpliesValid_A	380337288	215442	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	215442	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	4533902	0	0
ReadyAndValidImplyGrant_A	380337288	215442	0	0
ReqAndReadyImplyGrant_A	380337288	215442	0	0
ReqImpliesValid_A	380337288	1056072	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	215442	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	215442	0	0
T1	49033	68	0	0
T2	8929	7	0	0
T3	2206	10	0	0
T7	66292	165	0	0
T8	12101	170	0	0
T9	2261	9	0	0
T10	492982	14	0	0
T11	4619	46	0	0
T12	298876	18	0	0
T13	6769	44	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	215442	0	0
T1	49033	68	0	0
T2	8929	7	0	0
T3	2206	10	0	0
T7	66292	165	0	0
T8	12101	170	0	0
T9	2261	9	0	0
T10	492982	14	0	0
T11	4619	46	0	0
T12	298876	18	0	0
T13	6769	44	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	215442	0	0
T1	49033	68	0	0
T2	8929	7	0	0
T3	2206	10	0	0
T7	66292	165	0	0
T8	12101	170	0	0
T9	2261	9	0	0
T10	492982	14	0	0
T11	4619	46	0	0
T12	298876	18	0	0
T13	6769	44	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	4533902	0	0
T1	49033	1111	0	0
T2	8929	44	0	0
T3	2206	75	0	0
T7	66292	2426	0	0
T8	12101	1149	0	0
T9	2261	50	0	0
T10	492982	4344	0	0
T11	4619	263	0	0
T12	298876	126	0	0
T13	6769	175	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	215442	0	0
T1	49033	68	0	0
T2	8929	7	0	0
T3	2206	10	0	0
T7	66292	165	0	0
T8	12101	170	0	0
T9	2261	9	0	0
T10	492982	14	0	0
T11	4619	46	0	0
T12	298876	18	0	0
T13	6769	44	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	215442	0	0
T1	49033	68	0	0
T2	8929	7	0	0
T3	2206	10	0	0
T7	66292	165	0	0
T8	12101	170	0	0
T9	2261	9	0	0
T10	492982	14	0	0
T11	4619	46	0	0
T12	298876	18	0	0
T13	6769	44	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	1056072	0	0
T1	49033	119	0	0
T2	8929	7	0	0
T3	2206	27	0	0
T7	66292	355	0	0
T8	12101	300	0	0
T9	2261	9	0	0
T10	492982	38	0	0
T11	4619	71	0	0
T12	298876	26	0	0
T13	6769	50	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	215442	0	0
T1	49033	68	0	0
T2	8929	7	0	0
T3	2206	10	0	0
T7	66292	165	0	0
T8	12101	170	0	0
T9	2261	9	0	0
T10	492982	14	0	0
T11	4619	46	0	0
T12	298876	18	0	0
T13	6769	44	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	208672	0	0
GntImpliesValid_A	380337288	208672	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	208672	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	4727420	0	0
ReadyAndValidImplyGrant_A	380337288	208672	0	0
ReqAndReadyImplyGrant_A	380337288	208672	0	0
ReqImpliesValid_A	380337288	1155832	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	208672	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	208672	0	0
T1	49033	77	0	0
T2	8929	11	0	0
T3	2206	8	0	0
T7	66292	160	0	0
T8	12101	191	0	0
T9	2261	19	0	0
T10	492982	8	0	0
T11	4619	42	0	0
T12	298876	11	0	0
T13	6769	48	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	208672	0	0
T1	49033	77	0	0
T2	8929	11	0	0
T3	2206	8	0	0
T7	66292	160	0	0
T8	12101	191	0	0
T9	2261	19	0	0
T10	492982	8	0	0
T11	4619	42	0	0
T12	298876	11	0	0
T13	6769	48	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	208672	0	0
T1	49033	77	0	0
T2	8929	11	0	0
T3	2206	8	0	0
T7	66292	160	0	0
T8	12101	191	0	0
T9	2261	19	0	0
T10	492982	8	0	0
T11	4619	42	0	0
T12	298876	11	0	0
T13	6769	48	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	4727420	0	0
T1	49033	2097	0	0
T2	8929	120	0	0
T3	2206	37	0	0
T7	66292	2737	0	0
T8	12101	1047	0	0
T9	2261	99	0	0
T10	492982	1261	0	0
T11	4619	231	0	0
T12	298876	136	0	0
T13	6769	212	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	208672	0	0
T1	49033	77	0	0
T2	8929	11	0	0
T3	2206	8	0	0
T7	66292	160	0	0
T8	12101	191	0	0
T9	2261	19	0	0
T10	492982	8	0	0
T11	4619	42	0	0
T12	298876	11	0	0
T13	6769	48	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	208672	0	0
T1	49033	77	0	0
T2	8929	11	0	0
T3	2206	8	0	0
T7	66292	160	0	0
T8	12101	191	0	0
T9	2261	19	0	0
T10	492982	8	0	0
T11	4619	42	0	0
T12	298876	11	0	0
T13	6769	48	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	1155832	0	0
T1	49033	400	0	0
T2	8929	11	0	0
T3	2206	13	0	0
T7	66292	494	0	0
T8	12101	342	0	0
T9	2261	45	0	0
T10	492982	8	0	0
T11	4619	60	0	0
T12	298876	59	0	0
T13	6769	61	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	208672	0	0
T1	49033	77	0	0
T2	8929	11	0	0
T3	2206	8	0	0
T7	66292	160	0	0
T8	12101	191	0	0
T9	2261	19	0	0
T10	492982	8	0	0
T11	4619	42	0	0
T12	298876	11	0	0
T13	6769	48	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	199097	0	0
GntImpliesValid_A	380337288	199097	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	199097	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	4978745	0	0
ReadyAndValidImplyGrant_A	380337288	199097	0	0
ReqAndReadyImplyGrant_A	380337288	199097	0	0
ReqImpliesValid_A	380337288	1039308	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	199097	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	199097	0	0
T1	49033	77	0	0
T2	8929	11	0	0
T3	2206	19	0	0
T7	66292	170	0	0
T8	12101	190	0	0
T9	2261	14	0	0
T10	492982	7	0	0
T11	4619	41	0	0
T12	298876	6	0	0
T13	6769	50	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	199097	0	0
T1	49033	77	0	0
T2	8929	11	0	0
T3	2206	19	0	0
T7	66292	170	0	0
T8	12101	190	0	0
T9	2261	14	0	0
T10	492982	7	0	0
T11	4619	41	0	0
T12	298876	6	0	0
T13	6769	50	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	199097	0	0
T1	49033	77	0	0
T2	8929	11	0	0
T3	2206	19	0	0
T7	66292	170	0	0
T8	12101	190	0	0
T9	2261	14	0	0
T10	492982	7	0	0
T11	4619	41	0	0
T12	298876	6	0	0
T13	6769	50	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	4978745	0	0
T1	49033	4242	0	0
T2	8929	152	0	0
T3	2206	131	0	0
T7	66292	3952	0	0
T8	12101	1003	0	0
T9	2261	82	0	0
T10	492982	2361	0	0
T11	4619	271	0	0
T12	298876	126	0	0
T13	6769	234	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	199097	0	0
T1	49033	77	0	0
T2	8929	11	0	0
T3	2206	19	0	0
T7	66292	170	0	0
T8	12101	190	0	0
T9	2261	14	0	0
T10	492982	7	0	0
T11	4619	41	0	0
T12	298876	6	0	0
T13	6769	50	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	199097	0	0
T1	49033	77	0	0
T2	8929	11	0	0
T3	2206	19	0	0
T7	66292	170	0	0
T8	12101	190	0	0
T9	2261	14	0	0
T10	492982	7	0	0
T11	4619	41	0	0
T12	298876	6	0	0
T13	6769	50	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	1039308	0	0
T1	49033	583	0	0
T2	8929	11	0	0
T3	2206	54	0	0
T7	66292	482	0	0
T8	12101	322	0	0
T9	2261	21	0	0
T10	492982	7	0	0
T11	4619	50	0	0
T12	298876	6	0	0
T13	6769	60	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	199097	0	0
T1	49033	77	0	0
T2	8929	11	0	0
T3	2206	19	0	0
T7	66292	170	0	0
T8	12101	190	0	0
T9	2261	14	0	0
T10	492982	7	0	0
T11	4619	41	0	0
T12	298876	6	0	0
T13	6769	50	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T13
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T13

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T13
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	215730	0	0
GntImpliesValid_A	380337288	215730	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	215730	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	2889184	0	0
ReadyAndValidImplyGrant_A	380337288	215730	0	0
ReqAndReadyImplyGrant_A	380337288	215730	0	0
ReqImpliesValid_A	380337288	512295	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	215730	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	215730	0	0
T1	49033	88	0	0
T2	8929	7	0	0
T3	2206	19	0	0
T7	66292	177	0	0
T8	12101	159	0	0
T9	2261	10	0	0
T10	492982	13	0	0
T11	4619	54	0	0
T12	298876	9	0	0
T13	6769	554	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	215730	0	0
T1	49033	88	0	0
T2	8929	7	0	0
T3	2206	19	0	0
T7	66292	177	0	0
T8	12101	159	0	0
T9	2261	10	0	0
T10	492982	13	0	0
T11	4619	54	0	0
T12	298876	9	0	0
T13	6769	554	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	215730	0	0
T1	49033	88	0	0
T2	8929	7	0	0
T3	2206	19	0	0
T7	66292	177	0	0
T8	12101	159	0	0
T9	2261	10	0	0
T10	492982	13	0	0
T11	4619	54	0	0
T12	298876	9	0	0
T13	6769	554	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	2889184	0	0
T1	49033	651	0	0
T2	8929	47	0	0
T3	2206	20	0	0
T7	66292	1301	0	0
T8	12101	150	0	0
T9	2261	11	0	0
T10	492982	4257	0	0
T11	4619	55	0	0
T12	298876	33	0	0
T13	6769	446	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	215730	0	0
T1	49033	88	0	0
T2	8929	7	0	0
T3	2206	19	0	0
T7	66292	177	0	0
T8	12101	159	0	0
T9	2261	10	0	0
T10	492982	13	0	0
T11	4619	54	0	0
T12	298876	9	0	0
T13	6769	554	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	215730	0	0
T1	49033	88	0	0
T2	8929	7	0	0
T3	2206	19	0	0
T7	66292	177	0	0
T8	12101	159	0	0
T9	2261	10	0	0
T10	492982	13	0	0
T11	4619	54	0	0
T12	298876	9	0	0
T13	6769	554	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	512295	0	0
T1	49033	88	0	0
T2	8929	7	0	0
T3	2206	19	0	0
T7	66292	232	0	0
T8	12101	169	0	0
T9	2261	10	0	0
T10	492982	13	0	0
T11	4619	54	0	0
T12	298876	9	0	0
T13	6769	664	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	215730	0	0
T1	49033	88	0	0
T2	8929	7	0	0
T3	2206	19	0	0
T7	66292	177	0	0
T8	12101	159	0	0
T9	2261	10	0	0
T10	492982	13	0	0
T11	4619	54	0	0
T12	298876	9	0	0
T13	6769	554	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	216201	0	0
GntImpliesValid_A	380337288	216201	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	216201	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	2858742	0	0
ReadyAndValidImplyGrant_A	380337288	216201	0	0
ReqAndReadyImplyGrant_A	380337288	216201	0	0
ReqImpliesValid_A	380337288	552770	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	216201	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	216201	0	0
T1	49033	70	0	0
T2	8929	12	0	0
T3	2206	12	0	0
T7	66292	157	0	0
T8	12101	189	0	0
T9	2261	9	0	0
T10	492982	11	0	0
T11	4619	48	0	0
T12	298876	9	0	0
T13	6769	547	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	216201	0	0
T1	49033	70	0	0
T2	8929	12	0	0
T3	2206	12	0	0
T7	66292	157	0	0
T8	12101	189	0	0
T9	2261	9	0	0
T10	492982	11	0	0
T11	4619	48	0	0
T12	298876	9	0	0
T13	6769	547	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	216201	0	0
T1	49033	70	0	0
T2	8929	12	0	0
T3	2206	12	0	0
T7	66292	157	0	0
T8	12101	189	0	0
T9	2261	9	0	0
T10	492982	11	0	0
T11	4619	48	0	0
T12	298876	9	0	0
T13	6769	547	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	2858742	0	0
T1	49033	519	0	0
T2	8929	71	0	0
T3	2206	13	0	0
T7	66292	1084	0	0
T8	12101	181	0	0
T9	2261	10	0	0
T10	492982	4018	0	0
T11	4619	48	0	0
T12	298876	44	0	0
T13	6769	462	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	216201	0	0
T1	49033	70	0	0
T2	8929	12	0	0
T3	2206	12	0	0
T7	66292	157	0	0
T8	12101	189	0	0
T9	2261	9	0	0
T10	492982	11	0	0
T11	4619	48	0	0
T12	298876	9	0	0
T13	6769	547	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	216201	0	0
T1	49033	70	0	0
T2	8929	12	0	0
T3	2206	12	0	0
T7	66292	157	0	0
T8	12101	189	0	0
T9	2261	9	0	0
T10	492982	11	0	0
T11	4619	48	0	0
T12	298876	9	0	0
T13	6769	547	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	552770	0	0
T1	49033	92	0	0
T2	8929	28	0	0
T3	2206	12	0	0
T7	66292	201	0	0
T8	12101	198	0	0
T9	2261	9	0	0
T10	492982	11	0	0
T11	4619	49	0	0
T12	298876	9	0	0
T13	6769	634	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	216201	0	0
T1	49033	70	0	0
T2	8929	12	0	0
T3	2206	12	0	0
T7	66292	157	0	0
T8	12101	189	0	0
T9	2261	9	0	0
T10	492982	11	0	0
T11	4619	48	0	0
T12	298876	9	0	0
T13	6769	547	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	224108	0	0
GntImpliesValid_A	380337288	224108	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	224108	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	2892855	0	0
ReadyAndValidImplyGrant_A	380337288	224108	0	0
ReqAndReadyImplyGrant_A	380337288	224108	0	0
ReqImpliesValid_A	380337288	575616	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	224108	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	224108	0	0
T1	49033	75	0	0
T2	8929	13	0	0
T3	2206	11	0	0
T7	66292	164	0	0
T8	12101	187	0	0
T9	2261	6	0	0
T10	492982	13	0	0
T11	4619	51	0	0
T12	298876	18	0	0
T13	6769	39	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	224108	0	0
T1	49033	75	0	0
T2	8929	13	0	0
T3	2206	11	0	0
T7	66292	164	0	0
T8	12101	187	0	0
T9	2261	6	0	0
T10	492982	13	0	0
T11	4619	51	0	0
T12	298876	18	0	0
T13	6769	39	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	224108	0	0
T1	49033	75	0	0
T2	8929	13	0	0
T3	2206	11	0	0
T7	66292	164	0	0
T8	12101	187	0	0
T9	2261	6	0	0
T10	492982	13	0	0
T11	4619	51	0	0
T12	298876	18	0	0
T13	6769	39	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	2892855	0	0
T1	49033	539	0	0
T2	8929	109	0	0
T3	2206	12	0	0
T7	66292	1217	0	0
T8	12101	179	0	0
T9	2261	7	0	0
T10	492982	6404	0	0
T11	4619	51	0	0
T12	298876	93	0	0
T13	6769	41	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	224108	0	0
T1	49033	75	0	0
T2	8929	13	0	0
T3	2206	11	0	0
T7	66292	164	0	0
T8	12101	187	0	0
T9	2261	6	0	0
T10	492982	13	0	0
T11	4619	51	0	0
T12	298876	18	0	0
T13	6769	39	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	224108	0	0
T1	49033	75	0	0
T2	8929	13	0	0
T3	2206	11	0	0
T7	66292	164	0	0
T8	12101	187	0	0
T9	2261	6	0	0
T10	492982	13	0	0
T11	4619	51	0	0
T12	298876	18	0	0
T13	6769	39	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	575616	0	0
T1	49033	81	0	0
T2	8929	18	0	0
T3	2206	11	0	0
T7	66292	249	0	0
T8	12101	196	0	0
T9	2261	6	0	0
T10	492982	430	0	0
T11	4619	52	0	0
T12	298876	18	0	0
T13	6769	39	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	224108	0	0
T1	49033	75	0	0
T2	8929	13	0	0
T3	2206	11	0	0
T7	66292	164	0	0
T8	12101	187	0	0
T9	2261	6	0	0
T10	492982	13	0	0
T11	4619	51	0	0
T12	298876	18	0	0
T13	6769	39	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	202773	0	0
GntImpliesValid_A	380337288	202773	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	202773	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	2848934	0	0
ReadyAndValidImplyGrant_A	380337288	202773	0	0
ReqAndReadyImplyGrant_A	380337288	202773	0	0
ReqImpliesValid_A	380337288	477686	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	202773	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	202773	0	0
T1	49033	72	0	0
T2	8929	11	0	0
T3	2206	11	0	0
T7	66292	167	0	0
T8	12101	195	0	0
T9	2261	19	0	0
T10	492982	13	0	0
T11	4619	49	0	0
T12	298876	13	0	0
T13	6769	43	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	202773	0	0
T1	49033	72	0	0
T2	8929	11	0	0
T3	2206	11	0	0
T7	66292	167	0	0
T8	12101	195	0	0
T9	2261	19	0	0
T10	492982	13	0	0
T11	4619	49	0	0
T12	298876	13	0	0
T13	6769	43	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	202773	0	0
T1	49033	72	0	0
T2	8929	11	0	0
T3	2206	11	0	0
T7	66292	167	0	0
T8	12101	195	0	0
T9	2261	19	0	0
T10	492982	13	0	0
T11	4619	49	0	0
T12	298876	13	0	0
T13	6769	43	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	2848934	0	0
T1	49033	578	0	0
T2	8929	73	0	0
T3	2206	12	0	0
T7	66292	1269	0	0
T8	12101	182	0	0
T9	2261	19	0	0
T10	492982	3889	0	0
T11	4619	43	0	0
T12	298876	66	0	0
T13	6769	45	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	202773	0	0
T1	49033	72	0	0
T2	8929	11	0	0
T3	2206	11	0	0
T7	66292	167	0	0
T8	12101	195	0	0
T9	2261	19	0	0
T10	492982	13	0	0
T11	4619	49	0	0
T12	298876	13	0	0
T13	6769	43	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	202773	0	0
T1	49033	72	0	0
T2	8929	11	0	0
T3	2206	11	0	0
T7	66292	167	0	0
T8	12101	195	0	0
T9	2261	19	0	0
T10	492982	13	0	0
T11	4619	49	0	0
T12	298876	13	0	0
T13	6769	43	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	477686	0	0
T1	49033	75	0	0
T2	8929	11	0	0
T3	2206	11	0	0
T7	66292	233	0	0
T8	12101	209	0	0
T9	2261	20	0	0
T10	492982	13	0	0
T11	4619	56	0	0
T12	298876	15	0	0
T13	6769	43	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	202773	0	0
T1	49033	72	0	0
T2	8929	11	0	0
T3	2206	11	0	0
T7	66292	167	0	0
T8	12101	195	0	0
T9	2261	19	0	0
T10	492982	13	0	0
T11	4619	49	0	0
T12	298876	13	0	0
T13	6769	43	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	221348	0	0
GntImpliesValid_A	380337288	221348	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	221348	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	2917116	0	0
ReadyAndValidImplyGrant_A	380337288	221348	0	0
ReqAndReadyImplyGrant_A	380337288	221348	0	0
ReqImpliesValid_A	380337288	574021	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	221348	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	221348	0	0
T1	49033	68	0	0
T2	8929	5	0	0
T3	2206	9	0	0
T7	66292	176	0	0
T8	12101	186	0	0
T9	2261	12	0	0
T10	492982	16	0	0
T11	4619	44	0	0
T12	298876	15	0	0
T13	6769	39	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	221348	0	0
T1	49033	68	0	0
T2	8929	5	0	0
T3	2206	9	0	0
T7	66292	176	0	0
T8	12101	186	0	0
T9	2261	12	0	0
T10	492982	16	0	0
T11	4619	44	0	0
T12	298876	15	0	0
T13	6769	39	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	221348	0	0
T1	49033	68	0	0
T2	8929	5	0	0
T3	2206	9	0	0
T7	66292	176	0	0
T8	12101	186	0	0
T9	2261	12	0	0
T10	492982	16	0	0
T11	4619	44	0	0
T12	298876	15	0	0
T13	6769	39	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	2917116	0	0
T1	49033	560	0	0
T2	8929	24	0	0
T3	2206	10	0	0
T7	66292	1351	0	0
T8	12101	181	0	0
T9	2261	13	0	0
T10	492982	4350	0	0
T11	4619	43	0	0
T12	298876	73	0	0
T13	6769	41	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	221348	0	0
T1	49033	68	0	0
T2	8929	5	0	0
T3	2206	9	0	0
T7	66292	176	0	0
T8	12101	186	0	0
T9	2261	12	0	0
T10	492982	16	0	0
T11	4619	44	0	0
T12	298876	15	0	0
T13	6769	39	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	221348	0	0
T1	49033	68	0	0
T2	8929	5	0	0
T3	2206	9	0	0
T7	66292	176	0	0
T8	12101	186	0	0
T9	2261	12	0	0
T10	492982	16	0	0
T11	4619	44	0	0
T12	298876	15	0	0
T13	6769	39	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	574021	0	0
T1	49033	79	0	0
T2	8929	5	0	0
T3	2206	9	0	0
T7	66292	262	0	0
T8	12101	192	0	0
T9	2261	12	0	0
T10	492982	982	0	0
T11	4619	46	0	0
T12	298876	19	0	0
T13	6769	39	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	221348	0	0
T1	49033	68	0	0
T2	8929	5	0	0
T3	2206	9	0	0
T7	66292	176	0	0
T8	12101	186	0	0
T9	2261	12	0	0
T10	492982	16	0	0
T11	4619	44	0	0
T12	298876	15	0	0
T13	6769	39	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	220918	0	0
GntImpliesValid_A	380337288	220918	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	220918	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	2850330	0	0
ReadyAndValidImplyGrant_A	380337288	220918	0	0
ReqAndReadyImplyGrant_A	380337288	220918	0	0
ReqImpliesValid_A	380337288	587633	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	220918	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	220918	0	0
T1	49033	99	0	0
T2	8929	9	0	0
T3	2206	11	0	0
T7	66292	144	0	0
T8	12101	203	0	0
T9	2261	14	0	0
T10	492982	10	0	0
T11	4619	47	0	0
T12	298876	17	0	0
T13	6769	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	220918	0	0
T1	49033	99	0	0
T2	8929	9	0	0
T3	2206	11	0	0
T7	66292	144	0	0
T8	12101	203	0	0
T9	2261	14	0	0
T10	492982	10	0	0
T11	4619	47	0	0
T12	298876	17	0	0
T13	6769	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	220918	0	0
T1	49033	99	0	0
T2	8929	9	0	0
T3	2206	11	0	0
T7	66292	144	0	0
T8	12101	203	0	0
T9	2261	14	0	0
T10	492982	10	0	0
T11	4619	47	0	0
T12	298876	17	0	0
T13	6769	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	2850330	0	0
T1	49033	792	0	0
T2	8929	61	0	0
T3	2206	11	0	0
T7	66292	1132	0	0
T8	12101	187	0	0
T9	2261	15	0	0
T10	492982	4121	0	0
T11	4619	48	0	0
T12	298876	54	0	0
T13	6769	42	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	220918	0	0
T1	49033	99	0	0
T2	8929	9	0	0
T3	2206	11	0	0
T7	66292	144	0	0
T8	12101	203	0	0
T9	2261	14	0	0
T10	492982	10	0	0
T11	4619	47	0	0
T12	298876	17	0	0
T13	6769	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	220918	0	0
T1	49033	99	0	0
T2	8929	9	0	0
T3	2206	11	0	0
T7	66292	144	0	0
T8	12101	203	0	0
T9	2261	14	0	0
T10	492982	10	0	0
T11	4619	47	0	0
T12	298876	17	0	0
T13	6769	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	587633	0	0
T1	49033	143	0	0
T2	8929	9	0	0
T3	2206	12	0	0
T7	66292	185	0	0
T8	12101	220	0	0
T9	2261	14	0	0
T10	492982	10	0	0
T11	4619	47	0	0
T12	298876	23	0	0
T13	6769	40	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	220918	0	0
T1	49033	99	0	0
T2	8929	9	0	0
T3	2206	11	0	0
T7	66292	144	0	0
T8	12101	203	0	0
T9	2261	14	0	0
T10	492982	10	0	0
T11	4619	47	0	0
T12	298876	17	0	0
T13	6769	40	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	215361	0	0
GntImpliesValid_A	380337288	215361	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	215361	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	2824214	0	0
ReadyAndValidImplyGrant_A	380337288	215361	0	0
ReqAndReadyImplyGrant_A	380337288	215361	0	0
ReqImpliesValid_A	380337288	543266	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	215361	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	215361	0	0
T1	49033	77	0	0
T2	8929	14	0	0
T3	2206	14	0	0
T7	66292	156	0	0
T8	12101	187	0	0
T9	2261	11	0	0
T10	492982	17	0	0
T11	4619	49	0	0
T12	298876	22	0	0
T13	6769	50	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	215361	0	0
T1	49033	77	0	0
T2	8929	14	0	0
T3	2206	14	0	0
T7	66292	156	0	0
T8	12101	187	0	0
T9	2261	11	0	0
T10	492982	17	0	0
T11	4619	49	0	0
T12	298876	22	0	0
T13	6769	50	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	215361	0	0
T1	49033	77	0	0
T2	8929	14	0	0
T3	2206	14	0	0
T7	66292	156	0	0
T8	12101	187	0	0
T9	2261	11	0	0
T10	492982	17	0	0
T11	4619	49	0	0
T12	298876	22	0	0
T13	6769	50	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	2824214	0	0
T1	49033	656	0	0
T2	8929	110	0	0
T3	2206	15	0	0
T7	66292	1176	0	0
T8	12101	173	0	0
T9	2261	11	0	0
T10	492982	5269	0	0
T11	4619	47	0	0
T12	298876	105	0	0
T13	6769	52	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	215361	0	0
T1	49033	77	0	0
T2	8929	14	0	0
T3	2206	14	0	0
T7	66292	156	0	0
T8	12101	187	0	0
T9	2261	11	0	0
T10	492982	17	0	0
T11	4619	49	0	0
T12	298876	22	0	0
T13	6769	50	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	215361	0	0
T1	49033	77	0	0
T2	8929	14	0	0
T3	2206	14	0	0
T7	66292	156	0	0
T8	12101	187	0	0
T9	2261	11	0	0
T10	492982	17	0	0
T11	4619	49	0	0
T12	298876	22	0	0
T13	6769	50	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	543266	0	0
T1	49033	97	0	0
T2	8929	14	0	0
T3	2206	14	0	0
T7	66292	215	0	0
T8	12101	202	0	0
T9	2261	12	0	0
T10	492982	264	0	0
T11	4619	52	0	0
T12	298876	23	0	0
T13	6769	50	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	215361	0	0
T1	49033	77	0	0
T2	8929	14	0	0
T3	2206	14	0	0
T7	66292	156	0	0
T8	12101	187	0	0
T9	2261	11	0	0
T10	492982	17	0	0
T11	4619	49	0	0
T12	298876	22	0	0
T13	6769	50	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	221915	0	0
GntImpliesValid_A	380337288	221915	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	221915	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	2842933	0	0
ReadyAndValidImplyGrant_A	380337288	221915	0	0
ReqAndReadyImplyGrant_A	380337288	221915	0	0
ReqImpliesValid_A	380337288	525116	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	221915	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	221915	0	0
T1	49033	67	0	0
T2	8929	10	0	0
T3	2206	20	0	0
T7	66292	205	0	0
T8	12101	182	0	0
T9	2261	21	0	0
T10	492982	17	0	0
T11	4619	54	0	0
T12	298876	11	0	0
T13	6769	36	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	221915	0	0
T1	49033	67	0	0
T2	8929	10	0	0
T3	2206	20	0	0
T7	66292	205	0	0
T8	12101	182	0	0
T9	2261	21	0	0
T10	492982	17	0	0
T11	4619	54	0	0
T12	298876	11	0	0
T13	6769	36	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	221915	0	0
T1	49033	67	0	0
T2	8929	10	0	0
T3	2206	20	0	0
T7	66292	205	0	0
T8	12101	182	0	0
T9	2261	21	0	0
T10	492982	17	0	0
T11	4619	54	0	0
T12	298876	11	0	0
T13	6769	36	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	2842933	0	0
T1	49033	490	0	0
T2	8929	72	0	0
T3	2206	17	0	0
T7	66292	1519	0	0
T8	12101	177	0	0
T9	2261	20	0	0
T10	492982	5440	0	0
T11	4619	51	0	0
T12	298876	54	0	0
T13	6769	38	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	221915	0	0
T1	49033	67	0	0
T2	8929	10	0	0
T3	2206	20	0	0
T7	66292	205	0	0
T8	12101	182	0	0
T9	2261	21	0	0
T10	492982	17	0	0
T11	4619	54	0	0
T12	298876	11	0	0
T13	6769	36	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	221915	0	0
T1	49033	67	0	0
T2	8929	10	0	0
T3	2206	20	0	0
T7	66292	205	0	0
T8	12101	182	0	0
T9	2261	21	0	0
T10	492982	17	0	0
T11	4619	54	0	0
T12	298876	11	0	0
T13	6769	36	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	525116	0	0
T1	49033	149	0	0
T2	8929	10	0	0
T3	2206	24	0	0
T7	66292	334	0	0
T8	12101	188	0	0
T9	2261	23	0	0
T10	492982	64	0	0
T11	4619	58	0	0
T12	298876	11	0	0
T13	6769	36	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	221915	0	0
T1	49033	67	0	0
T2	8929	10	0	0
T3	2206	20	0	0
T7	66292	205	0	0
T8	12101	182	0	0
T9	2261	21	0	0
T10	492982	17	0	0
T11	4619	54	0	0
T12	298876	11	0	0
T13	6769	36	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	229337	0	0
GntImpliesValid_A	380337288	229337	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	229337	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	2857782	0	0
ReadyAndValidImplyGrant_A	380337288	229337	0	0
ReqAndReadyImplyGrant_A	380337288	229337	0	0
ReqImpliesValid_A	380337288	552501	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	229337	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	229337	0	0
T1	49033	147	0	0
T2	8929	9	0	0
T3	2206	14	0	0
T7	66292	166	0	0
T8	12101	181	0	0
T9	2261	15	0	0
T10	492982	6	0	0
T11	4619	104	0	0
T12	298876	10	0	0
T13	6769	74	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	229337	0	0
T1	49033	147	0	0
T2	8929	9	0	0
T3	2206	14	0	0
T7	66292	166	0	0
T8	12101	181	0	0
T9	2261	15	0	0
T10	492982	6	0	0
T11	4619	104	0	0
T12	298876	10	0	0
T13	6769	74	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	229337	0	0
T1	49033	147	0	0
T2	8929	9	0	0
T3	2206	14	0	0
T7	66292	166	0	0
T8	12101	181	0	0
T9	2261	15	0	0
T10	492982	6	0	0
T11	4619	104	0	0
T12	298876	10	0	0
T13	6769	74	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	2857782	0	0
T1	49033	1198	0	0
T2	8929	58	0	0
T3	2206	15	0	0
T7	66292	1291	0	0
T8	12101	169	0	0
T9	2261	16	0	0
T10	492982	3787	0	0
T11	4619	101	0	0
T12	298876	43	0	0
T13	6769	74	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	229337	0	0
T1	49033	147	0	0
T2	8929	9	0	0
T3	2206	14	0	0
T7	66292	166	0	0
T8	12101	181	0	0
T9	2261	15	0	0
T10	492982	6	0	0
T11	4619	104	0	0
T12	298876	10	0	0
T13	6769	74	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	229337	0	0
T1	49033	147	0	0
T2	8929	9	0	0
T3	2206	14	0	0
T7	66292	166	0	0
T8	12101	181	0	0
T9	2261	15	0	0
T10	492982	6	0	0
T11	4619	104	0	0
T12	298876	10	0	0
T13	6769	74	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	552501	0	0
T1	49033	197	0	0
T2	8929	9	0	0
T3	2206	14	0	0
T7	66292	211	0	0
T8	12101	194	0	0
T9	2261	15	0	0
T10	492982	6	0	0
T11	4619	108	0	0
T12	298876	10	0	0
T13	6769	76	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	229337	0	0
T1	49033	147	0	0
T2	8929	9	0	0
T3	2206	14	0	0
T7	66292	166	0	0
T8	12101	181	0	0
T9	2261	15	0	0
T10	492982	6	0	0
T11	4619	104	0	0
T12	298876	10	0	0
T13	6769	74	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	208519	0	0
GntImpliesValid_A	380337288	208519	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	208519	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	2843307	0	0
ReadyAndValidImplyGrant_A	380337288	208519	0	0
ReqAndReadyImplyGrant_A	380337288	208519	0	0
ReqImpliesValid_A	380337288	548334	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	208519	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	208519	0	0
T1	49033	82	0	0
T2	8929	10	0	0
T3	2206	8	0	0
T7	66292	167	0	0
T8	12101	175	0	0
T9	2261	14	0	0
T10	492982	14	0	0
T11	4619	44	0	0
T12	298876	14	0	0
T13	6769	43	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	208519	0	0
T1	49033	82	0	0
T2	8929	10	0	0
T3	2206	8	0	0
T7	66292	167	0	0
T8	12101	175	0	0
T9	2261	14	0	0
T10	492982	14	0	0
T11	4619	44	0	0
T12	298876	14	0	0
T13	6769	43	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	208519	0	0
T1	49033	82	0	0
T2	8929	10	0	0
T3	2206	8	0	0
T7	66292	167	0	0
T8	12101	175	0	0
T9	2261	14	0	0
T10	492982	14	0	0
T11	4619	44	0	0
T12	298876	14	0	0
T13	6769	43	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	2843307	0	0
T1	49033	593	0	0
T2	8929	68	0	0
T3	2206	9	0	0
T7	66292	1349	0	0
T8	12101	164	0	0
T9	2261	15	0	0
T10	492982	3435	0	0
T11	4619	43	0	0
T12	298876	53	0	0
T13	6769	42	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	208519	0	0
T1	49033	82	0	0
T2	8929	10	0	0
T3	2206	8	0	0
T7	66292	167	0	0
T8	12101	175	0	0
T9	2261	14	0	0
T10	492982	14	0	0
T11	4619	44	0	0
T12	298876	14	0	0
T13	6769	43	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	208519	0	0
T1	49033	82	0	0
T2	8929	10	0	0
T3	2206	8	0	0
T7	66292	167	0	0
T8	12101	175	0	0
T9	2261	14	0	0
T10	492982	14	0	0
T11	4619	44	0	0
T12	298876	14	0	0
T13	6769	43	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	548334	0	0
T1	49033	120	0	0
T2	8929	10	0	0
T3	2206	8	0	0
T7	66292	227	0	0
T8	12101	187	0	0
T9	2261	14	0	0
T10	492982	71	0	0
T11	4619	46	0	0
T12	298876	14	0	0
T13	6769	46	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	208519	0	0
T1	49033	82	0	0
T2	8929	10	0	0
T3	2206	8	0	0
T7	66292	167	0	0
T8	12101	175	0	0
T9	2261	14	0	0
T10	492982	14	0	0
T11	4619	44	0	0
T12	298876	14	0	0
T13	6769	43	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	217234	0	0
GntImpliesValid_A	380337288	217234	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	217234	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	2859940	0	0
ReadyAndValidImplyGrant_A	380337288	217234	0	0
ReqAndReadyImplyGrant_A	380337288	217234	0	0
ReqImpliesValid_A	380337288	556123	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	217234	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	217234	0	0
T1	49033	79	0	0
T2	8929	6	0	0
T3	2206	10	0	0
T7	66292	171	0	0
T8	12101	166	0	0
T9	2261	10	0	0
T10	492982	12	0	0
T11	4619	40	0	0
T12	298876	11	0	0
T13	6769	35	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	217234	0	0
T1	49033	79	0	0
T2	8929	6	0	0
T3	2206	10	0	0
T7	66292	171	0	0
T8	12101	166	0	0
T9	2261	10	0	0
T10	492982	12	0	0
T11	4619	40	0	0
T12	298876	11	0	0
T13	6769	35	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	217234	0	0
T1	49033	79	0	0
T2	8929	6	0	0
T3	2206	10	0	0
T7	66292	171	0	0
T8	12101	166	0	0
T9	2261	10	0	0
T10	492982	12	0	0
T11	4619	40	0	0
T12	298876	11	0	0
T13	6769	35	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	2859940	0	0
T1	49033	525	0	0
T2	8929	49	0	0
T3	2206	10	0	0
T7	66292	1208	0	0
T8	12101	156	0	0
T9	2261	10	0	0
T10	492982	4504	0	0
T11	4619	40	0	0
T12	298876	51	0	0
T13	6769	37	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	217234	0	0
T1	49033	79	0	0
T2	8929	6	0	0
T3	2206	10	0	0
T7	66292	171	0	0
T8	12101	166	0	0
T9	2261	10	0	0
T10	492982	12	0	0
T11	4619	40	0	0
T12	298876	11	0	0
T13	6769	35	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	217234	0	0
T1	49033	79	0	0
T2	8929	6	0	0
T3	2206	10	0	0
T7	66292	171	0	0
T8	12101	166	0	0
T9	2261	10	0	0
T10	492982	12	0	0
T11	4619	40	0	0
T12	298876	11	0	0
T13	6769	35	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	556123	0	0
T1	49033	87	0	0
T2	8929	6	0	0
T3	2206	11	0	0
T7	66292	219	0	0
T8	12101	177	0	0
T9	2261	11	0	0
T10	492982	69	0	0
T11	4619	41	0	0
T12	298876	11	0	0
T13	6769	35	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	217234	0	0
T1	49033	79	0	0
T2	8929	6	0	0
T3	2206	10	0	0
T7	66292	171	0	0
T8	12101	166	0	0
T9	2261	10	0	0
T10	492982	12	0	0
T11	4619	40	0	0
T12	298876	11	0	0
T13	6769	35	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	219208	0	0
GntImpliesValid_A	380337288	219208	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	219208	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	2860919	0	0
ReadyAndValidImplyGrant_A	380337288	219208	0	0
ReqAndReadyImplyGrant_A	380337288	219208	0	0
ReqImpliesValid_A	380337288	569539	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	219208	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	219208	0	0
T1	49033	75	0	0
T2	8929	4	0	0
T3	2206	8	0	0
T7	66292	168	0	0
T8	12101	176	0	0
T9	2261	15	0	0
T10	492982	10	0	0
T11	4619	46	0	0
T12	298876	12	0	0
T13	6769	48	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	219208	0	0
T1	49033	75	0	0
T2	8929	4	0	0
T3	2206	8	0	0
T7	66292	168	0	0
T8	12101	176	0	0
T9	2261	15	0	0
T10	492982	10	0	0
T11	4619	46	0	0
T12	298876	12	0	0
T13	6769	48	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	219208	0	0
T1	49033	75	0	0
T2	8929	4	0	0
T3	2206	8	0	0
T7	66292	168	0	0
T8	12101	176	0	0
T9	2261	15	0	0
T10	492982	10	0	0
T11	4619	46	0	0
T12	298876	12	0	0
T13	6769	48	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	2860919	0	0
T1	49033	623	0	0
T2	8929	35	0	0
T3	2206	9	0	0
T7	66292	1254	0	0
T8	12101	168	0	0
T9	2261	16	0	0
T10	492982	2629	0	0
T11	4619	46	0	0
T12	298876	70	0	0
T13	6769	50	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	219208	0	0
T1	49033	75	0	0
T2	8929	4	0	0
T3	2206	8	0	0
T7	66292	168	0	0
T8	12101	176	0	0
T9	2261	15	0	0
T10	492982	10	0	0
T11	4619	46	0	0
T12	298876	12	0	0
T13	6769	48	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	219208	0	0
T1	49033	75	0	0
T2	8929	4	0	0
T3	2206	8	0	0
T7	66292	168	0	0
T8	12101	176	0	0
T9	2261	15	0	0
T10	492982	10	0	0
T11	4619	46	0	0
T12	298876	12	0	0
T13	6769	48	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	569539	0	0
T1	49033	92	0	0
T2	8929	12	0	0
T3	2206	8	0	0
T7	66292	208	0	0
T8	12101	185	0	0
T9	2261	15	0	0
T10	492982	10	0	0
T11	4619	47	0	0
T12	298876	12	0	0
T13	6769	48	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	219208	0	0
T1	49033	75	0	0
T2	8929	4	0	0
T3	2206	8	0	0
T7	66292	168	0	0
T8	12101	176	0	0
T9	2261	15	0	0
T10	492982	10	0	0
T11	4619	46	0	0
T12	298876	12	0	0
T13	6769	48	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	212318	0	0
GntImpliesValid_A	380337288	212318	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	212318	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	2894070	0	0
ReadyAndValidImplyGrant_A	380337288	212318	0	0
ReqAndReadyImplyGrant_A	380337288	212318	0	0
ReqImpliesValid_A	380337288	550418	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	212318	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	212318	0	0
T1	49033	84	0	0
T2	8929	9	0	0
T3	2206	16	0	0
T7	66292	152	0	0
T8	12101	171	0	0
T9	2261	14	0	0
T10	492982	10	0	0
T11	4619	47	0	0
T12	298876	12	0	0
T13	6769	31	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	212318	0	0
T1	49033	84	0	0
T2	8929	9	0	0
T3	2206	16	0	0
T7	66292	152	0	0
T8	12101	171	0	0
T9	2261	14	0	0
T10	492982	10	0	0
T11	4619	47	0	0
T12	298876	12	0	0
T13	6769	31	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	212318	0	0
T1	49033	84	0	0
T2	8929	9	0	0
T3	2206	16	0	0
T7	66292	152	0	0
T8	12101	171	0	0
T9	2261	14	0	0
T10	492982	10	0	0
T11	4619	47	0	0
T12	298876	12	0	0
T13	6769	31	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	2894070	0	0
T1	49033	599	0	0
T2	8929	62	0	0
T3	2206	16	0	0
T7	66292	1018	0	0
T8	12101	163	0	0
T9	2261	13	0	0
T10	492982	3247	0	0
T11	4619	45	0	0
T12	298876	52	0	0
T13	6769	33	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	212318	0	0
T1	49033	84	0	0
T2	8929	9	0	0
T3	2206	16	0	0
T7	66292	152	0	0
T8	12101	171	0	0
T9	2261	14	0	0
T10	492982	10	0	0
T11	4619	47	0	0
T12	298876	12	0	0
T13	6769	31	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	212318	0	0
T1	49033	84	0	0
T2	8929	9	0	0
T3	2206	16	0	0
T7	66292	152	0	0
T8	12101	171	0	0
T9	2261	14	0	0
T10	492982	10	0	0
T11	4619	47	0	0
T12	298876	12	0	0
T13	6769	31	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	550418	0	0
T1	49033	117	0	0
T2	8929	9	0	0
T3	2206	17	0	0
T7	66292	244	0	0
T8	12101	180	0	0
T9	2261	16	0	0
T10	492982	10	0	0
T11	4619	50	0	0
T12	298876	13	0	0
T13	6769	31	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	212318	0	0
T1	49033	84	0	0
T2	8929	9	0	0
T3	2206	16	0	0
T7	66292	152	0	0
T8	12101	171	0	0
T9	2261	14	0	0
T10	492982	10	0	0
T11	4619	47	0	0
T12	298876	12	0	0
T13	6769	31	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	208599	0	0
GntImpliesValid_A	380337288	208599	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	208599	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	2804601	0	0
ReadyAndValidImplyGrant_A	380337288	208599	0	0
ReqAndReadyImplyGrant_A	380337288	208599	0	0
ReqImpliesValid_A	380337288	532640	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	0	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	208599	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	208599	0	0
T1	49033	82	0	0
T2	8929	9	0	0
T3	2206	12	0	0
T7	66292	175	0	0
T8	12101	181	0	0
T9	2261	15	0	0
T10	492982	8	0	0
T11	4619	38	0	0
T12	298876	11	0	0
T13	6769	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	208599	0	0
T1	49033	82	0	0
T2	8929	9	0	0
T3	2206	12	0	0
T7	66292	175	0	0
T8	12101	181	0	0
T9	2261	15	0	0
T10	492982	8	0	0
T11	4619	38	0	0
T12	298876	11	0	0
T13	6769	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	208599	0	0
T1	49033	82	0	0
T2	8929	9	0	0
T3	2206	12	0	0
T7	66292	175	0	0
T8	12101	181	0	0
T9	2261	15	0	0
T10	492982	8	0	0
T11	4619	38	0	0
T12	298876	11	0	0
T13	6769	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	2804601	0	0
T1	49033	553	0	0
T2	8929	92	0	0
T3	2206	12	0	0
T7	66292	1303	0	0
T8	12101	173	0	0
T9	2261	14	0	0
T10	492982	3104	0	0
T11	4619	36	0	0
T12	298876	33	0	0
T13	6769	41	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	208599	0	0
T1	49033	82	0	0
T2	8929	9	0	0
T3	2206	12	0	0
T7	66292	175	0	0
T8	12101	181	0	0
T9	2261	15	0	0
T10	492982	8	0	0
T11	4619	38	0	0
T12	298876	11	0	0
T13	6769	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	208599	0	0
T1	49033	82	0	0
T2	8929	9	0	0
T3	2206	12	0	0
T7	66292	175	0	0
T8	12101	181	0	0
T9	2261	15	0	0
T10	492982	8	0	0
T11	4619	38	0	0
T12	298876	11	0	0
T13	6769	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	532640	0	0
T1	49033	100	0	0
T2	8929	9	0	0
T3	2206	13	0	0
T7	66292	284	0	0
T8	12101	190	0	0
T9	2261	17	0	0
T10	492982	8	0	0
T11	4619	41	0	0
T12	298876	29	0	0
T13	6769	41	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	208599	0	0
T1	49033	82	0	0
T2	8929	9	0	0
T3	2206	12	0	0
T7	66292	175	0	0
T8	12101	181	0	0
T9	2261	15	0	0
T10	492982	8	0	0
T11	4619	38	0	0
T12	298876	11	0	0
T13	6769	40	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	871316	0	0
GntImpliesValid_A	380337288	871316	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	871316	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	10638876	0	0
ReadyAndValidImplyGrant_A	380337288	871316	0	0
ReqAndReadyImplyGrant_A	380337288	871316	0	0
ReqImpliesValid_A	380337288	2169351	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	22403	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	871316	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	871316	0	0
T1	49033	352	0	0
T2	8929	49	0	0
T3	2206	49	0	0
T7	66292	697	0	0
T8	12101	753	0	0
T9	2261	55	0	0
T10	492982	56	0	0
T11	4619	178	0	0
T12	298876	44	0	0
T13	6769	285	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	871316	0	0
T1	49033	352	0	0
T2	8929	49	0	0
T3	2206	49	0	0
T7	66292	697	0	0
T8	12101	753	0	0
T9	2261	55	0	0
T10	492982	56	0	0
T11	4619	178	0	0
T12	298876	44	0	0
T13	6769	285	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	871316	0	0
T1	49033	352	0	0
T2	8929	49	0	0
T3	2206	49	0	0
T7	66292	697	0	0
T8	12101	753	0	0
T9	2261	55	0	0
T10	492982	56	0	0
T11	4619	178	0	0
T12	298876	44	0	0
T13	6769	285	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	10638876	0	0
T1	49033	2358	0	0
T2	8929	359	0	0
T3	2206	1	0	0
T7	66292	3994	0	0
T8	12101	1	0	0
T9	2261	1	0	0
T10	492982	19074	0	0
T11	4619	1	0	0
T12	298876	191	0	0
T13	6769	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	871316	0	0
T1	49033	352	0	0
T2	8929	49	0	0
T3	2206	49	0	0
T7	66292	697	0	0
T8	12101	753	0	0
T9	2261	55	0	0
T10	492982	56	0	0
T11	4619	178	0	0
T12	298876	44	0	0
T13	6769	285	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	871316	0	0
T1	49033	352	0	0
T2	8929	49	0	0
T3	2206	49	0	0
T7	66292	697	0	0
T8	12101	753	0	0
T9	2261	55	0	0
T10	492982	56	0	0
T11	4619	178	0	0
T12	298876	44	0	0
T13	6769	285	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	2169351	0	0
T1	49033	488	0	0
T2	8929	75	0	0
T3	2206	49	0	0
T7	66292	1074	0	0
T8	12101	753	0	0
T9	2261	55	0	0
T10	492982	2178	0	0
T11	4619	178	0	0
T12	298876	54	0	0
T13	6769	285	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	22403	0	900
T8	12101	11	0	1
T9	2261	0	0	1
T10	492982	0	0	1
T11	4619	1	0	1
T12	298876	0	0	1
T13	6769	0	0	1
T14	6053	4	0	1
T15	0	13	0	0
T16	0	68	0	0
T17	0	14	0	0
T18	0	3	0	0
T19	0	1	0	0
T21	0	17	0	0
T22	0	1	0	0
T23	9993	0	0	1
T24	32486	0	0	1
T25	15226	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	871316	0	0
T1	49033	352	0	0
T2	8929	49	0	0
T3	2206	49	0	0
T7	66292	697	0	0
T8	12101	753	0	0
T9	2261	55	0	0
T10	492982	56	0	0
T11	4619	178	0	0
T12	298876	44	0	0
T13	6769	285	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380337288	380229951	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	380337288	853888	0	0
GntImpliesValid_A	380337288	853888	0	0
GrantKnown_A	380337288	380229951	0	0
IdxKnown_A	380337288	380229951	0	0
IndexIsCorrect_A	380337288	853888	0	0
LockArbDecision_A	380337288	0	0	0
NoReadyValidNoGrant_A	380337288	319378275	0	0
ReadyAndValidImplyGrant_A	380337288	853888	0	0
ReqAndReadyImplyGrant_A	380337288	853888	0	0
ReqImpliesValid_A	380337288	12786883	0	0
ReqStaysHighUntilGranted0_M	380337288	0	0	0
RoundRobin_A	380337288	26123	0	900
ValidKnown_A	380337288	380229951	0	0
gen_data_port_assertion.DataFlow_A	380337288	853888	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	853888	0	0
T1	49033	318	0	0
T2	8929	32	0	0
T3	2206	64	0	0
T7	66292	696	0	0
T8	12101	782	0	0
T9	2261	47	0	0
T10	492982	63	0	0
T11	4619	158	0	0
T12	298876	31	0	0
T13	6769	300	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	853888	0	0
T1	49033	318	0	0
T2	8929	32	0	0
T3	2206	64	0	0
T7	66292	696	0	0
T8	12101	782	0	0
T9	2261	47	0	0
T10	492982	63	0	0
T11	4619	158	0	0
T12	298876	31	0	0
T13	6769	300	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	853888	0	0
T1	49033	318	0	0
T2	8929	32	0	0
T3	2206	64	0	0
T7	66292	696	0	0
T8	12101	782	0	0
T9	2261	47	0	0
T10	492982	63	0	0
T11	4619	158	0	0
T12	298876	31	0	0
T13	6769	300	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	319378275	0	0
T1	49033	42206	0	0
T2	8929	7825	0	0
T3	2206	1	0	0
T7	66292	53460	0	0
T8	12101	1	0	0
T9	2261	1	0	0
T10	492982	470716	0	0
T11	4619	1	0	0
T12	298876	248760	0	0
T13	6769	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	853888	0	0
T1	49033	318	0	0
T2	8929	32	0	0
T3	2206	64	0	0
T7	66292	696	0	0
T8	12101	782	0	0
T9	2261	47	0	0
T10	492982	63	0	0
T11	4619	158	0	0
T12	298876	31	0	0
T13	6769	300	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	853888	0	0
T1	49033	318	0	0
T2	8929	32	0	0
T3	2206	64	0	0
T7	66292	696	0	0
T8	12101	782	0	0
T9	2261	47	0	0
T10	492982	63	0	0
T11	4619	158	0	0
T12	298876	31	0	0
T13	6769	300	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	12786883	0	0
T1	49033	2603	0	0
T2	8929	293	0	0
T3	2206	64	0	0
T7	66292	5389	0	0
T8	12101	782	0	0
T9	2261	47	0	0
T10	492982	21290	0	0
T11	4619	158	0	0
T12	298876	117	0	0
T13	6769	300	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	26123	0	900
T8	12101	18	0	1
T9	2261	0	0	1
T10	492982	0	0	1
T11	4619	1	0	1
T12	298876	0	0	1
T13	6769	1	0	1
T14	6053	4	0	1
T15	0	19	0	0
T17	0	16	0	0
T18	0	1	0	0
T20	0	1	0	0
T21	0	20	0	0
T22	0	1	0	0
T23	9993	0	0	1
T24	32486	0	0	1
T25	15226	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	380229951	0	0
T1	49033	48943	0	0
T2	8929	8896	0	0
T3	2206	2169	0	0
T7	66292	66240	0	0
T8	12101	12042	0	0
T9	2261	2210	0	0
T10	492982	492930	0	0
T11	4619	4559	0	0
T12	298876	298836	0	0
T13	6769	6720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380337288	853888	0	0
T1	49033	318	0	0
T2	8929	32	0	0
T3	2206	64	0	0
T7	66292	696	0	0
T8	12101	782	0	0
T9	2261	47	0	0
T10	492982	63	0	0
T11	4619	158	0	0
T12	298876	31	0	0
T13	6769	300	0	0