Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1565106	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

248338

1

T1

45

T2

51

T3

1317

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	614936	1			T1	106		T2	200		T3	3116
values[0x0]	583528	1			T1	107		T2	33		T3	3096
values[0x1]	614980	1			T1	104		T2	223		T3	3420

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1210585	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

602859

1

T1

104

T2

182

T3

3241

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28661	1			T1	5		T2	9		T3	199
valid_sources[0x01]	28378	1			T1	6		T2	6		T3	201
valid_sources[0x02]	29139	1			T1	7		T2	7		T3	178
valid_sources[0x03]	28441	1			T1	7		T2	9		T3	230
valid_sources[0x04]	28603	1			T1	2		T2	3		T3	155
valid_sources[0x05]	27576	1			T1	1		T2	7		T3	180
valid_sources[0x06]	28424	1			T1	8		T2	9		T3	162
valid_sources[0x07]	28769	1			T1	5		T2	12		T3	153
valid_sources[0x08]	27532	1			T1	6		T2	4		T3	101
valid_sources[0x09]	29185	1			T1	6		T2	11		T3	131
valid_sources[0x0a]	28625	1			T1	3		T2	6		T3	165
valid_sources[0x0b]	28086	1			T1	11		T2	10		T3	167
valid_sources[0x0c]	27664	1			T1	4		T2	7		T3	130
valid_sources[0x0d]	27334	1			T1	9		T2	4		T3	179
valid_sources[0x0e]	29018	1			T1	7		T2	9		T3	168
valid_sources[0x0f]	27650	1			T1	2		T2	4		T3	186
valid_sources[0x10]	28483	1			T1	2		T2	7		T3	186
valid_sources[0x11]	28407	1			T1	5		T2	9		T3	114
valid_sources[0x12]	27939	1			T1	7		T2	12		T3	147
valid_sources[0x13]	28668	1			T1	3		T2	6		T3	134
valid_sources[0x14]	29036	1			T1	4		T2	7		T3	121
valid_sources[0x15]	27795	1			T1	6		T2	7		T3	127
valid_sources[0x16]	27886	1			T1	4		T2	16		T3	161
valid_sources[0x17]	27245	1			T1	4		T2	4		T3	133
valid_sources[0x18]	28538	1			T1	3		T2	5		T3	119
valid_sources[0x19]	28044	1			T1	6		T2	4		T3	130
valid_sources[0x1a]	29105	1			T1	3		T2	6		T3	81
valid_sources[0x1b]	28124	1			T1	5		T2	2		T3	115
valid_sources[0x1c]	29230	1			T1	5		T2	16		T3	94
valid_sources[0x1d]	28263	1			T2	5		T3	139		T7	118
valid_sources[0x1e]	28619	1			T1	8		T2	5		T3	179
valid_sources[0x1f]	27603	1			T1	8		T2	5		T3	116
valid_sources[0x20]	28106	1			T1	2		T2	7		T3	102

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26074

1

T1

3

T2

23

T3

132

values[0x0]

all_enables

biggest_size

196277

1

T1

37

T2

12

T3

1043

values[0x1]

all_enables

biggest_size

25987

1

T1

5

T2

16

T3

142

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1571679	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

256019

1

T1

45

T2

44

T3

1411

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	624827	1			T1	92		T2	177		T3	3512
values[0x0]	577571	1			T1	120		T2	42		T3	3283
values[0x1]	625300	1			T1	118		T2	188		T3	3533

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1206857	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

620841

1

T1

112

T2

151

T3

3451

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28551	1			T2	3		T3	177		T7	119
valid_sources[0x01]	27396	1			T2	5		T3	211		T7	67
valid_sources[0x02]	29121	1			T2	2		T3	224		T7	168
valid_sources[0x03]	28063	1			T2	12		T3	229		T7	173
valid_sources[0x04]	27929	1			T2	4		T3	152		T7	206
valid_sources[0x05]	28580	1			T2	5		T3	160		T7	132
valid_sources[0x06]	28668	1			T2	7		T3	172		T7	71
valid_sources[0x07]	29005	1			T2	7		T3	167		T7	170
valid_sources[0x08]	28570	1			T1	24		T2	8		T3	163
valid_sources[0x09]	28035	1			T1	5		T2	7		T3	155
valid_sources[0x0a]	28964	1			T2	4		T3	212		T7	96
valid_sources[0x0b]	29333	1			T2	6		T3	154		T7	150
valid_sources[0x0c]	28575	1			T2	7		T3	163		T7	131
valid_sources[0x0d]	28840	1			T2	12		T3	150		T7	131
valid_sources[0x0e]	28759	1			T1	9		T2	9		T3	208
valid_sources[0x0f]	28253	1			T2	2		T3	178		T7	72
valid_sources[0x10]	28498	1			T2	6		T3	162		T7	74
valid_sources[0x11]	28807	1			T2	3		T3	133		T7	176
valid_sources[0x12]	28839	1			T2	5		T3	159		T7	155
valid_sources[0x13]	27937	1			T1	11		T2	4		T3	169
valid_sources[0x14]	28218	1			T2	10		T3	164		T7	145
valid_sources[0x15]	28738	1			T2	6		T3	154		T7	108
valid_sources[0x16]	28365	1			T2	3		T3	124		T7	129
valid_sources[0x17]	28804	1			T2	9		T3	166		T7	69
valid_sources[0x18]	28871	1			T2	1		T3	126		T7	185
valid_sources[0x19]	28727	1			T2	7		T3	141		T7	132
valid_sources[0x1a]	29489	1			T2	7		T3	106		T7	123
valid_sources[0x1b]	28145	1			T2	7		T3	110		T7	103
valid_sources[0x1c]	28481	1			T2	5		T3	124		T7	137
valid_sources[0x1d]	28216	1			T2	6		T3	139		T7	82
valid_sources[0x1e]	28597	1			T1	35		T2	5		T3	178
valid_sources[0x1f]	28164	1			T2	10		T3	166		T7	114
valid_sources[0x20]	28372	1			T1	16		T2	10		T3	114

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26909

1

T1

4

T2

11

T3

140

values[0x0]

all_enables

biggest_size

202473

1

T1

36

T2

19

T3

1128

values[0x1]

all_enables

biggest_size

26637

1

T1

5

T2

14

T3

143

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1572637	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

250028

1

T1

40

T2

39

T3

1437

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	617716	1			T1	77		T2	177		T3	3557
values[0x0]	587249	1			T1	85		T2	36		T3	3426
values[0x1]	617700	1			T1	92		T2	183		T3	3394

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1215641	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

607024

1

T1

82

T2

149

T3

3376

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28016	1			T1	3		T2	8		T3	186
valid_sources[0x01]	27903	1			T1	1		T2	5		T3	206
valid_sources[0x02]	28795	1			T2	3		T3	208		T7	135
valid_sources[0x03]	28945	1			T2	4		T3	223		T7	140
valid_sources[0x04]	28297	1			T2	6		T3	131		T7	177
valid_sources[0x05]	28774	1			T1	4		T2	10		T3	146
valid_sources[0x06]	28503	1			T1	2		T2	4		T3	180
valid_sources[0x07]	28349	1			T1	10		T2	8		T3	146
valid_sources[0x08]	28063	1			T1	4		T2	9		T3	149
valid_sources[0x09]	28950	1			T1	23		T2	8		T3	154
valid_sources[0x0a]	28782	1			T2	8		T3	196		T7	100
valid_sources[0x0b]	29039	1			T2	7		T3	164		T7	144
valid_sources[0x0c]	28544	1			T2	2		T3	153		T7	111
valid_sources[0x0d]	28347	1			T1	11		T2	7		T3	185
valid_sources[0x0e]	28584	1			T1	3		T2	8		T3	187
valid_sources[0x0f]	28088	1			T2	4		T3	166		T7	102
valid_sources[0x10]	28683	1			T2	7		T3	179		T7	132
valid_sources[0x11]	28512	1			T1	9		T2	7		T3	160
valid_sources[0x12]	28951	1			T1	3		T2	3		T3	159
valid_sources[0x13]	27477	1			T1	6		T2	4		T3	126
valid_sources[0x14]	28561	1			T1	1		T2	7		T3	204
valid_sources[0x15]	27873	1			T2	10		T3	140		T7	135
valid_sources[0x16]	28391	1			T1	4		T2	6		T3	138
valid_sources[0x17]	27640	1			T1	1		T2	9		T3	170
valid_sources[0x18]	29075	1			T1	20		T2	5		T3	189
valid_sources[0x19]	28019	1			T2	5		T3	131		T7	112
valid_sources[0x1a]	29002	1			T1	6		T2	6		T3	109
valid_sources[0x1b]	28379	1			T1	7		T2	3		T3	113
valid_sources[0x1c]	28660	1			T1	7		T2	5		T3	120
valid_sources[0x1d]	28558	1			T1	23		T2	4		T3	155
valid_sources[0x1e]	28998	1			T2	5		T3	172		T7	116
valid_sources[0x1f]	28389	1			T2	9		T3	165		T7	138
valid_sources[0x20]	28975	1			T2	10		T3	138		T7	146

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26242

1

T1

4

T2

12

T3

146

values[0x0]

all_enables

biggest_size

197694

1

T1

32

T2

14

T3

1166

values[0x1]

all_enables

biggest_size

26092

1

T1

4

T2

13

T3

125