Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7649843	0	0
GntImpliesValid_A	2147483647	7649843	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7649843	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	473485517	0	0
ReadyAndValidImplyGrant_A	2147483647	7649843	0	0
ReqAndReadyImplyGrant_A	2147483647	7649843	0	0
ReqImpliesValid_A	2147483647	34497266	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	40589	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7649843	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	169824	168864	0	0
T2	8030232	8025192	0	0
T3	7613328	7585080	0	0
T7	4698168	4688472	0	0
T8	303912	301944	0	0
T9	44856	44232	0	0
T10	2489904	2489544	0	0
T11	3381792	3381696	0	0
T12	6819432	6818256	0	0
T13	585144	583656	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7649843	0	0
T1	169824	460	0	0
T2	8030232	23274	0	0
T3	7613328	29711	0	0
T7	4698168	21267	0	0
T8	303912	883	0	0
T9	44856	486	0	0
T10	2489904	10596	0	0
T11	3381792	4861	0	0
T12	6819432	425	0	0
T13	585144	1642	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7649843	0	0
T1	169824	460	0	0
T2	8030232	23274	0	0
T3	7613328	29711	0	0
T7	4698168	21267	0	0
T8	303912	883	0	0
T9	44856	486	0	0
T10	2489904	10596	0	0
T11	3381792	4861	0	0
T12	6819432	425	0	0
T13	585144	1642	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	169824	168864	0	0
T2	8030232	8025192	0	0
T3	7613328	7585080	0	0
T7	4698168	4688472	0	0
T8	303912	301944	0	0
T9	44856	44232	0	0
T10	2489904	2489544	0	0
T11	3381792	3381696	0	0
T12	6819432	6818256	0	0
T13	585144	583656	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	169824	168864	0	0
T2	8030232	8025192	0	0
T3	7613328	7585080	0	0
T7	4698168	4688472	0	0
T8	303912	301944	0	0
T9	44856	44232	0	0
T10	2489904	2489544	0	0
T11	3381792	3381696	0	0
T12	6819432	6818256	0	0
T13	585144	583656	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7649843	0	0
T1	169824	460	0	0
T2	8030232	23274	0	0
T3	7613328	29711	0	0
T7	4698168	21267	0	0
T8	303912	883	0	0
T9	44856	486	0	0
T10	2489904	10596	0	0
T11	3381792	4861	0	0
T12	6819432	425	0	0
T13	585144	1642	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	473485517	0	0
T1	169824	9109	0	0
T2	8030232	454749	0	0
T3	7613328	484371	0	0
T7	4698168	301059	0	0
T8	303912	17679	0	0
T9	44856	482	0	0
T10	2489904	140403	0	0
T11	3381792	138156	0	0
T12	6819432	238087	0	0
T13	585144	33050	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7649843	0	0
T1	169824	460	0	0
T2	8030232	23274	0	0
T3	7613328	29711	0	0
T7	4698168	21267	0	0
T8	303912	883	0	0
T9	44856	486	0	0
T10	2489904	10596	0	0
T11	3381792	4861	0	0
T12	6819432	425	0	0
T13	585144	1642	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7649843	0	0
T1	169824	460	0	0
T2	8030232	23274	0	0
T3	7613328	29711	0	0
T7	4698168	21267	0	0
T8	303912	883	0	0
T9	44856	486	0	0
T10	2489904	10596	0	0
T11	3381792	4861	0	0
T12	6819432	425	0	0
T13	585144	1642	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34497266	0	0
T1	169824	883	0	0
T2	8030232	97316	0	0
T3	7613328	97795	0	0
T7	4698168	46949	0	0
T8	303912	1780	0	0
T9	44856	550	0	0
T10	2489904	37326	0	0
T11	3381792	8180	0	0
T12	6819432	724	0	0
T13	585144	3697	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	40589	0	21600
T2	669186	19	0	2
T3	634444	12	0	2
T4	0	1	0	0
T7	391514	3	0	2
T8	25326	0	0	2
T9	3738	0	0	2
T10	207492	3	0	2
T11	281816	0	0	2
T12	568286	0	0	2
T13	48762	1	0	2
T14	0	9	0	0
T15	0	18	0	0
T16	0	2	0	0
T17	0	422	0	0
T18	0	18	0	0
T19	0	26	0	0
T20	1119426	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	169824	168864	0	0
T2	8030232	8025192	0	0
T3	7613328	7585080	0	0
T7	4698168	4688472	0	0
T8	303912	301944	0	0
T9	44856	44232	0	0
T10	2489904	2489544	0	0
T11	3381792	3381696	0	0
T12	6819432	6818256	0	0
T13	585144	583656	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7649843	0	0
T1	169824	460	0	0
T2	8030232	23274	0	0
T3	7613328	29711	0	0
T7	4698168	21267	0	0
T8	303912	883	0	0
T9	44856	486	0	0
T10	2489904	10596	0	0
T11	3381792	4861	0	0
T12	6819432	425	0	0
T13	585144	1642	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	859303	0	0
GntImpliesValid_A	433802600	859303	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	859303	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	12447738	0	0
ReadyAndValidImplyGrant_A	433802600	859303	0	0
ReqAndReadyImplyGrant_A	433802600	859303	0	0
ReqImpliesValid_A	433802600	2522724	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	859303	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	859303	0	0
T1	7076	54	0	0
T2	334593	3468	0	0
T3	317222	2892	0	0
T7	195757	2332	0	0
T8	12663	97	0	0
T9	1869	43	0	0
T10	103746	1710	0	0
T11	140908	562	0	0
T12	284143	45	0	0
T13	24381	180	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	859303	0	0
T1	7076	54	0	0
T2	334593	3468	0	0
T3	317222	2892	0	0
T7	195757	2332	0	0
T8	12663	97	0	0
T9	1869	43	0	0
T10	103746	1710	0	0
T11	140908	562	0	0
T12	284143	45	0	0
T13	24381	180	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	859303	0	0
T1	7076	54	0	0
T2	334593	3468	0	0
T3	317222	2892	0	0
T7	195757	2332	0	0
T8	12663	97	0	0
T9	1869	43	0	0
T10	103746	1710	0	0
T11	140908	562	0	0
T12	284143	45	0	0
T13	24381	180	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	12447738	0	0
T1	7076	448	0	0
T2	334593	19434	0	0
T3	317222	21367	0	0
T7	195757	16121	0	0
T8	12663	632	0	0
T9	1869	37	0	0
T10	103746	10751	0	0
T11	140908	2387	0	0
T12	284143	165	0	0
T13	24381	1415	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	859303	0	0
T1	7076	54	0	0
T2	334593	3468	0	0
T3	317222	2892	0	0
T7	195757	2332	0	0
T8	12663	97	0	0
T9	1869	43	0	0
T10	103746	1710	0	0
T11	140908	562	0	0
T12	284143	45	0	0
T13	24381	180	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	859303	0	0
T1	7076	54	0	0
T2	334593	3468	0	0
T3	317222	2892	0	0
T7	195757	2332	0	0
T8	12663	97	0	0
T9	1869	43	0	0
T10	103746	1710	0	0
T11	140908	562	0	0
T12	284143	45	0	0
T13	24381	180	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	2522724	0	0
T1	7076	80	0	0
T2	334593	7853	0	0
T3	317222	4437	0	0
T7	195757	3777	0	0
T8	12663	118	0	0
T9	1869	50	0	0
T10	103746	5886	0	0
T11	140908	760	0	0
T12	284143	76	0	0
T13	24381	236	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	859303	0	0
T1	7076	54	0	0
T2	334593	3468	0	0
T3	317222	2892	0	0
T7	195757	2332	0	0
T8	12663	97	0	0
T9	1869	43	0	0
T10	103746	1710	0	0
T11	140908	562	0	0
T12	284143	45	0	0
T13	24381	180	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	840422	0	0
GntImpliesValid_A	433802600	840422	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	840422	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	12388193	0	0
ReadyAndValidImplyGrant_A	433802600	840422	0	0
ReqAndReadyImplyGrant_A	433802600	840422	0	0
ReqImpliesValid_A	433802600	2454993	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	840422	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	840422	0	0
T1	7076	55	0	0
T2	334593	1982	0	0
T3	317222	3563	0	0
T7	195757	2331	0	0
T8	12663	87	0	0
T9	1869	60	0	0
T10	103746	912	0	0
T11	140908	558	0	0
T12	284143	56	0	0
T13	24381	172	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	840422	0	0
T1	7076	55	0	0
T2	334593	1982	0	0
T3	317222	3563	0	0
T7	195757	2331	0	0
T8	12663	87	0	0
T9	1869	60	0	0
T10	103746	912	0	0
T11	140908	558	0	0
T12	284143	56	0	0
T13	24381	172	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	840422	0	0
T1	7076	55	0	0
T2	334593	1982	0	0
T3	317222	3563	0	0
T7	195757	2331	0	0
T8	12663	87	0	0
T9	1869	60	0	0
T10	103746	912	0	0
T11	140908	558	0	0
T12	284143	56	0	0
T13	24381	172	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	12388193	0	0
T1	7076	371	0	0
T2	334593	14933	0	0
T3	317222	22010	0	0
T7	195757	17382	0	0
T8	12663	615	0	0
T9	1869	44	0	0
T10	103746	6828	0	0
T11	140908	2335	0	0
T12	284143	230	0	0
T13	24381	1252	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	840422	0	0
T1	7076	55	0	0
T2	334593	1982	0	0
T3	317222	3563	0	0
T7	195757	2331	0	0
T8	12663	87	0	0
T9	1869	60	0	0
T10	103746	912	0	0
T11	140908	558	0	0
T12	284143	56	0	0
T13	24381	172	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	840422	0	0
T1	7076	55	0	0
T2	334593	1982	0	0
T3	317222	3563	0	0
T7	195757	2331	0	0
T8	12663	87	0	0
T9	1869	60	0	0
T10	103746	912	0	0
T11	140908	558	0	0
T12	284143	56	0	0
T13	24381	172	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	2454993	0	0
T1	7076	86	0	0
T2	334593	2836	0	0
T3	317222	6858	0	0
T7	195757	3785	0	0
T8	12663	124	0	0
T9	1869	77	0	0
T10	103746	1450	0	0
T11	140908	720	0	0
T12	284143	90	0	0
T13	24381	309	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	840422	0	0
T1	7076	55	0	0
T2	334593	1982	0	0
T3	317222	3563	0	0
T7	195757	2331	0	0
T8	12663	87	0	0
T9	1869	60	0	0
T10	103746	912	0	0
T11	140908	558	0	0
T12	284143	56	0	0
T13	24381	172	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	221481	0	0
GntImpliesValid_A	433802600	221481	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	221481	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	3133938	0	0
ReadyAndValidImplyGrant_A	433802600	221481	0	0
ReqAndReadyImplyGrant_A	433802600	221481	0	0
ReqImpliesValid_A	433802600	594509	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	221481	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	221481	0	0
T1	7076	9	0	0
T2	334593	264	0	0
T3	317222	989	0	0
T7	195757	811	0	0
T8	12663	27	0	0
T9	1869	7	0	0
T10	103746	168	0	0
T11	140908	117	0	0
T12	284143	10	0	0
T13	24381	48	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	221481	0	0
T1	7076	9	0	0
T2	334593	264	0	0
T3	317222	989	0	0
T7	195757	811	0	0
T8	12663	27	0	0
T9	1869	7	0	0
T10	103746	168	0	0
T11	140908	117	0	0
T12	284143	10	0	0
T13	24381	48	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	221481	0	0
T1	7076	9	0	0
T2	334593	264	0	0
T3	317222	989	0	0
T7	195757	811	0	0
T8	12663	27	0	0
T9	1869	7	0	0
T10	103746	168	0	0
T11	140908	117	0	0
T12	284143	10	0	0
T13	24381	48	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	3133938	0	0
T1	7076	68	0	0
T2	334593	1956	0	0
T3	317222	5970	0	0
T7	195757	4625	0	0
T8	12663	211	0	0
T9	1869	8	0	0
T10	103746	1333	0	0
T11	140908	505	0	0
T12	284143	38	0	0
T13	24381	439	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	221481	0	0
T1	7076	9	0	0
T2	334593	264	0	0
T3	317222	989	0	0
T7	195757	811	0	0
T8	12663	27	0	0
T9	1869	7	0	0
T10	103746	168	0	0
T11	140908	117	0	0
T12	284143	10	0	0
T13	24381	48	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	221481	0	0
T1	7076	9	0	0
T2	334593	264	0	0
T3	317222	989	0	0
T7	195757	811	0	0
T8	12663	27	0	0
T9	1869	7	0	0
T10	103746	168	0	0
T11	140908	117	0	0
T12	284143	10	0	0
T13	24381	48	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	594509	0	0
T1	7076	9	0	0
T2	334593	289	0	0
T3	317222	1979	0	0
T7	195757	1724	0	0
T8	12663	36	0	0
T9	1869	7	0	0
T10	103746	220	0	0
T11	140908	137	0	0
T12	284143	10	0	0
T13	24381	89	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	221481	0	0
T1	7076	9	0	0
T2	334593	264	0	0
T3	317222	989	0	0
T7	195757	811	0	0
T8	12663	27	0	0
T9	1869	7	0	0
T10	103746	168	0	0
T11	140908	117	0	0
T12	284143	10	0	0
T13	24381	48	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	213828	0	0
GntImpliesValid_A	433802600	213828	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	213828	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	3072120	0	0
ReadyAndValidImplyGrant_A	433802600	213828	0	0
ReqAndReadyImplyGrant_A	433802600	213828	0	0
ReqImpliesValid_A	433802600	562179	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	213828	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	213828	0	0
T1	7076	14	0	0
T2	334593	300	0	0
T3	317222	1249	0	0
T7	195757	575	0	0
T8	12663	17	0	0
T9	1869	9	0	0
T10	103746	140	0	0
T11	140908	111	0	0
T12	284143	10	0	0
T13	24381	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	213828	0	0
T1	7076	14	0	0
T2	334593	300	0	0
T3	317222	1249	0	0
T7	195757	575	0	0
T8	12663	17	0	0
T9	1869	9	0	0
T10	103746	140	0	0
T11	140908	111	0	0
T12	284143	10	0	0
T13	24381	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	213828	0	0
T1	7076	14	0	0
T2	334593	300	0	0
T3	317222	1249	0	0
T7	195757	575	0	0
T8	12663	17	0	0
T9	1869	9	0	0
T10	103746	140	0	0
T11	140908	111	0	0
T12	284143	10	0	0
T13	24381	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	3072120	0	0
T1	7076	97	0	0
T2	334593	2209	0	0
T3	317222	7159	0	0
T7	195757	4580	0	0
T8	12663	154	0	0
T9	1869	10	0	0
T10	103746	1038	0	0
T11	140908	438	0	0
T12	284143	35	0	0
T13	24381	312	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	213828	0	0
T1	7076	14	0	0
T2	334593	300	0	0
T3	317222	1249	0	0
T7	195757	575	0	0
T8	12663	17	0	0
T9	1869	9	0	0
T10	103746	140	0	0
T11	140908	111	0	0
T12	284143	10	0	0
T13	24381	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	213828	0	0
T1	7076	14	0	0
T2	334593	300	0	0
T3	317222	1249	0	0
T7	195757	575	0	0
T8	12663	17	0	0
T9	1869	9	0	0
T10	103746	140	0	0
T11	140908	111	0	0
T12	284143	10	0	0
T13	24381	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	562179	0	0
T1	7076	16	0	0
T2	334593	338	0	0
T3	317222	5187	0	0
T7	195757	647	0	0
T8	12663	24	0	0
T9	1869	9	0	0
T10	103746	203	0	0
T11	140908	127	0	0
T12	284143	10	0	0
T13	24381	55	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	213828	0	0
T1	7076	14	0	0
T2	334593	300	0	0
T3	317222	1249	0	0
T7	195757	575	0	0
T8	12663	17	0	0
T9	1869	9	0	0
T10	103746	140	0	0
T11	140908	111	0	0
T12	284143	10	0	0
T13	24381	40	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	215694	0	0
GntImpliesValid_A	433802600	215694	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	215694	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	5731046	0	0
ReadyAndValidImplyGrant_A	433802600	215694	0	0
ReqAndReadyImplyGrant_A	433802600	215694	0	0
ReqImpliesValid_A	433802600	1209737	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	215694	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	215694	0	0
T1	7076	13	0	0
T2	334593	550	0	0
T3	317222	475	0	0
T7	195757	621	0	0
T8	12663	26	0	0
T9	1869	11	0	0
T10	103746	167	0	0
T11	140908	140	0	0
T12	284143	9	0	0
T13	24381	42	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	215694	0	0
T1	7076	13	0	0
T2	334593	550	0	0
T3	317222	475	0	0
T7	195757	621	0	0
T8	12663	26	0	0
T9	1869	11	0	0
T10	103746	167	0	0
T11	140908	140	0	0
T12	284143	9	0	0
T13	24381	42	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	215694	0	0
T1	7076	13	0	0
T2	334593	550	0	0
T3	317222	475	0	0
T7	195757	621	0	0
T8	12663	26	0	0
T9	1869	11	0	0
T10	103746	167	0	0
T11	140908	140	0	0
T12	284143	9	0	0
T13	24381	42	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	5731046	0	0
T1	7076	172	0	0
T2	334593	18900	0	0
T3	317222	8917	0	0
T7	195757	4813	0	0
T8	12663	683	0	0
T9	1869	36	0	0
T10	103746	859	0	0
T11	140908	1462	0	0
T12	284143	146	0	0
T13	24381	966	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	215694	0	0
T1	7076	13	0	0
T2	334593	550	0	0
T3	317222	475	0	0
T7	195757	621	0	0
T8	12663	26	0	0
T9	1869	11	0	0
T10	103746	167	0	0
T11	140908	140	0	0
T12	284143	9	0	0
T13	24381	42	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	215694	0	0
T1	7076	13	0	0
T2	334593	550	0	0
T3	317222	475	0	0
T7	195757	621	0	0
T8	12663	26	0	0
T9	1869	11	0	0
T10	103746	167	0	0
T11	140908	140	0	0
T12	284143	9	0	0
T13	24381	42	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	1209737	0	0
T1	7076	25	0	0
T2	334593	14303	0	0
T3	317222	664	0	0
T7	195757	745	0	0
T8	12663	80	0	0
T9	1869	11	0	0
T10	103746	180	0	0
T11	140908	257	0	0
T12	284143	9	0	0
T13	24381	144	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	215694	0	0
T1	7076	13	0	0
T2	334593	550	0	0
T3	317222	475	0	0
T7	195757	621	0	0
T8	12663	26	0	0
T9	1869	11	0	0
T10	103746	167	0	0
T11	140908	140	0	0
T12	284143	9	0	0
T13	24381	42	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	207689	0	0
GntImpliesValid_A	433802600	207689	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	207689	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	5377630	0	0
ReadyAndValidImplyGrant_A	433802600	207689	0	0
ReqAndReadyImplyGrant_A	433802600	207689	0	0
ReqImpliesValid_A	433802600	1353758	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	207689	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	207689	0	0
T1	7076	7	0	0
T2	334593	276	0	0
T3	317222	2069	0	0
T7	195757	564	0	0
T8	12663	42	0	0
T9	1869	13	0	0
T10	103746	154	0	0
T11	140908	140	0	0
T12	284143	11	0	0
T13	24381	35	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	207689	0	0
T1	7076	7	0	0
T2	334593	276	0	0
T3	317222	2069	0	0
T7	195757	564	0	0
T8	12663	42	0	0
T9	1869	13	0	0
T10	103746	154	0	0
T11	140908	140	0	0
T12	284143	11	0	0
T13	24381	35	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	207689	0	0
T1	7076	7	0	0
T2	334593	276	0	0
T3	317222	2069	0	0
T7	195757	564	0	0
T8	12663	42	0	0
T9	1869	13	0	0
T10	103746	154	0	0
T11	140908	140	0	0
T12	284143	11	0	0
T13	24381	35	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	5377630	0	0
T1	7076	133	0	0
T2	334593	5123	0	0
T3	317222	31142	0	0
T7	195757	6205	0	0
T8	12663	423	0	0
T9	1869	45	0	0
T10	103746	1043	0	0
T11	140908	1120	0	0
T12	284143	161	0	0
T13	24381	396	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	207689	0	0
T1	7076	7	0	0
T2	334593	276	0	0
T3	317222	2069	0	0
T7	195757	564	0	0
T8	12663	42	0	0
T9	1869	13	0	0
T10	103746	154	0	0
T11	140908	140	0	0
T12	284143	11	0	0
T13	24381	35	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	207689	0	0
T1	7076	7	0	0
T2	334593	276	0	0
T3	317222	2069	0	0
T7	195757	564	0	0
T8	12663	42	0	0
T9	1869	13	0	0
T10	103746	154	0	0
T11	140908	140	0	0
T12	284143	11	0	0
T13	24381	35	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	1353758	0	0
T1	7076	7	0	0
T2	334593	419	0	0
T3	317222	13647	0	0
T7	195757	768	0	0
T8	12663	62	0	0
T9	1869	13	0	0
T10	103746	202	0	0
T11	140908	250	0	0
T12	284143	22	0	0
T13	24381	59	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	207689	0	0
T1	7076	7	0	0
T2	334593	276	0	0
T3	317222	2069	0	0
T7	195757	564	0	0
T8	12663	42	0	0
T9	1869	13	0	0
T10	103746	154	0	0
T11	140908	140	0	0
T12	284143	11	0	0
T13	24381	35	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	204032	0	0
GntImpliesValid_A	433802600	204032	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	204032	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	5676039	0	0
ReadyAndValidImplyGrant_A	433802600	204032	0	0
ReqAndReadyImplyGrant_A	433802600	204032	0	0
ReqImpliesValid_A	433802600	1100787	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	204032	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	204032	0	0
T1	7076	11	0	0
T2	334593	681	0	0
T3	317222	1161	0	0
T7	195757	547	0	0
T8	12663	24	0	0
T9	1869	16	0	0
T10	103746	659	0	0
T11	140908	153	0	0
T12	284143	6	0	0
T13	24381	50	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	204032	0	0
T1	7076	11	0	0
T2	334593	681	0	0
T3	317222	1161	0	0
T7	195757	547	0	0
T8	12663	24	0	0
T9	1869	16	0	0
T10	103746	659	0	0
T11	140908	153	0	0
T12	284143	6	0	0
T13	24381	50	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	204032	0	0
T1	7076	11	0	0
T2	334593	681	0	0
T3	317222	1161	0	0
T7	195757	547	0	0
T8	12663	24	0	0
T9	1869	16	0	0
T10	103746	659	0	0
T11	140908	153	0	0
T12	284143	6	0	0
T13	24381	50	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	5676039	0	0
T1	7076	113	0	0
T2	334593	20525	0	0
T3	317222	18709	0	0
T7	195757	5944	0	0
T8	12663	521	0	0
T9	1869	54	0	0
T10	103746	2563	0	0
T11	140908	1272	0	0
T12	284143	70	0	0
T13	24381	558	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	204032	0	0
T1	7076	11	0	0
T2	334593	681	0	0
T3	317222	1161	0	0
T7	195757	547	0	0
T8	12663	24	0	0
T9	1869	16	0	0
T10	103746	659	0	0
T11	140908	153	0	0
T12	284143	6	0	0
T13	24381	50	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	204032	0	0
T1	7076	11	0	0
T2	334593	681	0	0
T3	317222	1161	0	0
T7	195757	547	0	0
T8	12663	24	0	0
T9	1869	16	0	0
T10	103746	659	0	0
T11	140908	153	0	0
T12	284143	6	0	0
T13	24381	50	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	1100787	0	0
T1	7076	25	0	0
T2	334593	7232	0	0
T3	317222	5204	0	0
T7	195757	709	0	0
T8	12663	63	0	0
T9	1869	28	0	0
T10	103746	1862	0	0
T11	140908	246	0	0
T12	284143	18	0	0
T13	24381	81	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	204032	0	0
T1	7076	11	0	0
T2	334593	681	0	0
T3	317222	1161	0	0
T7	195757	547	0	0
T8	12663	24	0	0
T9	1869	16	0	0
T10	103746	659	0	0
T11	140908	153	0	0
T12	284143	6	0	0
T13	24381	50	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	207326	0	0
GntImpliesValid_A	433802600	207326	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	207326	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	5728109	0	0
ReadyAndValidImplyGrant_A	433802600	207326	0	0
ReqAndReadyImplyGrant_A	433802600	207326	0	0
ReqImpliesValid_A	433802600	1224667	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	207326	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	207326	0	0
T1	7076	13	0	0
T2	334593	271	0	0
T3	317222	988	0	0
T7	195757	598	0	0
T8	12663	27	0	0
T9	1869	22	0	0
T10	103746	153	0	0
T11	140908	134	0	0
T12	284143	11	0	0
T13	24381	41	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	207326	0	0
T1	7076	13	0	0
T2	334593	271	0	0
T3	317222	988	0	0
T7	195757	598	0	0
T8	12663	27	0	0
T9	1869	22	0	0
T10	103746	153	0	0
T11	140908	134	0	0
T12	284143	11	0	0
T13	24381	41	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	207326	0	0
T1	7076	13	0	0
T2	334593	271	0	0
T3	317222	988	0	0
T7	195757	598	0	0
T8	12663	27	0	0
T9	1869	22	0	0
T10	103746	153	0	0
T11	140908	134	0	0
T12	284143	11	0	0
T13	24381	41	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	5728109	0	0
T1	7076	93	0	0
T2	334593	3118	0	0
T3	317222	19484	0	0
T7	195757	5232	0	0
T8	12663	437	0	0
T9	1869	60	0	0
T10	103746	2147	0	0
T11	140908	1719	0	0
T12	284143	97	0	0
T13	24381	703	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	207326	0	0
T1	7076	13	0	0
T2	334593	271	0	0
T3	317222	988	0	0
T7	195757	598	0	0
T8	12663	27	0	0
T9	1869	22	0	0
T10	103746	153	0	0
T11	140908	134	0	0
T12	284143	11	0	0
T13	24381	41	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	207326	0	0
T1	7076	13	0	0
T2	334593	271	0	0
T3	317222	988	0	0
T7	195757	598	0	0
T8	12663	27	0	0
T9	1869	22	0	0
T10	103746	153	0	0
T11	140908	134	0	0
T12	284143	11	0	0
T13	24381	41	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	1224667	0	0
T1	7076	23	0	0
T2	334593	329	0	0
T3	317222	6452	0	0
T7	195757	749	0	0
T8	12663	46	0	0
T9	1869	42	0	0
T10	103746	235	0	0
T11	140908	281	0	0
T12	284143	29	0	0
T13	24381	119	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	207326	0	0
T1	7076	13	0	0
T2	334593	271	0	0
T3	317222	988	0	0
T7	195757	598	0	0
T8	12663	27	0	0
T9	1869	22	0	0
T10	103746	153	0	0
T11	140908	134	0	0
T12	284143	11	0	0
T13	24381	41	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	213007	0	0
GntImpliesValid_A	433802600	213007	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	213007	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	3123492	0	0
ReadyAndValidImplyGrant_A	433802600	213007	0	0
ReqAndReadyImplyGrant_A	433802600	213007	0	0
ReqImpliesValid_A	433802600	571475	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	213007	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	213007	0	0
T1	7076	20	0	0
T2	334593	316	0	0
T3	317222	515	0	0
T7	195757	553	0	0
T8	12663	27	0	0
T9	1869	10	0	0
T10	103746	588	0	0
T11	140908	130	0	0
T12	284143	12	0	0
T13	24381	41	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	213007	0	0
T1	7076	20	0	0
T2	334593	316	0	0
T3	317222	515	0	0
T7	195757	553	0	0
T8	12663	27	0	0
T9	1869	10	0	0
T10	103746	588	0	0
T11	140908	130	0	0
T12	284143	12	0	0
T13	24381	41	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	213007	0	0
T1	7076	20	0	0
T2	334593	316	0	0
T3	317222	515	0	0
T7	195757	553	0	0
T8	12663	27	0	0
T9	1869	10	0	0
T10	103746	588	0	0
T11	140908	130	0	0
T12	284143	12	0	0
T13	24381	41	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	3123492	0	0
T1	7076	140	0	0
T2	334593	2502	0	0
T3	317222	3990	0	0
T7	195757	4046	0	0
T8	12663	246	0	0
T9	1869	11	0	0
T10	103746	2137	0	0
T11	140908	501	0	0
T12	284143	54	0	0
T13	24381	388	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	213007	0	0
T1	7076	20	0	0
T2	334593	316	0	0
T3	317222	515	0	0
T7	195757	553	0	0
T8	12663	27	0	0
T9	1869	10	0	0
T10	103746	588	0	0
T11	140908	130	0	0
T12	284143	12	0	0
T13	24381	41	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	213007	0	0
T1	7076	20	0	0
T2	334593	316	0	0
T3	317222	515	0	0
T7	195757	553	0	0
T8	12663	27	0	0
T9	1869	10	0	0
T10	103746	588	0	0
T11	140908	130	0	0
T12	284143	12	0	0
T13	24381	41	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	571475	0	0
T1	7076	34	0	0
T2	334593	332	0	0
T3	317222	581	0	0
T7	195757	683	0	0
T8	12663	27	0	0
T9	1869	10	0	0
T10	103746	3829	0	0
T11	140908	167	0	0
T12	284143	16	0	0
T13	24381	57	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	213007	0	0
T1	7076	20	0	0
T2	334593	316	0	0
T3	317222	515	0	0
T7	195757	553	0	0
T8	12663	27	0	0
T9	1869	10	0	0
T10	103746	588	0	0
T11	140908	130	0	0
T12	284143	12	0	0
T13	24381	41	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	220198	0	0
GntImpliesValid_A	433802600	220198	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	220198	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	3065972	0	0
ReadyAndValidImplyGrant_A	433802600	220198	0	0
ReqAndReadyImplyGrant_A	433802600	220198	0	0
ReqImpliesValid_A	433802600	553794	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	220198	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	220198	0	0
T1	7076	8	0	0
T2	334593	1157	0	0
T3	317222	485	0	0
T7	195757	534	0	0
T8	12663	26	0	0
T9	1869	13	0	0
T10	103746	581	0	0
T11	140908	139	0	0
T12	284143	9	0	0
T13	24381	44	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	220198	0	0
T1	7076	8	0	0
T2	334593	1157	0	0
T3	317222	485	0	0
T7	195757	534	0	0
T8	12663	26	0	0
T9	1869	13	0	0
T10	103746	581	0	0
T11	140908	139	0	0
T12	284143	9	0	0
T13	24381	44	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	220198	0	0
T1	7076	8	0	0
T2	334593	1157	0	0
T3	317222	485	0	0
T7	195757	534	0	0
T8	12663	26	0	0
T9	1869	13	0	0
T10	103746	581	0	0
T11	140908	139	0	0
T12	284143	9	0	0
T13	24381	44	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	3065972	0	0
T1	7076	48	0	0
T2	334593	6291	0	0
T3	317222	3624	0	0
T7	195757	4145	0	0
T8	12663	145	0	0
T9	1869	14	0	0
T10	103746	3722	0	0
T11	140908	582	0	0
T12	284143	43	0	0
T13	24381	379	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	220198	0	0
T1	7076	8	0	0
T2	334593	1157	0	0
T3	317222	485	0	0
T7	195757	534	0	0
T8	12663	26	0	0
T9	1869	13	0	0
T10	103746	581	0	0
T11	140908	139	0	0
T12	284143	9	0	0
T13	24381	44	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	220198	0	0
T1	7076	8	0	0
T2	334593	1157	0	0
T3	317222	485	0	0
T7	195757	534	0	0
T8	12663	26	0	0
T9	1869	13	0	0
T10	103746	581	0	0
T11	140908	139	0	0
T12	284143	9	0	0
T13	24381	44	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	553794	0	0
T1	7076	8	0	0
T2	334593	5184	0	0
T3	317222	551	0	0
T7	195757	582	0	0
T8	12663	39	0	0
T9	1869	13	0	0
T10	103746	1768	0	0
T11	140908	165	0	0
T12	284143	9	0	0
T13	24381	57	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	220198	0	0
T1	7076	8	0	0
T2	334593	1157	0	0
T3	317222	485	0	0
T7	195757	534	0	0
T8	12663	26	0	0
T9	1869	13	0	0
T10	103746	581	0	0
T11	140908	139	0	0
T12	284143	9	0	0
T13	24381	44	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	206129	0	0
GntImpliesValid_A	433802600	206129	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	206129	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	3033177	0	0
ReadyAndValidImplyGrant_A	433802600	206129	0	0
ReqAndReadyImplyGrant_A	433802600	206129	0	0
ReqImpliesValid_A	433802600	515175	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	206129	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	206129	0	0
T1	7076	17	0	0
T2	334593	265	0	0
T3	317222	1010	0	0
T7	195757	514	0	0
T8	12663	23	0	0
T9	1869	9	0	0
T10	103746	177	0	0
T11	140908	137	0	0
T12	284143	9	0	0
T13	24381	42	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	206129	0	0
T1	7076	17	0	0
T2	334593	265	0	0
T3	317222	1010	0	0
T7	195757	514	0	0
T8	12663	23	0	0
T9	1869	9	0	0
T10	103746	177	0	0
T11	140908	137	0	0
T12	284143	9	0	0
T13	24381	42	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	206129	0	0
T1	7076	17	0	0
T2	334593	265	0	0
T3	317222	1010	0	0
T7	195757	514	0	0
T8	12663	23	0	0
T9	1869	9	0	0
T10	103746	177	0	0
T11	140908	137	0	0
T12	284143	9	0	0
T13	24381	42	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	3033177	0	0
T1	7076	133	0	0
T2	334593	2024	0	0
T3	317222	7107	0	0
T7	195757	4103	0	0
T8	12663	148	0	0
T9	1869	10	0	0
T10	103746	1339	0	0
T11	140908	549	0	0
T12	284143	38	0	0
T13	24381	355	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	206129	0	0
T1	7076	17	0	0
T2	334593	265	0	0
T3	317222	1010	0	0
T7	195757	514	0	0
T8	12663	23	0	0
T9	1869	9	0	0
T10	103746	177	0	0
T11	140908	137	0	0
T12	284143	9	0	0
T13	24381	42	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	206129	0	0
T1	7076	17	0	0
T2	334593	265	0	0
T3	317222	1010	0	0
T7	195757	514	0	0
T8	12663	23	0	0
T9	1869	9	0	0
T10	103746	177	0	0
T11	140908	137	0	0
T12	284143	9	0	0
T13	24381	42	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	515175	0	0
T1	7076	17	0	0
T2	334593	295	0	0
T3	317222	2273	0	0
T7	195757	621	0	0
T8	12663	25	0	0
T9	1869	9	0	0
T10	103746	226	0	0
T11	140908	175	0	0
T12	284143	11	0	0
T13	24381	43	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	206129	0	0
T1	7076	17	0	0
T2	334593	265	0	0
T3	317222	1010	0	0
T7	195757	514	0	0
T8	12663	23	0	0
T9	1869	9	0	0
T10	103746	177	0	0
T11	140908	137	0	0
T12	284143	9	0	0
T13	24381	42	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	207741	0	0
GntImpliesValid_A	433802600	207741	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	207741	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	3010255	0	0
ReadyAndValidImplyGrant_A	433802600	207741	0	0
ReqAndReadyImplyGrant_A	433802600	207741	0	0
ReqImpliesValid_A	433802600	564955	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	207741	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	207741	0	0
T1	7076	16	0	0
T2	334593	809	0	0
T3	317222	486	0	0
T7	195757	583	0	0
T8	12663	22	0	0
T9	1869	12	0	0
T10	103746	665	0	0
T11	140908	122	0	0
T12	284143	11	0	0
T13	24381	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	207741	0	0
T1	7076	16	0	0
T2	334593	809	0	0
T3	317222	486	0	0
T7	195757	583	0	0
T8	12663	22	0	0
T9	1869	12	0	0
T10	103746	665	0	0
T11	140908	122	0	0
T12	284143	11	0	0
T13	24381	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	207741	0	0
T1	7076	16	0	0
T2	334593	809	0	0
T3	317222	486	0	0
T7	195757	583	0	0
T8	12663	22	0	0
T9	1869	12	0	0
T10	103746	665	0	0
T11	140908	122	0	0
T12	284143	11	0	0
T13	24381	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	3010255	0	0
T1	7076	123	0	0
T2	334593	5352	0	0
T3	317222	3480	0	0
T7	195757	4324	0	0
T8	12663	174	0	0
T9	1869	12	0	0
T10	103746	3808	0	0
T11	140908	555	0	0
T12	284143	42	0	0
T13	24381	272	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	207741	0	0
T1	7076	16	0	0
T2	334593	809	0	0
T3	317222	486	0	0
T7	195757	583	0	0
T8	12663	22	0	0
T9	1869	12	0	0
T10	103746	665	0	0
T11	140908	122	0	0
T12	284143	11	0	0
T13	24381	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	207741	0	0
T1	7076	16	0	0
T2	334593	809	0	0
T3	317222	486	0	0
T7	195757	583	0	0
T8	12663	22	0	0
T9	1869	12	0	0
T10	103746	665	0	0
T11	140908	122	0	0
T12	284143	11	0	0
T13	24381	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	564955	0	0
T1	7076	17	0	0
T2	334593	1523	0	0
T3	317222	549	0	0
T7	195757	733	0	0
T8	12663	22	0	0
T9	1869	13	0	0
T10	103746	2731	0	0
T11	140908	146	0	0
T12	284143	11	0	0
T13	24381	62	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	207741	0	0
T1	7076	16	0	0
T2	334593	809	0	0
T3	317222	486	0	0
T7	195757	583	0	0
T8	12663	22	0	0
T9	1869	12	0	0
T10	103746	665	0	0
T11	140908	122	0	0
T12	284143	11	0	0
T13	24381	40	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	211501	0	0
GntImpliesValid_A	433802600	211501	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	211501	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	3026140	0	0
ReadyAndValidImplyGrant_A	433802600	211501	0	0
ReqAndReadyImplyGrant_A	433802600	211501	0	0
ReqImpliesValid_A	433802600	522440	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	211501	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	211501	0	0
T1	7076	9	0	0
T2	334593	283	0	0
T3	317222	1083	0	0
T7	195757	600	0	0
T8	12663	23	0	0
T9	1869	14	0	0
T10	103746	158	0	0
T11	140908	105	0	0
T12	284143	14	0	0
T13	24381	48	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	211501	0	0
T1	7076	9	0	0
T2	334593	283	0	0
T3	317222	1083	0	0
T7	195757	600	0	0
T8	12663	23	0	0
T9	1869	14	0	0
T10	103746	158	0	0
T11	140908	105	0	0
T12	284143	14	0	0
T13	24381	48	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	211501	0	0
T1	7076	9	0	0
T2	334593	283	0	0
T3	317222	1083	0	0
T7	195757	600	0	0
T8	12663	23	0	0
T9	1869	14	0	0
T10	103746	158	0	0
T11	140908	105	0	0
T12	284143	14	0	0
T13	24381	48	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	3026140	0	0
T1	7076	62	0	0
T2	334593	2197	0	0
T3	317222	7843	0	0
T7	195757	4519	0	0
T8	12663	159	0	0
T9	1869	15	0	0
T10	103746	1212	0	0
T11	140908	465	0	0
T12	284143	58	0	0
T13	24381	456	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	211501	0	0
T1	7076	9	0	0
T2	334593	283	0	0
T3	317222	1083	0	0
T7	195757	600	0	0
T8	12663	23	0	0
T9	1869	14	0	0
T10	103746	158	0	0
T11	140908	105	0	0
T12	284143	14	0	0
T13	24381	48	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	211501	0	0
T1	7076	9	0	0
T2	334593	283	0	0
T3	317222	1083	0	0
T7	195757	600	0	0
T8	12663	23	0	0
T9	1869	14	0	0
T10	103746	158	0	0
T11	140908	105	0	0
T12	284143	14	0	0
T13	24381	48	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	522440	0	0
T1	7076	9	0	0
T2	334593	312	0	0
T3	317222	2550	0	0
T7	195757	765	0	0
T8	12663	36	0	0
T9	1869	14	0	0
T10	103746	190	0	0
T11	140908	119	0	0
T12	284143	14	0	0
T13	24381	63	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	211501	0	0
T1	7076	9	0	0
T2	334593	283	0	0
T3	317222	1083	0	0
T7	195757	600	0	0
T8	12663	23	0	0
T9	1869	14	0	0
T10	103746	158	0	0
T11	140908	105	0	0
T12	284143	14	0	0
T13	24381	48	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	209166	0	0
GntImpliesValid_A	433802600	209166	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	209166	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	3041262	0	0
ReadyAndValidImplyGrant_A	433802600	209166	0	0
ReqAndReadyImplyGrant_A	433802600	209166	0	0
ReqImpliesValid_A	433802600	546955	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	209166	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	209166	0	0
T1	7076	10	0	0
T2	334593	304	0	0
T3	317222	921	0	0
T7	195757	571	0	0
T8	12663	31	0	0
T9	1869	14	0	0
T10	103746	131	0	0
T11	140908	149	0	0
T12	284143	9	0	0
T13	24381	46	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	209166	0	0
T1	7076	10	0	0
T2	334593	304	0	0
T3	317222	921	0	0
T7	195757	571	0	0
T8	12663	31	0	0
T9	1869	14	0	0
T10	103746	131	0	0
T11	140908	149	0	0
T12	284143	9	0	0
T13	24381	46	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	209166	0	0
T1	7076	10	0	0
T2	334593	304	0	0
T3	317222	921	0	0
T7	195757	571	0	0
T8	12663	31	0	0
T9	1869	14	0	0
T10	103746	131	0	0
T11	140908	149	0	0
T12	284143	9	0	0
T13	24381	46	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	3041262	0	0
T1	7076	60	0	0
T2	334593	2370	0	0
T3	317222	5712	0	0
T7	195757	4370	0	0
T8	12663	227	0	0
T9	1869	15	0	0
T10	103746	877	0	0
T11	140908	596	0	0
T12	284143	34	0	0
T13	24381	311	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	209166	0	0
T1	7076	10	0	0
T2	334593	304	0	0
T3	317222	921	0	0
T7	195757	571	0	0
T8	12663	31	0	0
T9	1869	14	0	0
T10	103746	131	0	0
T11	140908	149	0	0
T12	284143	9	0	0
T13	24381	46	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	209166	0	0
T1	7076	10	0	0
T2	334593	304	0	0
T3	317222	921	0	0
T7	195757	571	0	0
T8	12663	31	0	0
T9	1869	14	0	0
T10	103746	131	0	0
T11	140908	149	0	0
T12	284143	9	0	0
T13	24381	46	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	546955	0	0
T1	7076	10	0	0
T2	334593	331	0	0
T3	317222	1686	0	0
T7	195757	704	0	0
T8	12663	59	0	0
T9	1869	14	0	0
T10	103746	146	0	0
T11	140908	174	0	0
T12	284143	9	0	0
T13	24381	49	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	209166	0	0
T1	7076	10	0	0
T2	334593	304	0	0
T3	317222	921	0	0
T7	195757	571	0	0
T8	12663	31	0	0
T9	1869	14	0	0
T10	103746	131	0	0
T11	140908	149	0	0
T12	284143	9	0	0
T13	24381	46	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	208206	0	0
GntImpliesValid_A	433802600	208206	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	208206	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	3001475	0	0
ReadyAndValidImplyGrant_A	433802600	208206	0	0
ReqAndReadyImplyGrant_A	433802600	208206	0	0
ReqImpliesValid_A	433802600	521827	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	208206	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	208206	0	0
T1	7076	15	0	0
T2	334593	1378	0	0
T3	317222	488	0	0
T7	195757	609	0	0
T8	12663	27	0	0
T9	1869	15	0	0
T10	103746	187	0	0
T11	140908	120	0	0
T12	284143	13	0	0
T13	24381	45	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	208206	0	0
T1	7076	15	0	0
T2	334593	1378	0	0
T3	317222	488	0	0
T7	195757	609	0	0
T8	12663	27	0	0
T9	1869	15	0	0
T10	103746	187	0	0
T11	140908	120	0	0
T12	284143	13	0	0
T13	24381	45	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	208206	0	0
T1	7076	15	0	0
T2	334593	1378	0	0
T3	317222	488	0	0
T7	195757	609	0	0
T8	12663	27	0	0
T9	1869	15	0	0
T10	103746	187	0	0
T11	140908	120	0	0
T12	284143	13	0	0
T13	24381	45	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	3001475	0	0
T1	7076	94	0	0
T2	334593	6873	0	0
T3	317222	3771	0	0
T7	195757	4460	0	0
T8	12663	209	0	0
T9	1869	15	0	0
T10	103746	1307	0	0
T11	140908	534	0	0
T12	284143	48	0	0
T13	24381	385	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	208206	0	0
T1	7076	15	0	0
T2	334593	1378	0	0
T3	317222	488	0	0
T7	195757	609	0	0
T8	12663	27	0	0
T9	1869	15	0	0
T10	103746	187	0	0
T11	140908	120	0	0
T12	284143	13	0	0
T13	24381	45	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	208206	0	0
T1	7076	15	0	0
T2	334593	1378	0	0
T3	317222	488	0	0
T7	195757	609	0	0
T8	12663	27	0	0
T9	1869	15	0	0
T10	103746	187	0	0
T11	140908	120	0	0
T12	284143	13	0	0
T13	24381	45	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	521827	0	0
T1	7076	15	0	0
T2	334593	7079	0	0
T3	317222	529	0	0
T7	195757	831	0	0
T8	12663	27	0	0
T9	1869	16	0	0
T10	103746	261	0	0
T11	140908	144	0	0
T12	284143	18	0	0
T13	24381	46	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	208206	0	0
T1	7076	15	0	0
T2	334593	1378	0	0
T3	317222	488	0	0
T7	195757	609	0	0
T8	12663	27	0	0
T9	1869	15	0	0
T10	103746	187	0	0
T11	140908	120	0	0
T12	284143	13	0	0
T13	24381	45	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	221125	0	0
GntImpliesValid_A	433802600	221125	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	221125	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	3103074	0	0
ReadyAndValidImplyGrant_A	433802600	221125	0	0
ReqAndReadyImplyGrant_A	433802600	221125	0	0
ReqImpliesValid_A	433802600	609788	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	221125	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	221125	0	0
T1	7076	8	0	0
T2	334593	1241	0	0
T3	317222	472	0	0
T7	195757	590	0	0
T8	12663	22	0	0
T9	1869	12	0	0
T10	103746	179	0	0
T11	140908	125	0	0
T12	284143	10	0	0
T13	24381	42	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	221125	0	0
T1	7076	8	0	0
T2	334593	1241	0	0
T3	317222	472	0	0
T7	195757	590	0	0
T8	12663	22	0	0
T9	1869	12	0	0
T10	103746	179	0	0
T11	140908	125	0	0
T12	284143	10	0	0
T13	24381	42	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	221125	0	0
T1	7076	8	0	0
T2	334593	1241	0	0
T3	317222	472	0	0
T7	195757	590	0	0
T8	12663	22	0	0
T9	1869	12	0	0
T10	103746	179	0	0
T11	140908	125	0	0
T12	284143	10	0	0
T13	24381	42	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	3103074	0	0
T1	7076	32	0	0
T2	334593	6109	0	0
T3	317222	3538	0	0
T7	195757	4360	0	0
T8	12663	171	0	0
T9	1869	13	0	0
T10	103746	1425	0	0
T11	140908	559	0	0
T12	284143	52	0	0
T13	24381	251	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	221125	0	0
T1	7076	8	0	0
T2	334593	1241	0	0
T3	317222	472	0	0
T7	195757	590	0	0
T8	12663	22	0	0
T9	1869	12	0	0
T10	103746	179	0	0
T11	140908	125	0	0
T12	284143	10	0	0
T13	24381	42	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	221125	0	0
T1	7076	8	0	0
T2	334593	1241	0	0
T3	317222	472	0	0
T7	195757	590	0	0
T8	12663	22	0	0
T9	1869	12	0	0
T10	103746	179	0	0
T11	140908	125	0	0
T12	284143	10	0	0
T13	24381	42	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	609788	0	0
T1	7076	8	0	0
T2	334593	6646	0	0
T3	317222	507	0	0
T7	195757	724	0	0
T8	12663	26	0	0
T9	1869	12	0	0
T10	103746	218	0	0
T11	140908	153	0	0
T12	284143	10	0	0
T13	24381	45	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	221125	0	0
T1	7076	8	0	0
T2	334593	1241	0	0
T3	317222	472	0	0
T7	195757	590	0	0
T8	12663	22	0	0
T9	1869	12	0	0
T10	103746	179	0	0
T11	140908	125	0	0
T12	284143	10	0	0
T13	24381	42	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	226101	0	0
GntImpliesValid_A	433802600	226101	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	226101	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	3223457	0	0
ReadyAndValidImplyGrant_A	433802600	226101	0	0
ReqAndReadyImplyGrant_A	433802600	226101	0	0
ReqImpliesValid_A	433802600	583576	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	226101	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	226101	0	0
T1	7076	26	0	0
T2	334593	858	0	0
T3	317222	501	0	0
T7	195757	693	0	0
T8	12663	37	0	0
T9	1869	19	0	0
T10	103746	586	0	0
T11	140908	137	0	0
T12	284143	9	0	0
T13	24381	80	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	226101	0	0
T1	7076	26	0	0
T2	334593	858	0	0
T3	317222	501	0	0
T7	195757	693	0	0
T8	12663	37	0	0
T9	1869	19	0	0
T10	103746	586	0	0
T11	140908	137	0	0
T12	284143	9	0	0
T13	24381	80	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	226101	0	0
T1	7076	26	0	0
T2	334593	858	0	0
T3	317222	501	0	0
T7	195757	693	0	0
T8	12663	37	0	0
T9	1869	19	0	0
T10	103746	586	0	0
T11	140908	137	0	0
T12	284143	9	0	0
T13	24381	80	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	3223457	0	0
T1	7076	167	0	0
T2	334593	5606	0	0
T3	317222	3756	0	0
T7	195757	5409	0	0
T8	12663	344	0	0
T9	1869	17	0	0
T10	103746	3645	0	0
T11	140908	549	0	0
T12	284143	51	0	0
T13	24381	573	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	226101	0	0
T1	7076	26	0	0
T2	334593	858	0	0
T3	317222	501	0	0
T7	195757	693	0	0
T8	12663	37	0	0
T9	1869	19	0	0
T10	103746	586	0	0
T11	140908	137	0	0
T12	284143	9	0	0
T13	24381	80	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	226101	0	0
T1	7076	26	0	0
T2	334593	858	0	0
T3	317222	501	0	0
T7	195757	693	0	0
T8	12663	37	0	0
T9	1869	19	0	0
T10	103746	586	0	0
T11	140908	137	0	0
T12	284143	9	0	0
T13	24381	80	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	583576	0	0
T1	7076	31	0	0
T2	334593	2719	0	0
T3	317222	567	0	0
T7	195757	944	0	0
T8	12663	43	0	0
T9	1869	22	0	0
T10	103746	2006	0	0
T11	140908	173	0	0
T12	284143	10	0	0
T13	24381	107	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	226101	0	0
T1	7076	26	0	0
T2	334593	858	0	0
T3	317222	501	0	0
T7	195757	693	0	0
T8	12663	37	0	0
T9	1869	19	0	0
T10	103746	586	0	0
T11	140908	137	0	0
T12	284143	9	0	0
T13	24381	80	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	215105	0	0
GntImpliesValid_A	433802600	215105	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	215105	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	3086530	0	0
ReadyAndValidImplyGrant_A	433802600	215105	0	0
ReqAndReadyImplyGrant_A	433802600	215105	0	0
ReqImpliesValid_A	433802600	573345	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	215105	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	215105	0	0
T1	7076	11	0	0
T2	334593	884	0	0
T3	317222	501	0	0
T7	195757	580	0	0
T8	12663	25	0	0
T9	1869	13	0	0
T10	103746	158	0	0
T11	140908	147	0	0
T12	284143	8	0	0
T13	24381	36	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	215105	0	0
T1	7076	11	0	0
T2	334593	884	0	0
T3	317222	501	0	0
T7	195757	580	0	0
T8	12663	25	0	0
T9	1869	13	0	0
T10	103746	158	0	0
T11	140908	147	0	0
T12	284143	8	0	0
T13	24381	36	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	215105	0	0
T1	7076	11	0	0
T2	334593	884	0	0
T3	317222	501	0	0
T7	195757	580	0	0
T8	12663	25	0	0
T9	1869	13	0	0
T10	103746	158	0	0
T11	140908	147	0	0
T12	284143	8	0	0
T13	24381	36	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	3086530	0	0
T1	7076	103	0	0
T2	334593	5435	0	0
T3	317222	3750	0	0
T7	195757	4354	0	0
T8	12663	178	0	0
T9	1869	13	0	0
T10	103746	1304	0	0
T11	140908	600	0	0
T12	284143	39	0	0
T13	24381	251	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	215105	0	0
T1	7076	11	0	0
T2	334593	884	0	0
T3	317222	501	0	0
T7	195757	580	0	0
T8	12663	25	0	0
T9	1869	13	0	0
T10	103746	158	0	0
T11	140908	147	0	0
T12	284143	8	0	0
T13	24381	36	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	215105	0	0
T1	7076	11	0	0
T2	334593	884	0	0
T3	317222	501	0	0
T7	195757	580	0	0
T8	12663	25	0	0
T9	1869	13	0	0
T10	103746	158	0	0
T11	140908	147	0	0
T12	284143	8	0	0
T13	24381	36	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	573345	0	0
T1	7076	18	0	0
T2	334593	1763	0	0
T3	317222	613	0	0
T7	195757	869	0	0
T8	12663	29	0	0
T9	1869	14	0	0
T10	103746	190	0	0
T11	140908	188	0	0
T12	284143	8	0	0
T13	24381	42	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	215105	0	0
T1	7076	11	0	0
T2	334593	884	0	0
T3	317222	501	0	0
T7	195757	580	0	0
T8	12663	25	0	0
T9	1869	13	0	0
T10	103746	158	0	0
T11	140908	147	0	0
T12	284143	8	0	0
T13	24381	36	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	205016	0	0
GntImpliesValid_A	433802600	205016	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	205016	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	3032197	0	0
ReadyAndValidImplyGrant_A	433802600	205016	0	0
ReqAndReadyImplyGrant_A	433802600	205016	0	0
ReqImpliesValid_A	433802600	541918	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	205016	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	205016	0	0
T1	7076	12	0	0
T2	334593	298	0	0
T3	317222	493	0	0
T7	195757	587	0	0
T8	12663	20	0	0
T9	1869	14	0	0
T10	103746	135	0	0
T11	140908	137	0	0
T12	284143	12	0	0
T13	24381	50	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	205016	0	0
T1	7076	12	0	0
T2	334593	298	0	0
T3	317222	493	0	0
T7	195757	587	0	0
T8	12663	20	0	0
T9	1869	14	0	0
T10	103746	135	0	0
T11	140908	137	0	0
T12	284143	12	0	0
T13	24381	50	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	205016	0	0
T1	7076	12	0	0
T2	334593	298	0	0
T3	317222	493	0	0
T7	195757	587	0	0
T8	12663	20	0	0
T9	1869	14	0	0
T10	103746	135	0	0
T11	140908	137	0	0
T12	284143	12	0	0
T13	24381	50	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	3032197	0	0
T1	7076	86	0	0
T2	334593	2211	0	0
T3	317222	3854	0	0
T7	195757	4485	0	0
T8	12663	156	0	0
T9	1869	15	0	0
T10	103746	940	0	0
T11	140908	592	0	0
T12	284143	35	0	0
T13	24381	374	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	205016	0	0
T1	7076	12	0	0
T2	334593	298	0	0
T3	317222	493	0	0
T7	195757	587	0	0
T8	12663	20	0	0
T9	1869	14	0	0
T10	103746	135	0	0
T11	140908	137	0	0
T12	284143	12	0	0
T13	24381	50	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	205016	0	0
T1	7076	12	0	0
T2	334593	298	0	0
T3	317222	493	0	0
T7	195757	587	0	0
T8	12663	20	0	0
T9	1869	14	0	0
T10	103746	135	0	0
T11	140908	137	0	0
T12	284143	12	0	0
T13	24381	50	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	541918	0	0
T1	7076	12	0	0
T2	334593	318	0	0
T3	317222	534	0	0
T7	195757	673	0	0
T8	12663	21	0	0
T9	1869	14	0	0
T10	103746	164	0	0
T11	140908	187	0	0
T12	284143	14	0	0
T13	24381	50	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	205016	0	0
T1	7076	12	0	0
T2	334593	298	0	0
T3	317222	493	0	0
T7	195757	587	0	0
T8	12663	20	0	0
T9	1869	14	0	0
T10	103746	135	0	0
T11	140908	137	0	0
T12	284143	12	0	0
T13	24381	50	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	212659	0	0
GntImpliesValid_A	433802600	212659	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	212659	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	3096768	0	0
ReadyAndValidImplyGrant_A	433802600	212659	0	0
ReqAndReadyImplyGrant_A	433802600	212659	0	0
ReqImpliesValid_A	433802600	574143	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	212659	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	212659	0	0
T1	7076	10	0	0
T2	334593	744	0	0
T3	317222	481	0	0
T7	195757	612	0	0
T8	12663	22	0	0
T9	1869	11	0	0
T10	103746	182	0	0
T11	140908	138	0	0
T12	284143	6	0	0
T13	24381	46	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	212659	0	0
T1	7076	10	0	0
T2	334593	744	0	0
T3	317222	481	0	0
T7	195757	612	0	0
T8	12663	22	0	0
T9	1869	11	0	0
T10	103746	182	0	0
T11	140908	138	0	0
T12	284143	6	0	0
T13	24381	46	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	212659	0	0
T1	7076	10	0	0
T2	334593	744	0	0
T3	317222	481	0	0
T7	195757	612	0	0
T8	12663	22	0	0
T9	1869	11	0	0
T10	103746	182	0	0
T11	140908	138	0	0
T12	284143	6	0	0
T13	24381	46	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	3096768	0	0
T1	7076	74	0	0
T2	334593	5374	0	0
T3	317222	3612	0	0
T7	195757	4327	0	0
T8	12663	142	0	0
T9	1869	11	0	0
T10	103746	1434	0	0
T11	140908	601	0	0
T12	284143	18	0	0
T13	24381	371	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	212659	0	0
T1	7076	10	0	0
T2	334593	744	0	0
T3	317222	481	0	0
T7	195757	612	0	0
T8	12663	22	0	0
T9	1869	11	0	0
T10	103746	182	0	0
T11	140908	138	0	0
T12	284143	6	0	0
T13	24381	46	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	212659	0	0
T1	7076	10	0	0
T2	334593	744	0	0
T3	317222	481	0	0
T7	195757	612	0	0
T8	12663	22	0	0
T9	1869	11	0	0
T10	103746	182	0	0
T11	140908	138	0	0
T12	284143	6	0	0
T13	24381	46	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	574143	0	0
T1	7076	10	0	0
T2	334593	1495	0	0
T3	317222	504	0	0
T7	195757	915	0	0
T8	12663	22	0	0
T9	1869	12	0	0
T10	103746	231	0	0
T11	140908	168	0	0
T12	284143	6	0	0
T13	24381	63	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	212659	0	0
T1	7076	10	0	0
T2	334593	744	0	0
T3	317222	481	0	0
T7	195757	612	0	0
T8	12663	22	0	0
T9	1869	11	0	0
T10	103746	182	0	0
T11	140908	138	0	0
T12	284143	6	0	0
T13	24381	46	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	202201	0	0
GntImpliesValid_A	433802600	202201	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	202201	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	3095404	0	0
ReadyAndValidImplyGrant_A	433802600	202201	0	0
ReqAndReadyImplyGrant_A	433802600	202201	0	0
ReqImpliesValid_A	433802600	558939	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	202201	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	202201	0	0
T1	7076	7	0	0
T2	334593	328	0	0
T3	317222	1006	0	0
T7	195757	563	0	0
T8	12663	29	0	0
T9	1869	12	0	0
T10	103746	152	0	0
T11	140908	131	0	0
T12	284143	11	0	0
T13	24381	42	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	202201	0	0
T1	7076	7	0	0
T2	334593	328	0	0
T3	317222	1006	0	0
T7	195757	563	0	0
T8	12663	29	0	0
T9	1869	12	0	0
T10	103746	152	0	0
T11	140908	131	0	0
T12	284143	11	0	0
T13	24381	42	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	202201	0	0
T1	7076	7	0	0
T2	334593	328	0	0
T3	317222	1006	0	0
T7	195757	563	0	0
T8	12663	29	0	0
T9	1869	12	0	0
T10	103746	152	0	0
T11	140908	131	0	0
T12	284143	11	0	0
T13	24381	42	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	3095404	0	0
T1	7076	40	0	0
T2	334593	2449	0	0
T3	317222	6361	0	0
T7	195757	4292	0	0
T8	12663	188	0	0
T9	1869	12	0	0
T10	103746	963	0	0
T11	140908	599	0	0
T12	284143	28	0	0
T13	24381	250	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	202201	0	0
T1	7076	7	0	0
T2	334593	328	0	0
T3	317222	1006	0	0
T7	195757	563	0	0
T8	12663	29	0	0
T9	1869	12	0	0
T10	103746	152	0	0
T11	140908	131	0	0
T12	284143	11	0	0
T13	24381	42	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	202201	0	0
T1	7076	7	0	0
T2	334593	328	0	0
T3	317222	1006	0	0
T7	195757	563	0	0
T8	12663	29	0	0
T9	1869	12	0	0
T10	103746	152	0	0
T11	140908	131	0	0
T12	284143	11	0	0
T13	24381	42	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	558939	0	0
T1	7076	7	0	0
T2	334593	367	0	0
T3	317222	3127	0	0
T7	195757	698	0	0
T8	12663	31	0	0
T9	1869	13	0	0
T10	103746	190	0	0
T11	140908	141	0	0
T12	284143	11	0	0
T13	24381	44	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	202201	0	0
T1	7076	7	0	0
T2	334593	328	0	0
T3	317222	1006	0	0
T7	195757	563	0	0
T8	12663	29	0	0
T9	1869	12	0	0
T10	103746	152	0	0
T11	140908	131	0	0
T12	284143	11	0	0
T13	24381	42	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	211202	0	0
GntImpliesValid_A	433802600	211202	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	211202	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	3069020	0	0
ReadyAndValidImplyGrant_A	433802600	211202	0	0
ReqAndReadyImplyGrant_A	433802600	211202	0	0
ReqImpliesValid_A	433802600	565168	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	0	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	211202	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	211202	0	0
T1	7076	6	0	0
T2	334593	769	0	0
T3	317222	1001	0	0
T7	195757	552	0	0
T8	12663	32	0	0
T9	1869	12	0	0
T10	103746	145	0	0
T11	140908	131	0	0
T12	284143	10	0	0
T13	24381	35	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	211202	0	0
T1	7076	6	0	0
T2	334593	769	0	0
T3	317222	1001	0	0
T7	195757	552	0	0
T8	12663	32	0	0
T9	1869	12	0	0
T10	103746	145	0	0
T11	140908	131	0	0
T12	284143	10	0	0
T13	24381	35	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	211202	0	0
T1	7076	6	0	0
T2	334593	769	0	0
T3	317222	1001	0	0
T7	195757	552	0	0
T8	12663	32	0	0
T9	1869	12	0	0
T10	103746	145	0	0
T11	140908	131	0	0
T12	284143	10	0	0
T13	24381	35	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	3069020	0	0
T1	7076	47	0	0
T2	334593	5069	0	0
T3	317222	5852	0	0
T7	195757	4321	0	0
T8	12663	288	0	0
T9	1869	13	0	0
T10	103746	1191	0	0
T11	140908	599	0	0
T12	284143	35	0	0
T13	24381	264	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	211202	0	0
T1	7076	6	0	0
T2	334593	769	0	0
T3	317222	1001	0	0
T7	195757	552	0	0
T8	12663	32	0	0
T9	1869	12	0	0
T10	103746	145	0	0
T11	140908	131	0	0
T12	284143	10	0	0
T13	24381	35	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	211202	0	0
T1	7076	6	0	0
T2	334593	769	0	0
T3	317222	1001	0	0
T7	195757	552	0	0
T8	12663	32	0	0
T9	1869	12	0	0
T10	103746	145	0	0
T11	140908	131	0	0
T12	284143	10	0	0
T13	24381	35	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	565168	0	0
T1	7076	6	0	0
T2	334593	2034	0	0
T3	317222	2073	0	0
T7	195757	688	0	0
T8	12663	42	0	0
T9	1869	12	0	0
T10	103746	207	0	0
T11	140908	161	0	0
T12	284143	12	0	0
T13	24381	45	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	211202	0	0
T1	7076	6	0	0
T2	334593	769	0	0
T3	317222	1001	0	0
T7	195757	552	0	0
T8	12663	32	0	0
T9	1869	12	0	0
T10	103746	145	0	0
T11	140908	131	0	0
T12	284143	10	0	0
T13	24381	35	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	860470	0	0
GntImpliesValid_A	433802600	860470	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	860470	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	11689160	0	0
ReadyAndValidImplyGrant_A	433802600	860470	0	0
ReqAndReadyImplyGrant_A	433802600	860470	0	0
ReqImpliesValid_A	433802600	2230237	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	18074	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	860470	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	860470	0	0
T1	7076	60	0	0
T2	334593	3935	0	0
T3	317222	3536	0	0
T7	195757	2360	0	0
T8	12663	89	0	0
T9	1869	59	0	0
T10	103746	939	0	0
T11	140908	541	0	0
T12	284143	69	0	0
T13	24381	199	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	860470	0	0
T1	7076	60	0	0
T2	334593	3935	0	0
T3	317222	3536	0	0
T7	195757	2360	0	0
T8	12663	89	0	0
T9	1869	59	0	0
T10	103746	939	0	0
T11	140908	541	0	0
T12	284143	69	0	0
T13	24381	199	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	860470	0	0
T1	7076	60	0	0
T2	334593	3935	0	0
T3	317222	3536	0	0
T7	195757	2360	0	0
T8	12663	89	0	0
T9	1869	59	0	0
T10	103746	939	0	0
T11	140908	541	0	0
T12	284143	69	0	0
T13	24381	199	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	11689160	0	0
T1	7076	413	0	0
T2	334593	18494	0	0
T3	317222	21259	0	0
T7	195757	14716	0	0
T8	12663	592	0	0
T9	1869	1	0	0
T10	103746	6050	0	0
T11	140908	1807	0	0
T12	284143	218	0	0
T13	24381	1359	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	860470	0	0
T1	7076	60	0	0
T2	334593	3935	0	0
T3	317222	3536	0	0
T7	195757	2360	0	0
T8	12663	89	0	0
T9	1869	59	0	0
T10	103746	939	0	0
T11	140908	541	0	0
T12	284143	69	0	0
T13	24381	199	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	860470	0	0
T1	7076	60	0	0
T2	334593	3935	0	0
T3	317222	3536	0	0
T7	195757	2360	0	0
T8	12663	89	0	0
T9	1869	59	0	0
T10	103746	939	0	0
T11	140908	541	0	0
T12	284143	69	0	0
T13	24381	199	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	2230237	0	0
T1	7076	113	0	0
T2	334593	17554	0	0
T3	317222	8267	0	0
T7	195757	3433	0	0
T8	12663	139	0	0
T9	1869	59	0	0
T10	103746	1361	0	0
T11	140908	696	0	0
T12	284143	88	0	0
T13	24381	304	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	18074	0	900
T2	334593	18	0	1
T3	317222	3	0	1
T4	0	1	0	0
T7	195757	1	0	1
T8	12663	0	0	1
T9	1869	0	0	1
T10	103746	0	0	1
T11	140908	0	0	1
T12	284143	0	0	1
T13	24381	1	0	1
T14	0	5	0	0
T15	0	10	0	0
T17	0	366	0	0
T18	0	10	0	0
T19	0	14	0	0
T20	559713	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	860470	0	0
T1	7076	60	0	0
T2	334593	3935	0	0
T3	317222	3536	0	0
T7	195757	2360	0	0
T8	12663	89	0	0
T9	1869	59	0	0
T10	103746	939	0	0
T11	140908	541	0	0
T12	284143	69	0	0
T13	24381	199	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	433802600	433679432	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	433802600	850241	0	0
GntImpliesValid_A	433802600	850241	0	0
GrantKnown_A	433802600	433679432	0	0
IdxKnown_A	433802600	433679432	0	0
IndexIsCorrect_A	433802600	850241	0	0
LockArbDecision_A	433802600	0	0	0
NoReadyValidNoGrant_A	433802600	365233321	0	0
ReadyAndValidImplyGrant_A	433802600	850241	0	0
ReqAndReadyImplyGrant_A	433802600	850241	0	0
ReqImpliesValid_A	433802600	13440177	0	0
ReqStaysHighUntilGranted0_M	433802600	0	0	0
RoundRobin_A	433802600	22515	0	900
ValidKnown_A	433802600	433679432	0	0
gen_data_port_assertion.DataFlow_A	433802600	850241	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	850241	0	0
T1	7076	49	0	0
T2	334593	1913	0	0
T3	317222	3346	0	0
T7	195757	2387	0	0
T8	12663	81	0	0
T9	1869	66	0	0
T10	103746	1570	0	0
T11	140908	557	0	0
T12	284143	55	0	0
T13	24381	198	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	850241	0	0
T1	7076	49	0	0
T2	334593	1913	0	0
T3	317222	3346	0	0
T7	195757	2387	0	0
T8	12663	81	0	0
T9	1869	66	0	0
T10	103746	1570	0	0
T11	140908	557	0	0
T12	284143	55	0	0
T13	24381	198	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	850241	0	0
T1	7076	49	0	0
T2	334593	1913	0	0
T3	317222	3346	0	0
T7	195757	2387	0	0
T8	12663	81	0	0
T9	1869	66	0	0
T10	103746	1570	0	0
T11	140908	557	0	0
T12	284143	55	0	0
T13	24381	198	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	365233321	0	0
T1	7076	5992	0	0
T2	334593	290195	0	0
T3	317222	262104	0	0
T7	195757	159926	0	0
T8	12663	10636	0	0
T9	1869	1	0	0
T10	103746	82487	0	0
T11	140908	117230	0	0
T12	284143	236352	0	0
T13	24381	20770	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	850241	0	0
T1	7076	49	0	0
T2	334593	1913	0	0
T3	317222	3346	0	0
T7	195757	2387	0	0
T8	12663	81	0	0
T9	1869	66	0	0
T10	103746	1570	0	0
T11	140908	557	0	0
T12	284143	55	0	0
T13	24381	198	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	850241	0	0
T1	7076	49	0	0
T2	334593	1913	0	0
T3	317222	3346	0	0
T7	195757	2387	0	0
T8	12663	81	0	0
T9	1869	66	0	0
T10	103746	1570	0	0
T11	140908	557	0	0
T12	284143	55	0	0
T13	24381	198	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	13440177	0	0
T1	7076	297	0	0
T2	334593	15765	0	0
T3	317222	28456	0	0
T7	195757	20182	0	0
T8	12663	639	0	0
T9	1869	66	0	0
T10	103746	13370	0	0
T11	140908	2445	0	0
T12	284143	213	0	0
T13	24381	1528	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	22515	0	900
T2	334593	1	0	1
T3	317222	9	0	1
T7	195757	2	0	1
T8	12663	0	0	1
T9	1869	0	0	1
T10	103746	3	0	1
T11	140908	0	0	1
T12	284143	0	0	1
T13	24381	0	0	1
T14	0	4	0	0
T15	0	8	0	0
T16	0	2	0	0
T17	0	56	0	0
T18	0	8	0	0
T19	0	12	0	0
T20	559713	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	433679432	0	0
T1	7076	7036	0	0
T2	334593	334383	0	0
T3	317222	316045	0	0
T7	195757	195353	0	0
T8	12663	12581	0	0
T9	1869	1843	0	0
T10	103746	103731	0	0
T11	140908	140904	0	0
T12	284143	284094	0	0
T13	24381	24319	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433802600	850241	0	0
T1	7076	49	0	0
T2	334593	1913	0	0
T3	317222	3346	0	0
T7	195757	2387	0	0
T8	12663	81	0	0
T9	1869	66	0	0
T10	103746	1570	0	0
T11	140908	557	0	0
T12	284143	55	0	0
T13	24381	198	0	0