Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1595420 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 255007 1 T1 453 T2 534 T3 62


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 627062 1 T1 987 T2 1281 T3 156
values[0x0] 595711 1 T1 1011 T2 1204 T3 126
values[0x1] 627654 1 T1 1166 T2 1292 T3 159


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1232864 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 617563 1 T1 1049 T2 1301 T3 148


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 29363 1 T1 33 T2 66 T3 9
valid_sources[0x01] 29094 1 T1 9 T2 67 T3 5
valid_sources[0x02] 29915 1 T1 7 T2 43 T3 3
valid_sources[0x03] 28504 1 T1 69 T2 70 T3 5
valid_sources[0x04] 29760 1 T1 59 T2 71 T3 12
valid_sources[0x05] 28718 1 T1 52 T2 64 T3 9
valid_sources[0x06] 28050 1 T1 35 T2 54 T3 8
valid_sources[0x07] 29443 1 T1 68 T2 56 T3 6
valid_sources[0x08] 29446 1 T1 79 T2 71 T3 9
valid_sources[0x09] 28172 1 T1 111 T2 61 T3 17
valid_sources[0x0a] 28909 1 T1 4 T2 63 T3 11
valid_sources[0x0b] 27574 1 T1 46 T2 62 T3 8
valid_sources[0x0c] 28049 1 T1 73 T2 53 T3 7
valid_sources[0x0d] 28519 1 T1 56 T2 69 T3 6
valid_sources[0x0e] 30242 1 T1 48 T2 58 T3 6
valid_sources[0x0f] 29189 1 T1 43 T2 53 T3 6
valid_sources[0x10] 29482 1 T1 44 T2 71 T3 7
valid_sources[0x11] 28269 1 T1 21 T2 52 T3 4
valid_sources[0x12] 28813 1 T1 53 T2 55 T3 5
valid_sources[0x13] 27482 1 T1 6 T2 49 T3 5
valid_sources[0x14] 28492 1 T1 82 T2 61 T3 3
valid_sources[0x15] 29135 1 T1 29 T2 45 T3 4
valid_sources[0x16] 29097 1 T1 108 T2 59 T3 6
valid_sources[0x17] 29512 1 T1 13 T2 42 T3 4
valid_sources[0x18] 28495 1 T1 42 T2 43 T3 11
valid_sources[0x19] 30528 1 T1 33 T2 62 T3 6
valid_sources[0x1a] 28519 1 T1 97 T2 64 T3 14
valid_sources[0x1b] 28510 1 T1 52 T2 58 T3 9
valid_sources[0x1c] 28034 1 T1 23 T2 61 T3 2
valid_sources[0x1d] 28763 1 T1 56 T2 59 T3 4
valid_sources[0x1e] 30222 1 T1 47 T2 55 T3 9
valid_sources[0x1f] 28893 1 T1 73 T2 63 T3 5
valid_sources[0x20] 28684 1 T1 28 T2 69 T3 7


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26784 1 T1 49 T2 47 T3 6
values[0x0] all_enables biggest_size 201684 1 T1 352 T2 436 T3 45
values[0x1] all_enables biggest_size 26539 1 T1 52 T2 51 T3 11


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1614519 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 263691 1 T1 435 T2 516 T3 54


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 642546 1 T1 1033 T2 1290 T3 116
values[0x0] 592628 1 T1 1039 T2 1157 T3 120
values[0x1] 643036 1 T1 1079 T2 1287 T3 140


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1239545 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 638665 1 T1 1046 T2 1281 T3 132


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 29314 1 T1 55 T2 99 T3 3
valid_sources[0x01] 29742 1 T1 38 T2 26 T3 5
valid_sources[0x02] 29403 1 T1 37 T2 60 T3 4
valid_sources[0x03] 28680 1 T1 40 T2 43 T3 3
valid_sources[0x04] 29718 1 T1 48 T2 47 T3 2
valid_sources[0x05] 28945 1 T1 43 T2 41 T3 3
valid_sources[0x06] 29090 1 T1 34 T2 46 T3 10
valid_sources[0x07] 29038 1 T1 42 T2 57 T3 4
valid_sources[0x08] 29736 1 T1 82 T2 63 T3 6
valid_sources[0x09] 28608 1 T1 85 T2 56 T3 10
valid_sources[0x0a] 29810 1 T1 26 T2 126 T3 2
valid_sources[0x0b] 29174 1 T1 34 T2 51 T3 5
valid_sources[0x0c] 29874 1 T1 84 T2 55 T3 3
valid_sources[0x0d] 29343 1 T1 37 T2 46 T3 5
valid_sources[0x0e] 28595 1 T1 48 T2 69 T3 11
valid_sources[0x0f] 29647 1 T1 47 T2 38 T3 1
valid_sources[0x10] 30368 1 T1 32 T2 70 T3 9
valid_sources[0x11] 29685 1 T1 64 T2 59 T3 9
valid_sources[0x12] 29468 1 T1 65 T2 75 T3 7
valid_sources[0x13] 28822 1 T1 31 T2 57 T3 2
valid_sources[0x14] 29466 1 T1 76 T2 99 T3 7
valid_sources[0x15] 29414 1 T1 35 T2 39 T3 10
valid_sources[0x16] 29000 1 T1 40 T2 82 T3 4
valid_sources[0x17] 29643 1 T1 36 T2 83 T3 3
valid_sources[0x18] 29541 1 T1 35 T2 81 T3 5
valid_sources[0x19] 29748 1 T1 20 T2 86 T3 5
valid_sources[0x1a] 28695 1 T1 65 T2 47 T3 7
valid_sources[0x1b] 29973 1 T1 20 T2 41 T3 2
valid_sources[0x1c] 29875 1 T1 42 T2 61 T3 3
valid_sources[0x1d] 30174 1 T1 54 T2 55 T3 4
valid_sources[0x1e] 29723 1 T1 79 T2 57 T3 5
valid_sources[0x1f] 29252 1 T1 27 T2 24 T3 7
valid_sources[0x20] 29142 1 T1 69 T2 37 T3 8


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 27639 1 T1 41 T2 62 T3 5
values[0x0] all_enables biggest_size 208321 1 T1 358 T2 411 T3 45
values[0x1] all_enables biggest_size 27731 1 T1 36 T2 43 T3 4


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1601082 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 255177 1 T1 437 T2 495 T3 75


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 629625 1 T1 1058 T2 1156 T3 186
values[0x0] 597144 1 T1 1034 T2 1185 T3 163
values[0x1] 629490 1 T1 995 T2 1219 T3 192


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1236574 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 619685 1 T1 1036 T2 1152 T3 188


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27865 1 T1 46 T2 32 T3 10
valid_sources[0x01] 29353 1 T1 33 T2 52 T3 18
valid_sources[0x02] 29425 1 T1 39 T2 46 T3 11
valid_sources[0x03] 28874 1 T1 29 T2 61 T3 9
valid_sources[0x04] 29392 1 T1 37 T2 49 T3 10
valid_sources[0x05] 28322 1 T1 54 T2 83 T3 12
valid_sources[0x06] 29186 1 T1 44 T2 49 T3 9
valid_sources[0x07] 29521 1 T1 40 T2 52 T3 6
valid_sources[0x08] 29456 1 T1 58 T2 48 T3 10
valid_sources[0x09] 28657 1 T1 95 T2 56 T3 5
valid_sources[0x0a] 29132 1 T1 23 T2 57 T3 13
valid_sources[0x0b] 28817 1 T1 29 T2 56 T3 11
valid_sources[0x0c] 29785 1 T1 61 T2 32 T3 8
valid_sources[0x0d] 28384 1 T1 50 T2 66 T3 7
valid_sources[0x0e] 29752 1 T1 53 T2 55 T3 9
valid_sources[0x0f] 28360 1 T1 50 T2 50 T3 9
valid_sources[0x10] 29736 1 T1 36 T2 78 T3 12
valid_sources[0x11] 29243 1 T1 44 T2 42 T3 11
valid_sources[0x12] 29537 1 T1 48 T2 61 T3 10
valid_sources[0x13] 28820 1 T1 33 T2 33 T3 8
valid_sources[0x14] 28855 1 T1 90 T2 35 T3 8
valid_sources[0x15] 29211 1 T1 54 T2 73 T3 5
valid_sources[0x16] 29211 1 T1 48 T2 87 T3 5
valid_sources[0x17] 29215 1 T1 32 T2 46 T3 7
valid_sources[0x18] 29438 1 T1 56 T2 93 T3 7
valid_sources[0x19] 29304 1 T1 33 T2 55 T3 7
valid_sources[0x1a] 28344 1 T1 55 T2 57 T3 7
valid_sources[0x1b] 29571 1 T1 35 T2 113 T3 10
valid_sources[0x1c] 29158 1 T1 48 T2 83 T3 10
valid_sources[0x1d] 29628 1 T1 49 T2 66 T3 9
valid_sources[0x1e] 29108 1 T1 59 T2 36 T3 9
valid_sources[0x1f] 28641 1 T1 48 T2 66 T3 6
valid_sources[0x20] 28445 1 T1 84 T2 116 T3 4


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26831 1 T1 49 T2 46 T3 8
values[0x0] all_enables biggest_size 201416 1 T1 343 T2 404 T3 59
values[0x1] all_enables biggest_size 26930 1 T1 45 T2 45 T3 8

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%