Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7838052	0	0
GntImpliesValid_A	2147483647	7838052	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7838052	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	414529451	0	0
ReadyAndValidImplyGrant_A	2147483647	7838052	0	0
ReqAndReadyImplyGrant_A	2147483647	7838052	0	0
ReqImpliesValid_A	2147483647	32359471	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	46289	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7838052	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	513816	496176	0	0
T2	536640	536208	0	0
T3	245136	243240	0	0
T4	75408	73560	0	0
T7	755520	755208	0	0
T8	5454216	5452152	0	0
T9	512424	510600	0	0
T10	63336	63192	0	0
T11	9286608	9286032	0	0
T12	188016	186384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7838052	0	0
T1	513816	7606	0	0
T2	536640	11071	0	0
T3	245136	669	0	0
T4	75408	1279	0	0
T7	755520	3565	0	0
T8	5454216	21351	0	0
T9	512424	7075	0	0
T10	63336	1659	0	0
T11	9286608	694	0	0
T12	188016	2472	0	0
T13	0	1177	0	0
T14	0	430	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7838052	0	0
T1	513816	7606	0	0
T2	536640	11071	0	0
T3	245136	669	0	0
T4	75408	1279	0	0
T7	755520	3565	0	0
T8	5454216	21351	0	0
T9	512424	7075	0	0
T10	63336	1659	0	0
T11	9286608	694	0	0
T12	188016	2472	0	0
T13	0	1177	0	0
T14	0	430	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	513816	496176	0	0
T2	536640	536208	0	0
T3	245136	243240	0	0
T4	75408	73560	0	0
T7	755520	755208	0	0
T8	5454216	5452152	0	0
T9	512424	510600	0	0
T10	63336	63192	0	0
T11	9286608	9286032	0	0
T12	188016	186384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	513816	496176	0	0
T2	536640	536208	0	0
T3	245136	243240	0	0
T4	75408	73560	0	0
T7	755520	755208	0	0
T8	5454216	5452152	0	0
T9	512424	510600	0	0
T10	63336	63192	0	0
T11	9286608	9286032	0	0
T12	188016	186384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7838052	0	0
T1	513816	7606	0	0
T2	536640	11071	0	0
T3	245136	669	0	0
T4	75408	1279	0	0
T7	755520	3565	0	0
T8	5454216	21351	0	0
T9	512424	7075	0	0
T10	63336	1659	0	0
T11	9286608	694	0	0
T12	188016	2472	0	0
T13	0	1177	0	0
T14	0	430	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	414529451	0	0
T1	513816	13185	0	0
T2	536640	1334	0	0
T3	245136	13472	0	0
T4	75408	2137	0	0
T7	755520	46694	0	0
T8	5454216	342788	0	0
T9	512424	10797	0	0
T10	63336	1646	0	0
T11	9286608	324633	0	0
T12	188016	4473	0	0
T13	0	4015	0	0
T14	0	244	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7838052	0	0
T1	513816	7606	0	0
T2	536640	11071	0	0
T3	245136	669	0	0
T4	75408	1279	0	0
T7	755520	3565	0	0
T8	5454216	21351	0	0
T9	512424	7075	0	0
T10	63336	1659	0	0
T11	9286608	694	0	0
T12	188016	2472	0	0
T13	0	1177	0	0
T14	0	430	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7838052	0	0
T1	513816	7606	0	0
T2	536640	11071	0	0
T3	245136	669	0	0
T4	75408	1279	0	0
T7	755520	3565	0	0
T8	5454216	21351	0	0
T9	512424	7075	0	0
T10	63336	1659	0	0
T11	9286608	694	0	0
T12	188016	2472	0	0
T13	0	1177	0	0
T14	0	430	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32359471	0	0
T1	513816	8664	0	0
T2	536640	24835	0	0
T3	245136	1367	0	0
T4	75408	1632	0	0
T7	755520	7800	0	0
T8	5454216	44802	0	0
T9	512424	7332	0	0
T10	63336	1873	0	0
T11	9286608	1678	0	0
T12	188016	3056	0	0
T13	0	3505	0	0
T14	0	505	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46289	0	21600
T1	42818	92	0	2
T2	44720	289	0	2
T3	20428	0	0	2
T4	6284	2	0	2
T7	62960	2	0	2
T8	454518	2	0	2
T9	42702	18	0	2
T10	5278	8	0	2
T11	773884	0	0	2
T12	15668	8	0	2
T14	0	1	0	0
T15	0	3	0	0
T16	0	5	0	0
T17	0	4	0	0
T18	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	513816	496176	0	0
T2	536640	536208	0	0
T3	245136	243240	0	0
T4	75408	73560	0	0
T7	755520	755208	0	0
T8	5454216	5452152	0	0
T9	512424	510600	0	0
T10	63336	63192	0	0
T11	9286608	9286032	0	0
T12	188016	186384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7838052	0	0
T1	513816	7606	0	0
T2	536640	11071	0	0
T3	245136	669	0	0
T4	75408	1279	0	0
T7	755520	3565	0	0
T8	5454216	21351	0	0
T9	512424	7075	0	0
T10	63336	1659	0	0
T11	9286608	694	0	0
T12	188016	2472	0	0
T13	0	1177	0	0
T14	0	430	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	884781	0	0
GntImpliesValid_A	378853553	884781	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	884781	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	11161624	0	0
ReadyAndValidImplyGrant_A	378853553	884781	0	0
ReqAndReadyImplyGrant_A	378853553	884781	0	0
ReqImpliesValid_A	378853553	2391353	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	884781	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	884781	0	0
T1	21409	729	0	0
T2	22360	1607	0	0
T3	10214	75	0	0
T4	3142	121	0	0
T7	31480	390	0	0
T8	227259	2412	0	0
T9	21351	783	0	0
T10	2639	180	0	0
T11	386942	0	0	0
T12	7834	300	0	0
T13	0	153	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	884781	0	0
T1	21409	729	0	0
T2	22360	1607	0	0
T3	10214	75	0	0
T4	3142	121	0	0
T7	31480	390	0	0
T8	227259	2412	0	0
T9	21351	783	0	0
T10	2639	180	0	0
T11	386942	0	0	0
T12	7834	300	0	0
T13	0	153	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	884781	0	0
T1	21409	729	0	0
T2	22360	1607	0	0
T3	10214	75	0	0
T4	3142	121	0	0
T7	31480	390	0	0
T8	227259	2412	0	0
T9	21351	783	0	0
T10	2639	180	0	0
T11	386942	0	0	0
T12	7834	300	0	0
T13	0	153	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	11161624	0	0
T1	21409	635	0	0
T2	22360	570	0	0
T3	10214	580	0	0
T4	3142	99	0	0
T7	31480	2792	0	0
T8	227259	18244	0	0
T9	21351	768	0	0
T10	2639	132	0	0
T11	386942	1	0	0
T12	7834	250	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	884781	0	0
T1	21409	729	0	0
T2	22360	1607	0	0
T3	10214	75	0	0
T4	3142	121	0	0
T7	31480	390	0	0
T8	227259	2412	0	0
T9	21351	783	0	0
T10	2639	180	0	0
T11	386942	0	0	0
T12	7834	300	0	0
T13	0	153	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	884781	0	0
T1	21409	729	0	0
T2	22360	1607	0	0
T3	10214	75	0	0
T4	3142	121	0	0
T7	31480	390	0	0
T8	227259	2412	0	0
T9	21351	783	0	0
T10	2639	180	0	0
T11	386942	0	0	0
T12	7834	300	0	0
T13	0	153	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	2391353	0	0
T1	21409	828	0	0
T2	22360	2645	0	0
T3	10214	134	0	0
T4	3142	144	0	0
T7	31480	777	0	0
T8	227259	3855	0	0
T9	21351	799	0	0
T10	2639	229	0	0
T11	386942	0	0	0
T12	7834	351	0	0
T13	0	266	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	884781	0	0
T1	21409	729	0	0
T2	22360	1607	0	0
T3	10214	75	0	0
T4	3142	121	0	0
T7	31480	390	0	0
T8	227259	2412	0	0
T9	21351	783	0	0
T10	2639	180	0	0
T11	386942	0	0	0
T12	7834	300	0	0
T13	0	153	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	880663	0	0
GntImpliesValid_A	378853553	880663	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	880663	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	11263975	0	0
ReadyAndValidImplyGrant_A	378853553	880663	0	0
ReqAndReadyImplyGrant_A	378853553	880663	0	0
ReqImpliesValid_A	378853553	2420481	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	880663	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	880663	0	0
T1	21409	808	0	0
T2	22360	774	0	0
T3	10214	60	0	0
T4	3142	142	0	0
T7	31480	403	0	0
T8	227259	2268	0	0
T9	21351	813	0	0
T10	2639	179	0	0
T11	386942	694	0	0
T12	7834	271	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	880663	0	0
T1	21409	808	0	0
T2	22360	774	0	0
T3	10214	60	0	0
T4	3142	142	0	0
T7	31480	403	0	0
T8	227259	2268	0	0
T9	21351	813	0	0
T10	2639	179	0	0
T11	386942	694	0	0
T12	7834	271	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	880663	0	0
T1	21409	808	0	0
T2	22360	774	0	0
T3	10214	60	0	0
T4	3142	142	0	0
T7	31480	403	0	0
T8	227259	2268	0	0
T9	21351	813	0	0
T10	2639	179	0	0
T11	386942	694	0	0
T12	7834	271	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	11263975	0	0
T1	21409	711	0	0
T2	22360	577	0	0
T3	10214	386	0	0
T4	3142	107	0	0
T7	31480	3049	0	0
T8	227259	16898	0	0
T9	21351	780	0	0
T10	2639	131	0	0
T11	386942	2089	0	0
T12	7834	221	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	880663	0	0
T1	21409	808	0	0
T2	22360	774	0	0
T3	10214	60	0	0
T4	3142	142	0	0
T7	31480	403	0	0
T8	227259	2268	0	0
T9	21351	813	0	0
T10	2639	179	0	0
T11	386942	694	0	0
T12	7834	271	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	880663	0	0
T1	21409	808	0	0
T2	22360	774	0	0
T3	10214	60	0	0
T4	3142	142	0	0
T7	31480	403	0	0
T8	227259	2268	0	0
T9	21351	813	0	0
T10	2639	179	0	0
T11	386942	694	0	0
T12	7834	271	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	2420481	0	0
T1	21409	909	0	0
T2	22360	972	0	0
T3	10214	122	0	0
T4	3142	178	0	0
T7	31480	850	0	0
T8	227259	3334	0	0
T9	21351	847	0	0
T10	2639	228	0	0
T11	386942	1678	0	0
T12	7834	322	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	880663	0	0
T1	21409	808	0	0
T2	22360	774	0	0
T3	10214	60	0	0
T4	3142	142	0	0
T7	31480	403	0	0
T8	227259	2268	0	0
T9	21351	813	0	0
T10	2639	179	0	0
T11	386942	694	0	0
T12	7834	271	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T7
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T9,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T9,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	220398	0	0
GntImpliesValid_A	378853553	220398	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	220398	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	2804778	0	0
ReadyAndValidImplyGrant_A	378853553	220398	0	0
ReqAndReadyImplyGrant_A	378853553	220398	0	0
ReqImpliesValid_A	378853553	556646	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	220398	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	220398	0	0
T1	21409	183	0	0
T2	22360	0	0	0
T3	10214	22	0	0
T4	3142	49	0	0
T7	31480	91	0	0
T8	227259	603	0	0
T9	21351	206	0	0
T10	2639	53	0	0
T11	386942	0	0	0
T12	7834	68	0	0
T13	0	37	0	0
T14	0	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	220398	0	0
T1	21409	183	0	0
T2	22360	0	0	0
T3	10214	22	0	0
T4	3142	49	0	0
T7	31480	91	0	0
T8	227259	603	0	0
T9	21351	206	0	0
T10	2639	53	0	0
T11	386942	0	0	0
T12	7834	68	0	0
T13	0	37	0	0
T14	0	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	220398	0	0
T1	21409	183	0	0
T2	22360	0	0	0
T3	10214	22	0	0
T4	3142	49	0	0
T7	31480	91	0	0
T8	227259	603	0	0
T9	21351	206	0	0
T10	2639	53	0	0
T11	386942	0	0	0
T12	7834	68	0	0
T13	0	37	0	0
T14	0	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	2804778	0	0
T1	21409	183	0	0
T2	22360	1	0	0
T3	10214	132	0	0
T4	3142	46	0	0
T7	31480	661	0	0
T8	227259	4464	0	0
T9	21351	206	0	0
T10	2639	52	0	0
T11	386942	1	0	0
T12	7834	66	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	220398	0	0
T1	21409	183	0	0
T2	22360	0	0	0
T3	10214	22	0	0
T4	3142	49	0	0
T7	31480	91	0	0
T8	227259	603	0	0
T9	21351	206	0	0
T10	2639	53	0	0
T11	386942	0	0	0
T12	7834	68	0	0
T13	0	37	0	0
T14	0	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	220398	0	0
T1	21409	183	0	0
T2	22360	0	0	0
T3	10214	22	0	0
T4	3142	49	0	0
T7	31480	91	0	0
T8	227259	603	0	0
T9	21351	206	0	0
T10	2639	53	0	0
T11	386942	0	0	0
T12	7834	68	0	0
T13	0	37	0	0
T14	0	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	556646	0	0
T1	21409	188	0	0
T2	22360	0	0	0
T3	10214	22	0	0
T4	3142	53	0	0
T7	31480	129	0	0
T8	227259	754	0	0
T9	21351	207	0	0
T10	2639	55	0	0
T11	386942	0	0	0
T12	7834	71	0	0
T13	0	64	0	0
T14	0	34	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	220398	0	0
T1	21409	183	0	0
T2	22360	0	0	0
T3	10214	22	0	0
T4	3142	49	0	0
T7	31480	91	0	0
T8	227259	603	0	0
T9	21351	206	0	0
T10	2639	53	0	0
T11	386942	0	0	0
T12	7834	68	0	0
T13	0	37	0	0
T14	0	32	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	220834	0	0
GntImpliesValid_A	378853553	220834	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	220834	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	2812028	0	0
ReadyAndValidImplyGrant_A	378853553	220834	0	0
ReqAndReadyImplyGrant_A	378853553	220834	0	0
ReqImpliesValid_A	378853553	541651	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	220834	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	220834	0	0
T1	21409	183	0	0
T2	22360	1021	0	0
T3	10214	22	0	0
T4	3142	44	0	0
T7	31480	92	0	0
T8	227259	579	0	0
T9	21351	183	0	0
T10	2639	49	0	0
T11	386942	0	0	0
T12	7834	62	0	0
T13	0	21	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	220834	0	0
T1	21409	183	0	0
T2	22360	1021	0	0
T3	10214	22	0	0
T4	3142	44	0	0
T7	31480	92	0	0
T8	227259	579	0	0
T9	21351	183	0	0
T10	2639	49	0	0
T11	386942	0	0	0
T12	7834	62	0	0
T13	0	21	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	220834	0	0
T1	21409	183	0	0
T2	22360	1021	0	0
T3	10214	22	0	0
T4	3142	44	0	0
T7	31480	92	0	0
T8	227259	579	0	0
T9	21351	183	0	0
T10	2639	49	0	0
T11	386942	0	0	0
T12	7834	62	0	0
T13	0	21	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	2812028	0	0
T1	21409	182	0	0
T2	22360	5	0	0
T3	10214	149	0	0
T4	3142	43	0	0
T7	31480	640	0	0
T8	227259	4361	0	0
T9	21351	182	0	0
T10	2639	49	0	0
T11	386942	1	0	0
T12	7834	60	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	220834	0	0
T1	21409	183	0	0
T2	22360	1021	0	0
T3	10214	22	0	0
T4	3142	44	0	0
T7	31480	92	0	0
T8	227259	579	0	0
T9	21351	183	0	0
T10	2639	49	0	0
T11	386942	0	0	0
T12	7834	62	0	0
T13	0	21	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	220834	0	0
T1	21409	183	0	0
T2	22360	1021	0	0
T3	10214	22	0	0
T4	3142	44	0	0
T7	31480	92	0	0
T8	227259	579	0	0
T9	21351	183	0	0
T10	2639	49	0	0
T11	386942	0	0	0
T12	7834	62	0	0
T13	0	21	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	541651	0	0
T1	21409	189	0	0
T2	22360	2038	0	0
T3	10214	27	0	0
T4	3142	46	0	0
T7	31480	125	0	0
T8	227259	699	0	0
T9	21351	185	0	0
T10	2639	50	0	0
T11	386942	0	0	0
T12	7834	65	0	0
T13	0	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	220834	0	0
T1	21409	183	0	0
T2	22360	1021	0	0
T3	10214	22	0	0
T4	3142	44	0	0
T7	31480	92	0	0
T8	227259	579	0	0
T9	21351	183	0	0
T10	2639	49	0	0
T11	386942	0	0	0
T12	7834	62	0	0
T13	0	21	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	211243	0	0
GntImpliesValid_A	378853553	211243	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	211243	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	5010528	0	0
ReadyAndValidImplyGrant_A	378853553	211243	0	0
ReqAndReadyImplyGrant_A	378853553	211243	0	0
ReqImpliesValid_A	378853553	1144191	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	211243	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	211243	0	0
T1	21409	178	0	0
T2	22360	928	0	0
T3	10214	21	0	0
T4	3142	40	0	0
T7	31480	99	0	0
T8	227259	582	0	0
T9	21351	190	0	0
T10	2639	58	0	0
T11	386942	0	0	0
T12	7834	62	0	0
T13	0	30	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	211243	0	0
T1	21409	178	0	0
T2	22360	928	0	0
T3	10214	21	0	0
T4	3142	40	0	0
T7	31480	99	0	0
T8	227259	582	0	0
T9	21351	190	0	0
T10	2639	58	0	0
T11	386942	0	0	0
T12	7834	62	0	0
T13	0	30	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	211243	0	0
T1	21409	178	0	0
T2	22360	928	0	0
T3	10214	21	0	0
T4	3142	40	0	0
T7	31480	99	0	0
T8	227259	582	0	0
T9	21351	190	0	0
T10	2639	58	0	0
T11	386942	0	0	0
T12	7834	62	0	0
T13	0	30	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	5010528	0	0
T1	21409	3688	0	0
T2	22360	76	0	0
T3	10214	243	0	0
T4	3142	532	0	0
T7	31480	461	0	0
T8	227259	3841	0	0
T9	21351	2354	0	0
T10	2639	183	0	0
T11	386942	0	0	0
T12	7834	483	0	0
T13	0	1142	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	211243	0	0
T1	21409	178	0	0
T2	22360	928	0	0
T3	10214	21	0	0
T4	3142	40	0	0
T7	31480	99	0	0
T8	227259	582	0	0
T9	21351	190	0	0
T10	2639	58	0	0
T11	386942	0	0	0
T12	7834	62	0	0
T13	0	30	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	211243	0	0
T1	21409	178	0	0
T2	22360	928	0	0
T3	10214	21	0	0
T4	3142	40	0	0
T7	31480	99	0	0
T8	227259	582	0	0
T9	21351	190	0	0
T10	2639	58	0	0
T11	386942	0	0	0
T12	7834	62	0	0
T13	0	30	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	1144191	0	0
T1	21409	533	0	0
T2	22360	5710	0	0
T3	10214	29	0	0
T4	3142	177	0	0
T7	31480	123	0	0
T8	227259	634	0	0
T9	21351	253	0	0
T10	2639	75	0	0
T11	386942	0	0	0
T12	7834	107	0	0
T13	0	242	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	211243	0	0
T1	21409	178	0	0
T2	22360	928	0	0
T3	10214	21	0	0
T4	3142	40	0	0
T7	31480	99	0	0
T8	227259	582	0	0
T9	21351	190	0	0
T10	2639	58	0	0
T11	386942	0	0	0
T12	7834	62	0	0
T13	0	30	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T7
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T9
1	0	Not Covered
1	1	Covered	T1,T9,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T9

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T9,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	212567	0	0
GntImpliesValid_A	378853553	212567	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	212567	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	4470728	0	0
ReadyAndValidImplyGrant_A	378853553	212567	0	0
ReqAndReadyImplyGrant_A	378853553	212567	0	0
ReqImpliesValid_A	378853553	1001852	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	212567	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	212567	0	0
T1	21409	168	0	0
T2	22360	0	0	0
T3	10214	13	0	0
T4	3142	26	0	0
T7	31480	93	0	0
T8	227259	627	0	0
T9	21351	181	0	0
T10	2639	64	0	0
T11	386942	0	0	0
T12	7834	62	0	0
T13	0	30	0	0
T14	0	30	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	212567	0	0
T1	21409	168	0	0
T2	22360	0	0	0
T3	10214	13	0	0
T4	3142	26	0	0
T7	31480	93	0	0
T8	227259	627	0	0
T9	21351	181	0	0
T10	2639	64	0	0
T11	386942	0	0	0
T12	7834	62	0	0
T13	0	30	0	0
T14	0	30	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	212567	0	0
T1	21409	168	0	0
T2	22360	0	0	0
T3	10214	13	0	0
T4	3142	26	0	0
T7	31480	93	0	0
T8	227259	627	0	0
T9	21351	181	0	0
T10	2639	64	0	0
T11	386942	0	0	0
T12	7834	62	0	0
T13	0	30	0	0
T14	0	30	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	4470728	0	0
T1	21409	1316	0	0
T2	22360	0	0	0
T3	10214	186	0	0
T4	3142	202	0	0
T7	31480	460	0	0
T8	227259	4728	0	0
T9	21351	1042	0	0
T10	2639	203	0	0
T11	386942	0	0	0
T12	7834	563	0	0
T13	0	441	0	0
T14	0	244	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	212567	0	0
T1	21409	168	0	0
T2	22360	0	0	0
T3	10214	13	0	0
T4	3142	26	0	0
T7	31480	93	0	0
T8	227259	627	0	0
T9	21351	181	0	0
T10	2639	64	0	0
T11	386942	0	0	0
T12	7834	62	0	0
T13	0	30	0	0
T14	0	30	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	212567	0	0
T1	21409	168	0	0
T2	22360	0	0	0
T3	10214	13	0	0
T4	3142	26	0	0
T7	31480	93	0	0
T8	227259	627	0	0
T9	21351	181	0	0
T10	2639	64	0	0
T11	386942	0	0	0
T12	7834	62	0	0
T13	0	30	0	0
T14	0	30	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	1001852	0	0
T1	21409	235	0	0
T2	22360	0	0	0
T3	10214	13	0	0
T4	3142	36	0	0
T7	31480	113	0	0
T8	227259	802	0	0
T9	21351	205	0	0
T10	2639	84	0	0
T11	386942	0	0	0
T12	7834	105	0	0
T13	0	37	0	0
T14	0	77	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	212567	0	0
T1	21409	168	0	0
T2	22360	0	0	0
T3	10214	13	0	0
T4	3142	26	0	0
T7	31480	93	0	0
T8	227259	627	0	0
T9	21351	181	0	0
T10	2639	64	0	0
T11	386942	0	0	0
T12	7834	62	0	0
T13	0	30	0	0
T14	0	30	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	218804	0	0
GntImpliesValid_A	378853553	218804	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	218804	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	4943200	0	0
ReadyAndValidImplyGrant_A	378853553	218804	0	0
ReqAndReadyImplyGrant_A	378853553	218804	0	0
ReqImpliesValid_A	378853553	1175733	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	218804	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	218804	0	0
T1	21409	165	0	0
T2	22360	411	0	0
T3	10214	15	0	0
T4	3142	30	0	0
T7	31480	108	0	0
T8	227259	584	0	0
T9	21351	198	0	0
T10	2639	57	0	0
T11	386942	0	0	0
T12	7834	75	0	0
T13	0	42	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	218804	0	0
T1	21409	165	0	0
T2	22360	411	0	0
T3	10214	15	0	0
T4	3142	30	0	0
T7	31480	108	0	0
T8	227259	584	0	0
T9	21351	198	0	0
T10	2639	57	0	0
T11	386942	0	0	0
T12	7834	75	0	0
T13	0	42	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	218804	0	0
T1	21409	165	0	0
T2	22360	411	0	0
T3	10214	15	0	0
T4	3142	30	0	0
T7	31480	108	0	0
T8	227259	584	0	0
T9	21351	198	0	0
T10	2639	57	0	0
T11	386942	0	0	0
T12	7834	75	0	0
T13	0	42	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	4943200	0	0
T1	21409	971	0	0
T2	22360	27	0	0
T3	10214	194	0	0
T4	3142	147	0	0
T7	31480	579	0	0
T8	227259	12549	0	0
T9	21351	1591	0	0
T10	2639	174	0	0
T11	386942	0	0	0
T12	7834	1144	0	0
T13	0	2170	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	218804	0	0
T1	21409	165	0	0
T2	22360	411	0	0
T3	10214	15	0	0
T4	3142	30	0	0
T7	31480	108	0	0
T8	227259	584	0	0
T9	21351	198	0	0
T10	2639	57	0	0
T11	386942	0	0	0
T12	7834	75	0	0
T13	0	42	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	218804	0	0
T1	21409	165	0	0
T2	22360	411	0	0
T3	10214	15	0	0
T4	3142	30	0	0
T7	31480	108	0	0
T8	227259	584	0	0
T9	21351	198	0	0
T10	2639	57	0	0
T11	386942	0	0	0
T12	7834	75	0	0
T13	0	42	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	1175733	0	0
T1	21409	229	0	0
T2	22360	1843	0	0
T3	10214	28	0	0
T4	3142	50	0	0
T7	31480	133	0	0
T8	227259	1292	0	0
T9	21351	251	0	0
T10	2639	79	0	0
T11	386942	0	0	0
T12	7834	299	0	0
T13	0	315	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	218804	0	0
T1	21409	165	0	0
T2	22360	411	0	0
T3	10214	15	0	0
T4	3142	30	0	0
T7	31480	108	0	0
T8	227259	584	0	0
T9	21351	198	0	0
T10	2639	57	0	0
T11	386942	0	0	0
T12	7834	75	0	0
T13	0	42	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	211129	0	0
GntImpliesValid_A	378853553	211129	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	211129	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	5013016	0	0
ReadyAndValidImplyGrant_A	378853553	211129	0	0
ReqAndReadyImplyGrant_A	378853553	211129	0	0
ReqImpliesValid_A	378853553	1150329	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	211129	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	211129	0	0
T1	21409	187	0	0
T2	22360	465	0	0
T3	10214	18	0	0
T4	3142	42	0	0
T7	31480	107	0	0
T8	227259	575	0	0
T9	21351	176	0	0
T10	2639	43	0	0
T11	386942	0	0	0
T12	7834	76	0	0
T13	0	29	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	211129	0	0
T1	21409	187	0	0
T2	22360	465	0	0
T3	10214	18	0	0
T4	3142	42	0	0
T7	31480	107	0	0
T8	227259	575	0	0
T9	21351	176	0	0
T10	2639	43	0	0
T11	386942	0	0	0
T12	7834	76	0	0
T13	0	29	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	211129	0	0
T1	21409	187	0	0
T2	22360	465	0	0
T3	10214	18	0	0
T4	3142	42	0	0
T7	31480	107	0	0
T8	227259	575	0	0
T9	21351	176	0	0
T10	2639	43	0	0
T11	386942	0	0	0
T12	7834	76	0	0
T13	0	29	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	5013016	0	0
T1	21409	2697	0	0
T2	22360	14	0	0
T3	10214	207	0	0
T4	3142	458	0	0
T7	31480	503	0	0
T8	227259	8327	0	0
T9	21351	1141	0	0
T10	2639	137	0	0
T11	386942	0	0	0
T12	7834	729	0	0
T13	0	262	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	211129	0	0
T1	21409	187	0	0
T2	22360	465	0	0
T3	10214	18	0	0
T4	3142	42	0	0
T7	31480	107	0	0
T8	227259	575	0	0
T9	21351	176	0	0
T10	2639	43	0	0
T11	386942	0	0	0
T12	7834	76	0	0
T13	0	29	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	211129	0	0
T1	21409	187	0	0
T2	22360	465	0	0
T3	10214	18	0	0
T4	3142	42	0	0
T7	31480	107	0	0
T8	227259	575	0	0
T9	21351	176	0	0
T10	2639	43	0	0
T11	386942	0	0	0
T12	7834	76	0	0
T13	0	29	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	1150329	0	0
T1	21409	468	0	0
T2	22360	2315	0	0
T3	10214	18	0	0
T4	3142	145	0	0
T7	31480	128	0	0
T8	227259	814	0	0
T9	21351	215	0	0
T10	2639	53	0	0
T11	386942	0	0	0
T12	7834	205	0	0
T13	0	76	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	211129	0	0
T1	21409	187	0	0
T2	22360	465	0	0
T3	10214	18	0	0
T4	3142	42	0	0
T7	31480	107	0	0
T8	227259	575	0	0
T9	21351	176	0	0
T10	2639	43	0	0
T11	386942	0	0	0
T12	7834	76	0	0
T13	0	29	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	221121	0	0
GntImpliesValid_A	378853553	221121	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	221121	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	2816862	0	0
ReadyAndValidImplyGrant_A	378853553	221121	0	0
ReqAndReadyImplyGrant_A	378853553	221121	0	0
ReqImpliesValid_A	378853553	533456	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	221121	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	221121	0	0
T1	21409	207	0	0
T2	22360	1085	0	0
T3	10214	19	0	0
T4	3142	31	0	0
T7	31480	99	0	0
T8	227259	599	0	0
T9	21351	180	0	0
T10	2639	49	0	0
T11	386942	0	0	0
T12	7834	64	0	0
T13	0	45	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	221121	0	0
T1	21409	207	0	0
T2	22360	1085	0	0
T3	10214	19	0	0
T4	3142	31	0	0
T7	31480	99	0	0
T8	227259	599	0	0
T9	21351	180	0	0
T10	2639	49	0	0
T11	386942	0	0	0
T12	7834	64	0	0
T13	0	45	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	221121	0	0
T1	21409	207	0	0
T2	22360	1085	0	0
T3	10214	19	0	0
T4	3142	31	0	0
T7	31480	99	0	0
T8	227259	599	0	0
T9	21351	180	0	0
T10	2639	49	0	0
T11	386942	0	0	0
T12	7834	64	0	0
T13	0	45	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	2816862	0	0
T1	21409	205	0	0
T2	22360	13	0	0
T3	10214	138	0	0
T4	3142	32	0	0
T7	31480	688	0	0
T8	227259	4428	0	0
T9	21351	181	0	0
T10	2639	47	0	0
T11	386942	1	0	0
T12	7834	62	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	221121	0	0
T1	21409	207	0	0
T2	22360	1085	0	0
T3	10214	19	0	0
T4	3142	31	0	0
T7	31480	99	0	0
T8	227259	599	0	0
T9	21351	180	0	0
T10	2639	49	0	0
T11	386942	0	0	0
T12	7834	64	0	0
T13	0	45	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	221121	0	0
T1	21409	207	0	0
T2	22360	1085	0	0
T3	10214	19	0	0
T4	3142	31	0	0
T7	31480	99	0	0
T8	227259	599	0	0
T9	21351	180	0	0
T10	2639	49	0	0
T11	386942	0	0	0
T12	7834	64	0	0
T13	0	45	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	533456	0	0
T1	21409	214	0	0
T2	22360	2158	0	0
T3	10214	19	0	0
T4	3142	31	0	0
T7	31480	123	0	0
T8	227259	714	0	0
T9	21351	180	0	0
T10	2639	52	0	0
T11	386942	0	0	0
T12	7834	67	0	0
T13	0	70	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	221121	0	0
T1	21409	207	0	0
T2	22360	1085	0	0
T3	10214	19	0	0
T4	3142	31	0	0
T7	31480	99	0	0
T8	227259	599	0	0
T9	21351	180	0	0
T10	2639	49	0	0
T11	386942	0	0	0
T12	7834	64	0	0
T13	0	45	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	220950	0	0
GntImpliesValid_A	378853553	220950	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	220950	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	2768970	0	0
ReadyAndValidImplyGrant_A	378853553	220950	0	0
ReqAndReadyImplyGrant_A	378853553	220950	0	0
ReqImpliesValid_A	378853553	529469	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	220950	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	220950	0	0
T1	21409	436	0	0
T2	22360	0	0	0
T3	10214	20	0	0
T4	3142	46	0	0
T7	31480	119	0	0
T8	227259	589	0	0
T9	21351	195	0	0
T10	2639	45	0	0
T11	386942	0	0	0
T12	7834	60	0	0
T13	0	28	0	0
T14	0	26	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	220950	0	0
T1	21409	436	0	0
T2	22360	0	0	0
T3	10214	20	0	0
T4	3142	46	0	0
T7	31480	119	0	0
T8	227259	589	0	0
T9	21351	195	0	0
T10	2639	45	0	0
T11	386942	0	0	0
T12	7834	60	0	0
T13	0	28	0	0
T14	0	26	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	220950	0	0
T1	21409	436	0	0
T2	22360	0	0	0
T3	10214	20	0	0
T4	3142	46	0	0
T7	31480	119	0	0
T8	227259	589	0	0
T9	21351	195	0	0
T10	2639	45	0	0
T11	386942	0	0	0
T12	7834	60	0	0
T13	0	28	0	0
T14	0	26	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	2768970	0	0
T1	21409	414	0	0
T2	22360	1	0	0
T3	10214	143	0	0
T4	3142	46	0	0
T7	31480	834	0	0
T8	227259	4394	0	0
T9	21351	195	0	0
T10	2639	45	0	0
T11	386942	1	0	0
T12	7834	60	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	220950	0	0
T1	21409	436	0	0
T2	22360	0	0	0
T3	10214	20	0	0
T4	3142	46	0	0
T7	31480	119	0	0
T8	227259	589	0	0
T9	21351	195	0	0
T10	2639	45	0	0
T11	386942	0	0	0
T12	7834	60	0	0
T13	0	28	0	0
T14	0	26	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	220950	0	0
T1	21409	436	0	0
T2	22360	0	0	0
T3	10214	20	0	0
T4	3142	46	0	0
T7	31480	119	0	0
T8	227259	589	0	0
T9	21351	195	0	0
T10	2639	45	0	0
T11	386942	0	0	0
T12	7834	60	0	0
T13	0	28	0	0
T14	0	26	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	529469	0	0
T1	21409	463	0	0
T2	22360	0	0	0
T3	10214	30	0	0
T4	3142	47	0	0
T7	31480	175	0	0
T8	227259	706	0	0
T9	21351	196	0	0
T10	2639	46	0	0
T11	386942	0	0	0
T12	7834	61	0	0
T13	0	28	0	0
T14	0	28	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	220950	0	0
T1	21409	436	0	0
T2	22360	0	0	0
T3	10214	20	0	0
T4	3142	46	0	0
T7	31480	119	0	0
T8	227259	589	0	0
T9	21351	195	0	0
T10	2639	45	0	0
T11	386942	0	0	0
T12	7834	60	0	0
T13	0	28	0	0
T14	0	26	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T7
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T9,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T9,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	226347	0	0
GntImpliesValid_A	378853553	226347	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	226347	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	2814837	0	0
ReadyAndValidImplyGrant_A	378853553	226347	0	0
ReqAndReadyImplyGrant_A	378853553	226347	0	0
ReqImpliesValid_A	378853553	567280	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	226347	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	226347	0	0
T1	21409	166	0	0
T2	22360	0	0	0
T3	10214	21	0	0
T4	3142	33	0	0
T7	31480	105	0	0
T8	227259	602	0	0
T9	21351	185	0	0
T10	2639	41	0	0
T11	386942	0	0	0
T12	7834	81	0	0
T13	0	38	0	0
T14	0	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	226347	0	0
T1	21409	166	0	0
T2	22360	0	0	0
T3	10214	21	0	0
T4	3142	33	0	0
T7	31480	105	0	0
T8	227259	602	0	0
T9	21351	185	0	0
T10	2639	41	0	0
T11	386942	0	0	0
T12	7834	81	0	0
T13	0	38	0	0
T14	0	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	226347	0	0
T1	21409	166	0	0
T2	22360	0	0	0
T3	10214	21	0	0
T4	3142	33	0	0
T7	31480	105	0	0
T8	227259	602	0	0
T9	21351	185	0	0
T10	2639	41	0	0
T11	386942	0	0	0
T12	7834	81	0	0
T13	0	38	0	0
T14	0	38	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	2814837	0	0
T1	21409	170	0	0
T2	22360	1	0	0
T3	10214	181	0	0
T4	3142	33	0	0
T7	31480	781	0	0
T8	227259	4528	0	0
T9	21351	184	0	0
T10	2639	39	0	0
T11	386942	1	0	0
T12	7834	78	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	226347	0	0
T1	21409	166	0	0
T2	22360	0	0	0
T3	10214	21	0	0
T4	3142	33	0	0
T7	31480	105	0	0
T8	227259	602	0	0
T9	21351	185	0	0
T10	2639	41	0	0
T11	386942	0	0	0
T12	7834	81	0	0
T13	0	38	0	0
T14	0	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	226347	0	0
T1	21409	166	0	0
T2	22360	0	0	0
T3	10214	21	0	0
T4	3142	33	0	0
T7	31480	105	0	0
T8	227259	602	0	0
T9	21351	185	0	0
T10	2639	41	0	0
T11	386942	0	0	0
T12	7834	81	0	0
T13	0	38	0	0
T14	0	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	567280	0	0
T1	21409	167	0	0
T2	22360	0	0	0
T3	10214	21	0	0
T4	3142	34	0	0
T7	31480	163	0	0
T8	227259	714	0	0
T9	21351	187	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	85	0	0
T13	0	42	0	0
T14	0	41	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	226347	0	0
T1	21409	166	0	0
T2	22360	0	0	0
T3	10214	21	0	0
T4	3142	33	0	0
T7	31480	105	0	0
T8	227259	602	0	0
T9	21351	185	0	0
T10	2639	41	0	0
T11	386942	0	0	0
T12	7834	81	0	0
T13	0	38	0	0
T14	0	38	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T7
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T9,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T9,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	208513	0	0
GntImpliesValid_A	378853553	208513	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	208513	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	2778110	0	0
ReadyAndValidImplyGrant_A	378853553	208513	0	0
ReqAndReadyImplyGrant_A	378853553	208513	0	0
ReqImpliesValid_A	378853553	482047	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	208513	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	208513	0	0
T1	21409	211	0	0
T2	22360	0	0	0
T3	10214	19	0	0
T4	3142	32	0	0
T7	31480	97	0	0
T8	227259	629	0	0
T9	21351	184	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	75	0	0
T13	0	46	0	0
T14	0	42	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	208513	0	0
T1	21409	211	0	0
T2	22360	0	0	0
T3	10214	19	0	0
T4	3142	32	0	0
T7	31480	97	0	0
T8	227259	629	0	0
T9	21351	184	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	75	0	0
T13	0	46	0	0
T14	0	42	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	208513	0	0
T1	21409	211	0	0
T2	22360	0	0	0
T3	10214	19	0	0
T4	3142	32	0	0
T7	31480	97	0	0
T8	227259	629	0	0
T9	21351	184	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	75	0	0
T13	0	46	0	0
T14	0	42	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	2778110	0	0
T1	21409	208	0	0
T2	22360	1	0	0
T3	10214	159	0	0
T4	3142	33	0	0
T7	31480	735	0	0
T8	227259	4819	0	0
T9	21351	182	0	0
T10	2639	44	0	0
T11	386942	1	0	0
T12	7834	74	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	208513	0	0
T1	21409	211	0	0
T2	22360	0	0	0
T3	10214	19	0	0
T4	3142	32	0	0
T7	31480	97	0	0
T8	227259	629	0	0
T9	21351	184	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	75	0	0
T13	0	46	0	0
T14	0	42	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	208513	0	0
T1	21409	211	0	0
T2	22360	0	0	0
T3	10214	19	0	0
T4	3142	32	0	0
T7	31480	97	0	0
T8	227259	629	0	0
T9	21351	184	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	75	0	0
T13	0	46	0	0
T14	0	42	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	482047	0	0
T1	21409	219	0	0
T2	22360	0	0	0
T3	10214	19	0	0
T4	3142	32	0	0
T7	31480	206	0	0
T8	227259	804	0	0
T9	21351	187	0	0
T10	2639	45	0	0
T11	386942	0	0	0
T12	7834	77	0	0
T13	0	70	0	0
T14	0	47	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	208513	0	0
T1	21409	211	0	0
T2	22360	0	0	0
T3	10214	19	0	0
T4	3142	32	0	0
T7	31480	97	0	0
T8	227259	629	0	0
T9	21351	184	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	75	0	0
T13	0	46	0	0
T14	0	42	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	211152	0	0
GntImpliesValid_A	378853553	211152	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	211152	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	2847665	0	0
ReadyAndValidImplyGrant_A	378853553	211152	0	0
ReqAndReadyImplyGrant_A	378853553	211152	0	0
ReqImpliesValid_A	378853553	525454	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	211152	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	211152	0	0
T1	21409	160	0	0
T2	22360	460	0	0
T3	10214	12	0	0
T4	3142	38	0	0
T7	31480	91	0	0
T8	227259	611	0	0
T9	21351	185	0	0
T10	2639	55	0	0
T11	386942	0	0	0
T12	7834	69	0	0
T13	0	45	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	211152	0	0
T1	21409	160	0	0
T2	22360	460	0	0
T3	10214	12	0	0
T4	3142	38	0	0
T7	31480	91	0	0
T8	227259	611	0	0
T9	21351	185	0	0
T10	2639	55	0	0
T11	386942	0	0	0
T12	7834	69	0	0
T13	0	45	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	211152	0	0
T1	21409	160	0	0
T2	22360	460	0	0
T3	10214	12	0	0
T4	3142	38	0	0
T7	31480	91	0	0
T8	227259	611	0	0
T9	21351	185	0	0
T10	2639	55	0	0
T11	386942	0	0	0
T12	7834	69	0	0
T13	0	45	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	2847665	0	0
T1	21409	162	0	0
T2	22360	8	0	0
T3	10214	80	0	0
T4	3142	38	0	0
T7	31480	707	0	0
T8	227259	4747	0	0
T9	21351	182	0	0
T10	2639	48	0	0
T11	386942	1	0	0
T12	7834	68	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	211152	0	0
T1	21409	160	0	0
T2	22360	460	0	0
T3	10214	12	0	0
T4	3142	38	0	0
T7	31480	91	0	0
T8	227259	611	0	0
T9	21351	185	0	0
T10	2639	55	0	0
T11	386942	0	0	0
T12	7834	69	0	0
T13	0	45	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	211152	0	0
T1	21409	160	0	0
T2	22360	460	0	0
T3	10214	12	0	0
T4	3142	38	0	0
T7	31480	91	0	0
T8	227259	611	0	0
T9	21351	185	0	0
T10	2639	55	0	0
T11	386942	0	0	0
T12	7834	69	0	0
T13	0	45	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	525454	0	0
T1	21409	163	0	0
T2	22360	913	0	0
T3	10214	12	0	0
T4	3142	39	0	0
T7	31480	99	0	0
T8	227259	699	0	0
T9	21351	189	0	0
T10	2639	63	0	0
T11	386942	0	0	0
T12	7834	71	0	0
T13	0	107	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	211152	0	0
T1	21409	160	0	0
T2	22360	460	0	0
T3	10214	12	0	0
T4	3142	38	0	0
T7	31480	91	0	0
T8	227259	611	0	0
T9	21351	185	0	0
T10	2639	55	0	0
T11	386942	0	0	0
T12	7834	69	0	0
T13	0	45	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	216272	0	0
GntImpliesValid_A	378853553	216272	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	216272	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	2716907	0	0
ReadyAndValidImplyGrant_A	378853553	216272	0	0
ReqAndReadyImplyGrant_A	378853553	216272	0	0
ReqImpliesValid_A	378853553	527570	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	216272	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	216272	0	0
T1	21409	172	0	0
T2	22360	0	0	0
T3	10214	24	0	0
T4	3142	35	0	0
T7	31480	106	0	0
T8	227259	568	0	0
T9	21351	212	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	73	0	0
T13	0	40	0	0
T14	0	55	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	216272	0	0
T1	21409	172	0	0
T2	22360	0	0	0
T3	10214	24	0	0
T4	3142	35	0	0
T7	31480	106	0	0
T8	227259	568	0	0
T9	21351	212	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	73	0	0
T13	0	40	0	0
T14	0	55	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	216272	0	0
T1	21409	172	0	0
T2	22360	0	0	0
T3	10214	24	0	0
T4	3142	35	0	0
T7	31480	106	0	0
T8	227259	568	0	0
T9	21351	212	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	73	0	0
T13	0	40	0	0
T14	0	55	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	2716907	0	0
T1	21409	176	0	0
T2	22360	1	0	0
T3	10214	185	0	0
T4	3142	32	0	0
T7	31480	843	0	0
T8	227259	4476	0	0
T9	21351	213	0	0
T10	2639	42	0	0
T11	386942	1	0	0
T12	7834	72	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	216272	0	0
T1	21409	172	0	0
T2	22360	0	0	0
T3	10214	24	0	0
T4	3142	35	0	0
T7	31480	106	0	0
T8	227259	568	0	0
T9	21351	212	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	73	0	0
T13	0	40	0	0
T14	0	55	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	216272	0	0
T1	21409	172	0	0
T2	22360	0	0	0
T3	10214	24	0	0
T4	3142	35	0	0
T7	31480	106	0	0
T8	227259	568	0	0
T9	21351	212	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	73	0	0
T13	0	40	0	0
T14	0	55	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	527570	0	0
T1	21409	173	0	0
T2	22360	0	0	0
T3	10214	45	0	0
T4	3142	39	0	0
T7	31480	128	0	0
T8	227259	650	0	0
T9	21351	212	0	0
T10	2639	47	0	0
T11	386942	0	0	0
T12	7834	75	0	0
T13	0	100	0	0
T14	0	57	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	216272	0	0
T1	21409	172	0	0
T2	22360	0	0	0
T3	10214	24	0	0
T4	3142	35	0	0
T7	31480	106	0	0
T8	227259	568	0	0
T9	21351	212	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	73	0	0
T13	0	40	0	0
T14	0	55	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	215860	0	0
GntImpliesValid_A	378853553	215860	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	215860	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	2762617	0	0
ReadyAndValidImplyGrant_A	378853553	215860	0	0
ReqAndReadyImplyGrant_A	378853553	215860	0	0
ReqImpliesValid_A	378853553	542330	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	215860	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	215860	0	0
T1	21409	191	0	0
T2	22360	480	0	0
T3	10214	20	0	0
T4	3142	23	0	0
T7	31480	83	0	0
T8	227259	588	0	0
T9	21351	222	0	0
T10	2639	53	0	0
T11	386942	0	0	0
T12	7834	61	0	0
T13	0	42	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	215860	0	0
T1	21409	191	0	0
T2	22360	480	0	0
T3	10214	20	0	0
T4	3142	23	0	0
T7	31480	83	0	0
T8	227259	588	0	0
T9	21351	222	0	0
T10	2639	53	0	0
T11	386942	0	0	0
T12	7834	61	0	0
T13	0	42	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	215860	0	0
T1	21409	191	0	0
T2	22360	480	0	0
T3	10214	20	0	0
T4	3142	23	0	0
T7	31480	83	0	0
T8	227259	588	0	0
T9	21351	222	0	0
T10	2639	53	0	0
T11	386942	0	0	0
T12	7834	61	0	0
T13	0	42	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	2762617	0	0
T1	21409	193	0	0
T2	22360	2	0	0
T3	10214	153	0	0
T4	3142	24	0	0
T7	31480	696	0	0
T8	227259	4426	0	0
T9	21351	220	0	0
T10	2639	50	0	0
T11	386942	1	0	0
T12	7834	58	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	215860	0	0
T1	21409	191	0	0
T2	22360	480	0	0
T3	10214	20	0	0
T4	3142	23	0	0
T7	31480	83	0	0
T8	227259	588	0	0
T9	21351	222	0	0
T10	2639	53	0	0
T11	386942	0	0	0
T12	7834	61	0	0
T13	0	42	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	215860	0	0
T1	21409	191	0	0
T2	22360	480	0	0
T3	10214	20	0	0
T4	3142	23	0	0
T7	31480	83	0	0
T8	227259	588	0	0
T9	21351	222	0	0
T10	2639	53	0	0
T11	386942	0	0	0
T12	7834	61	0	0
T13	0	42	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	542330	0	0
T1	21409	194	0	0
T2	22360	959	0	0
T3	10214	28	0	0
T4	3142	23	0	0
T7	31480	123	0	0
T8	227259	742	0	0
T9	21351	225	0	0
T10	2639	57	0	0
T11	386942	0	0	0
T12	7834	65	0	0
T13	0	111	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	215860	0	0
T1	21409	191	0	0
T2	22360	480	0	0
T3	10214	20	0	0
T4	3142	23	0	0
T7	31480	83	0	0
T8	227259	588	0	0
T9	21351	222	0	0
T10	2639	53	0	0
T11	386942	0	0	0
T12	7834	61	0	0
T13	0	42	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	208316	0	0
GntImpliesValid_A	378853553	208316	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	208316	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	2740454	0	0
ReadyAndValidImplyGrant_A	378853553	208316	0	0
ReqAndReadyImplyGrant_A	378853553	208316	0	0
ReqImpliesValid_A	378853553	524728	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	208316	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	208316	0	0
T1	21409	168	0	0
T2	22360	0	0	0
T3	10214	26	0	0
T4	3142	44	0	0
T7	31480	78	0	0
T8	227259	587	0	0
T9	21351	207	0	0
T10	2639	41	0	0
T11	386942	0	0	0
T12	7834	63	0	0
T13	0	28	0	0
T14	0	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	208316	0	0
T1	21409	168	0	0
T2	22360	0	0	0
T3	10214	26	0	0
T4	3142	44	0	0
T7	31480	78	0	0
T8	227259	587	0	0
T9	21351	207	0	0
T10	2639	41	0	0
T11	386942	0	0	0
T12	7834	63	0	0
T13	0	28	0	0
T14	0	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	208316	0	0
T1	21409	168	0	0
T2	22360	0	0	0
T3	10214	26	0	0
T4	3142	44	0	0
T7	31480	78	0	0
T8	227259	587	0	0
T9	21351	207	0	0
T10	2639	41	0	0
T11	386942	0	0	0
T12	7834	63	0	0
T13	0	28	0	0
T14	0	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	2740454	0	0
T1	21409	168	0	0
T2	22360	1	0	0
T3	10214	178	0	0
T4	3142	41	0	0
T7	31480	623	0	0
T8	227259	4512	0	0
T9	21351	205	0	0
T10	2639	39	0	0
T11	386942	1	0	0
T12	7834	61	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	208316	0	0
T1	21409	168	0	0
T2	22360	0	0	0
T3	10214	26	0	0
T4	3142	44	0	0
T7	31480	78	0	0
T8	227259	587	0	0
T9	21351	207	0	0
T10	2639	41	0	0
T11	386942	0	0	0
T12	7834	63	0	0
T13	0	28	0	0
T14	0	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	208316	0	0
T1	21409	168	0	0
T2	22360	0	0	0
T3	10214	26	0	0
T4	3142	44	0	0
T7	31480	78	0	0
T8	227259	587	0	0
T9	21351	207	0	0
T10	2639	41	0	0
T11	386942	0	0	0
T12	7834	63	0	0
T13	0	28	0	0
T14	0	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	524728	0	0
T1	21409	173	0	0
T2	22360	0	0	0
T3	10214	31	0	0
T4	3142	48	0	0
T7	31480	101	0	0
T8	227259	619	0	0
T9	21351	210	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	66	0	0
T13	0	33	0	0
T14	0	45	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	208316	0	0
T1	21409	168	0	0
T2	22360	0	0	0
T3	10214	26	0	0
T4	3142	44	0	0
T7	31480	78	0	0
T8	227259	587	0	0
T9	21351	207	0	0
T10	2639	41	0	0
T11	386942	0	0	0
T12	7834	63	0	0
T13	0	28	0	0
T14	0	40	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	240939	0	0
GntImpliesValid_A	378853553	240939	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	240939	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	2908345	0	0
ReadyAndValidImplyGrant_A	378853553	240939	0	0
ReqAndReadyImplyGrant_A	378853553	240939	0	0
ReqImpliesValid_A	378853553	603964	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	240939	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	240939	0	0
T1	21409	213	0	0
T2	22360	0	0	0
T3	10214	33	0	0
T4	3142	37	0	0
T7	31480	113	0	0
T8	227259	667	0	0
T9	21351	200	0	0
T10	2639	45	0	0
T11	386942	0	0	0
T12	7834	124	0	0
T13	0	38	0	0
T14	0	35	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	240939	0	0
T1	21409	213	0	0
T2	22360	0	0	0
T3	10214	33	0	0
T4	3142	37	0	0
T7	31480	113	0	0
T8	227259	667	0	0
T9	21351	200	0	0
T10	2639	45	0	0
T11	386942	0	0	0
T12	7834	124	0	0
T13	0	38	0	0
T14	0	35	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	240939	0	0
T1	21409	213	0	0
T2	22360	0	0	0
T3	10214	33	0	0
T4	3142	37	0	0
T7	31480	113	0	0
T8	227259	667	0	0
T9	21351	200	0	0
T10	2639	45	0	0
T11	386942	0	0	0
T12	7834	124	0	0
T13	0	38	0	0
T14	0	35	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	2908345	0	0
T1	21409	215	0	0
T2	22360	1	0	0
T3	10214	265	0	0
T4	3142	37	0	0
T7	31480	846	0	0
T8	227259	5136	0	0
T9	21351	201	0	0
T10	2639	43	0	0
T11	386942	1	0	0
T12	7834	120	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	240939	0	0
T1	21409	213	0	0
T2	22360	0	0	0
T3	10214	33	0	0
T4	3142	37	0	0
T7	31480	113	0	0
T8	227259	667	0	0
T9	21351	200	0	0
T10	2639	45	0	0
T11	386942	0	0	0
T12	7834	124	0	0
T13	0	38	0	0
T14	0	35	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	240939	0	0
T1	21409	213	0	0
T2	22360	0	0	0
T3	10214	33	0	0
T4	3142	37	0	0
T7	31480	113	0	0
T8	227259	667	0	0
T9	21351	200	0	0
T10	2639	45	0	0
T11	386942	0	0	0
T12	7834	124	0	0
T13	0	38	0	0
T14	0	35	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	603964	0	0
T1	21409	216	0	0
T2	22360	0	0	0
T3	10214	53	0	0
T4	3142	38	0	0
T7	31480	171	0	0
T8	227259	768	0	0
T9	21351	200	0	0
T10	2639	48	0	0
T11	386942	0	0	0
T12	7834	129	0	0
T13	0	41	0	0
T14	0	37	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	240939	0	0
T1	21409	213	0	0
T2	22360	0	0	0
T3	10214	33	0	0
T4	3142	37	0	0
T7	31480	113	0	0
T8	227259	667	0	0
T9	21351	200	0	0
T10	2639	45	0	0
T11	386942	0	0	0
T12	7834	124	0	0
T13	0	38	0	0
T14	0	35	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	218366	0	0
GntImpliesValid_A	378853553	218366	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	218366	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	2831050	0	0
ReadyAndValidImplyGrant_A	378853553	218366	0	0
ReqAndReadyImplyGrant_A	378853553	218366	0	0
ReqImpliesValid_A	378853553	574338	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	218366	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	218366	0	0
T1	21409	144	0	0
T2	22360	989	0	0
T3	10214	14	0	0
T4	3142	36	0	0
T7	31480	93	0	0
T8	227259	602	0	0
T9	21351	195	0	0
T10	2639	45	0	0
T11	386942	0	0	0
T12	7834	56	0	0
T13	0	37	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	218366	0	0
T1	21409	144	0	0
T2	22360	989	0	0
T3	10214	14	0	0
T4	3142	36	0	0
T7	31480	93	0	0
T8	227259	602	0	0
T9	21351	195	0	0
T10	2639	45	0	0
T11	386942	0	0	0
T12	7834	56	0	0
T13	0	37	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	218366	0	0
T1	21409	144	0	0
T2	22360	989	0	0
T3	10214	14	0	0
T4	3142	36	0	0
T7	31480	93	0	0
T8	227259	602	0	0
T9	21351	195	0	0
T10	2639	45	0	0
T11	386942	0	0	0
T12	7834	56	0	0
T13	0	37	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	2831050	0	0
T1	21409	144	0	0
T2	22360	3	0	0
T3	10214	90	0	0
T4	3142	37	0	0
T7	31480	676	0	0
T8	227259	4755	0	0
T9	21351	192	0	0
T10	2639	43	0	0
T11	386942	1	0	0
T12	7834	57	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	218366	0	0
T1	21409	144	0	0
T2	22360	989	0	0
T3	10214	14	0	0
T4	3142	36	0	0
T7	31480	93	0	0
T8	227259	602	0	0
T9	21351	195	0	0
T10	2639	45	0	0
T11	386942	0	0	0
T12	7834	56	0	0
T13	0	37	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	218366	0	0
T1	21409	144	0	0
T2	22360	989	0	0
T3	10214	14	0	0
T4	3142	36	0	0
T7	31480	93	0	0
T8	227259	602	0	0
T9	21351	195	0	0
T10	2639	45	0	0
T11	386942	0	0	0
T12	7834	56	0	0
T13	0	37	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	574338	0	0
T1	21409	149	0	0
T2	22360	1976	0	0
T3	10214	23	0	0
T4	3142	36	0	0
T7	31480	109	0	0
T8	227259	677	0	0
T9	21351	199	0	0
T10	2639	48	0	0
T11	386942	0	0	0
T12	7834	56	0	0
T13	0	56	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	218366	0	0
T1	21409	144	0	0
T2	22360	989	0	0
T3	10214	14	0	0
T4	3142	36	0	0
T7	31480	93	0	0
T8	227259	602	0	0
T9	21351	195	0	0
T10	2639	45	0	0
T11	386942	0	0	0
T12	7834	56	0	0
T13	0	37	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T7
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T9,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T9,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	224927	0	0
GntImpliesValid_A	378853553	224927	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	224927	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	2791508	0	0
ReadyAndValidImplyGrant_A	378853553	224927	0	0
ReqAndReadyImplyGrant_A	378853553	224927	0	0
ReqImpliesValid_A	378853553	555097	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	224927	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	224927	0	0
T1	21409	181	0	0
T2	22360	0	0	0
T3	10214	30	0	0
T4	3142	34	0	0
T7	31480	95	0	0
T8	227259	611	0	0
T9	21351	192	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	65	0	0
T13	0	32	0	0
T14	0	30	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	224927	0	0
T1	21409	181	0	0
T2	22360	0	0	0
T3	10214	30	0	0
T4	3142	34	0	0
T7	31480	95	0	0
T8	227259	611	0	0
T9	21351	192	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	65	0	0
T13	0	32	0	0
T14	0	30	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	224927	0	0
T1	21409	181	0	0
T2	22360	0	0	0
T3	10214	30	0	0
T4	3142	34	0	0
T7	31480	95	0	0
T8	227259	611	0	0
T9	21351	192	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	65	0	0
T13	0	32	0	0
T14	0	30	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	2791508	0	0
T1	21409	181	0	0
T2	22360	1	0	0
T3	10214	182	0	0
T4	3142	35	0	0
T7	31480	617	0	0
T8	227259	4737	0	0
T9	21351	192	0	0
T10	2639	41	0	0
T11	386942	1	0	0
T12	7834	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	224927	0	0
T1	21409	181	0	0
T2	22360	0	0	0
T3	10214	30	0	0
T4	3142	34	0	0
T7	31480	95	0	0
T8	227259	611	0	0
T9	21351	192	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	65	0	0
T13	0	32	0	0
T14	0	30	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	224927	0	0
T1	21409	181	0	0
T2	22360	0	0	0
T3	10214	30	0	0
T4	3142	34	0	0
T7	31480	95	0	0
T8	227259	611	0	0
T9	21351	192	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	65	0	0
T13	0	32	0	0
T14	0	30	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	555097	0	0
T1	21409	186	0	0
T2	22360	0	0	0
T3	10214	30	0	0
T4	3142	34	0	0
T7	31480	153	0	0
T8	227259	756	0	0
T9	21351	193	0	0
T10	2639	48	0	0
T11	386942	0	0	0
T12	7834	67	0	0
T13	0	46	0	0
T14	0	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	224927	0	0
T1	21409	181	0	0
T2	22360	0	0	0
T3	10214	30	0	0
T4	3142	34	0	0
T7	31480	95	0	0
T8	227259	611	0	0
T9	21351	192	0	0
T10	2639	44	0	0
T11	386942	0	0	0
T12	7834	65	0	0
T13	0	32	0	0
T14	0	30	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	215286	0	0
GntImpliesValid_A	378853553	215286	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	215286	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	2780505	0	0
ReadyAndValidImplyGrant_A	378853553	215286	0	0
ReqAndReadyImplyGrant_A	378853553	215286	0	0
ReqImpliesValid_A	378853553	533574	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	215286	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	215286	0	0
T1	21409	202	0	0
T2	22360	0	0	0
T3	10214	13	0	0
T4	3142	45	0	0
T7	31480	105	0	0
T8	227259	577	0	0
T9	21351	201	0	0
T10	2639	36	0	0
T11	386942	0	0	0
T12	7834	47	0	0
T13	0	36	0	0
T14	0	54	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	215286	0	0
T1	21409	202	0	0
T2	22360	0	0	0
T3	10214	13	0	0
T4	3142	45	0	0
T7	31480	105	0	0
T8	227259	577	0	0
T9	21351	201	0	0
T10	2639	36	0	0
T11	386942	0	0	0
T12	7834	47	0	0
T13	0	36	0	0
T14	0	54	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	215286	0	0
T1	21409	202	0	0
T2	22360	0	0	0
T3	10214	13	0	0
T4	3142	45	0	0
T7	31480	105	0	0
T8	227259	577	0	0
T9	21351	201	0	0
T10	2639	36	0	0
T11	386942	0	0	0
T12	7834	47	0	0
T13	0	36	0	0
T14	0	54	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	2780505	0	0
T1	21409	200	0	0
T2	22360	1	0	0
T3	10214	83	0	0
T4	3142	41	0	0
T7	31480	717	0	0
T8	227259	4367	0	0
T9	21351	201	0	0
T10	2639	34	0	0
T11	386942	1	0	0
T12	7834	48	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	215286	0	0
T1	21409	202	0	0
T2	22360	0	0	0
T3	10214	13	0	0
T4	3142	45	0	0
T7	31480	105	0	0
T8	227259	577	0	0
T9	21351	201	0	0
T10	2639	36	0	0
T11	386942	0	0	0
T12	7834	47	0	0
T13	0	36	0	0
T14	0	54	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	215286	0	0
T1	21409	202	0	0
T2	22360	0	0	0
T3	10214	13	0	0
T4	3142	45	0	0
T7	31480	105	0	0
T8	227259	577	0	0
T9	21351	201	0	0
T10	2639	36	0	0
T11	386942	0	0	0
T12	7834	47	0	0
T13	0	36	0	0
T14	0	54	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	533574	0	0
T1	21409	208	0	0
T2	22360	0	0	0
T3	10214	29	0	0
T4	3142	50	0	0
T7	31480	140	0	0
T8	227259	727	0	0
T9	21351	202	0	0
T10	2639	39	0	0
T11	386942	0	0	0
T12	7834	47	0	0
T13	0	83	0	0
T14	0	56	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	215286	0	0
T1	21409	202	0	0
T2	22360	0	0	0
T3	10214	13	0	0
T4	3142	45	0	0
T7	31480	105	0	0
T8	227259	577	0	0
T9	21351	201	0	0
T10	2639	36	0	0
T11	386942	0	0	0
T12	7834	47	0	0
T13	0	36	0	0
T14	0	54	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	212695	0	0
GntImpliesValid_A	378853553	212695	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	212695	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	2834076	0	0
ReadyAndValidImplyGrant_A	378853553	212695	0	0
ReqAndReadyImplyGrant_A	378853553	212695	0	0
ReqImpliesValid_A	378853553	521190	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	212695	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	212695	0	0
T1	21409	171	0	0
T2	22360	0	0	0
T3	10214	20	0	0
T4	3142	39	0	0
T7	31480	97	0	0
T8	227259	613	0	0
T9	21351	196	0	0
T10	2639	36	0	0
T11	386942	0	0	0
T12	7834	67	0	0
T13	0	35	0	0
T14	0	48	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	212695	0	0
T1	21409	171	0	0
T2	22360	0	0	0
T3	10214	20	0	0
T4	3142	39	0	0
T7	31480	97	0	0
T8	227259	613	0	0
T9	21351	196	0	0
T10	2639	36	0	0
T11	386942	0	0	0
T12	7834	67	0	0
T13	0	35	0	0
T14	0	48	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	212695	0	0
T1	21409	171	0	0
T2	22360	0	0	0
T3	10214	20	0	0
T4	3142	39	0	0
T7	31480	97	0	0
T8	227259	613	0	0
T9	21351	196	0	0
T10	2639	36	0	0
T11	386942	0	0	0
T12	7834	67	0	0
T13	0	35	0	0
T14	0	48	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	2834076	0	0
T1	21409	175	0	0
T2	22360	1	0	0
T3	10214	197	0	0
T4	3142	40	0	0
T7	31480	701	0	0
T8	227259	4660	0	0
T9	21351	196	0	0
T10	2639	32	0	0
T11	386942	1	0	0
T12	7834	63	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	212695	0	0
T1	21409	171	0	0
T2	22360	0	0	0
T3	10214	20	0	0
T4	3142	39	0	0
T7	31480	97	0	0
T8	227259	613	0	0
T9	21351	196	0	0
T10	2639	36	0	0
T11	386942	0	0	0
T12	7834	67	0	0
T13	0	35	0	0
T14	0	48	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	212695	0	0
T1	21409	171	0	0
T2	22360	0	0	0
T3	10214	20	0	0
T4	3142	39	0	0
T7	31480	97	0	0
T8	227259	613	0	0
T9	21351	196	0	0
T10	2639	36	0	0
T11	386942	0	0	0
T12	7834	67	0	0
T13	0	35	0	0
T14	0	48	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	521190	0	0
T1	21409	172	0	0
T2	22360	0	0	0
T3	10214	23	0	0
T4	3142	39	0	0
T7	31480	127	0	0
T8	227259	736	0	0
T9	21351	197	0	0
T10	2639	41	0	0
T11	386942	0	0	0
T12	7834	72	0	0
T13	0	37	0	0
T14	0	51	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	212695	0	0
T1	21409	171	0	0
T2	22360	0	0	0
T3	10214	20	0	0
T4	3142	39	0	0
T7	31480	97	0	0
T8	227259	613	0	0
T9	21351	196	0	0
T10	2639	36	0	0
T11	386942	0	0	0
T12	7834	67	0	0
T13	0	35	0	0
T14	0	48	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	210184	0	0
GntImpliesValid_A	378853553	210184	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	210184	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	2822437	0	0
ReadyAndValidImplyGrant_A	378853553	210184	0	0
ReqAndReadyImplyGrant_A	378853553	210184	0	0
ReqImpliesValid_A	378853553	518736	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	0	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	210184	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	210184	0	0
T1	21409	186	0	0
T2	22360	481	0	0
T3	10214	21	0	0
T4	3142	32	0	0
T7	31480	101	0	0
T8	227259	584	0	0
T9	21351	188	0	0
T10	2639	35	0	0
T11	386942	0	0	0
T12	7834	71	0	0
T13	0	35	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	210184	0	0
T1	21409	186	0	0
T2	22360	481	0	0
T3	10214	21	0	0
T4	3142	32	0	0
T7	31480	101	0	0
T8	227259	584	0	0
T9	21351	188	0	0
T10	2639	35	0	0
T11	386942	0	0	0
T12	7834	71	0	0
T13	0	35	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	210184	0	0
T1	21409	186	0	0
T2	22360	481	0	0
T3	10214	21	0	0
T4	3142	32	0	0
T7	31480	101	0	0
T8	227259	584	0	0
T9	21351	188	0	0
T10	2639	35	0	0
T11	386942	0	0	0
T12	7834	71	0	0
T13	0	35	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	2822437	0	0
T1	21409	185	0	0
T2	22360	27	0	0
T3	10214	137	0	0
T4	3142	32	0	0
T7	31480	686	0	0
T8	227259	4408	0	0
T9	21351	187	0	0
T10	2639	36	0	0
T11	386942	1	0	0
T12	7834	70	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	210184	0	0
T1	21409	186	0	0
T2	22360	481	0	0
T3	10214	21	0	0
T4	3142	32	0	0
T7	31480	101	0	0
T8	227259	584	0	0
T9	21351	188	0	0
T10	2639	35	0	0
T11	386942	0	0	0
T12	7834	71	0	0
T13	0	35	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	210184	0	0
T1	21409	186	0	0
T2	22360	481	0	0
T3	10214	21	0	0
T4	3142	32	0	0
T7	31480	101	0	0
T8	227259	584	0	0
T9	21351	188	0	0
T10	2639	35	0	0
T11	386942	0	0	0
T12	7834	71	0	0
T13	0	35	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	518736	0	0
T1	21409	191	0	0
T2	22360	936	0	0
T3	10214	21	0	0
T4	3142	33	0	0
T7	31480	203	0	0
T8	227259	688	0	0
T9	21351	190	0	0
T10	2639	35	0	0
T11	386942	0	0	0
T12	7834	73	0	0
T13	0	45	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	210184	0	0
T1	21409	186	0	0
T2	22360	481	0	0
T3	10214	21	0	0
T4	3142	32	0	0
T7	31480	101	0	0
T8	227259	584	0	0
T9	21351	188	0	0
T10	2639	35	0	0
T11	386942	0	0	0
T12	7834	71	0	0
T13	0	35	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	870553	0	0
GntImpliesValid_A	378853553	870553	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	870553	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	10607493	0	0
ReadyAndValidImplyGrant_A	378853553	870553	0	0
ReqAndReadyImplyGrant_A	378853553	870553	0	0
ReqImpliesValid_A	378853553	2108709	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	18448	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	870553	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	870553	0	0
T1	21409	1443	0	0
T2	22360	1603	0	0
T3	10214	65	0	0
T4	3142	139	0	0
T7	31480	414	0	0
T8	227259	2354	0	0
T9	21351	846	0	0
T10	2639	178	0	0
T11	386942	0	0	0
T12	7834	235	0	0
T13	0	151	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	870553	0	0
T1	21409	1443	0	0
T2	22360	1603	0	0
T3	10214	65	0	0
T4	3142	139	0	0
T7	31480	414	0	0
T8	227259	2354	0	0
T9	21351	846	0	0
T10	2639	178	0	0
T11	386942	0	0	0
T12	7834	235	0	0
T13	0	151	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	870553	0	0
T1	21409	1443	0	0
T2	22360	1603	0	0
T3	10214	65	0	0
T4	3142	139	0	0
T7	31480	414	0	0
T8	227259	2354	0	0
T9	21351	846	0	0
T10	2639	178	0	0
T11	386942	0	0	0
T12	7834	235	0	0
T13	0	151	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	10607493	0	0
T1	21409	5	0	0
T2	22360	1	0	0
T3	10214	429	0	0
T4	3142	1	0	0
T7	31480	2345	0	0
T8	227259	15355	0	0
T9	21351	1	0	0
T10	2639	1	0	0
T11	386942	1	0	0
T12	7834	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	870553	0	0
T1	21409	1443	0	0
T2	22360	1603	0	0
T3	10214	65	0	0
T4	3142	139	0	0
T7	31480	414	0	0
T8	227259	2354	0	0
T9	21351	846	0	0
T10	2639	178	0	0
T11	386942	0	0	0
T12	7834	235	0	0
T13	0	151	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	870553	0	0
T1	21409	1443	0	0
T2	22360	1603	0	0
T3	10214	65	0	0
T4	3142	139	0	0
T7	31480	414	0	0
T8	227259	2354	0	0
T9	21351	846	0	0
T10	2639	178	0	0
T11	386942	0	0	0
T12	7834	235	0	0
T13	0	151	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	2108709	0	0
T1	21409	1443	0	0
T2	22360	1603	0	0
T3	10214	109	0	0
T4	3142	139	0	0
T7	31480	719	0	0
T8	227259	3529	0	0
T9	21351	846	0	0
T10	2639	178	0	0
T11	386942	0	0	0
T12	7834	235	0	0
T13	0	277	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	18448	0	900
T1	21409	84	0	1
T2	22360	289	0	1
T3	10214	0	0	1
T4	3142	0	0	1
T7	31480	1	0	1
T8	227259	1	0	1
T9	21351	8	0	1
T10	2639	2	0	1
T11	386942	0	0	1
T12	7834	6	0	1
T16	0	2	0	0
T17	0	4	0	0
T18	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	870553	0	0
T1	21409	1443	0	0
T2	22360	1603	0	0
T3	10214	65	0	0
T4	3142	139	0	0
T7	31480	414	0	0
T8	227259	2354	0	0
T9	21351	846	0	0
T10	2639	178	0	0
T11	386942	0	0	0
T12	7834	235	0	0
T13	0	151	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378853553	378724491	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	378853553	856152	0	0
GntImpliesValid_A	378853553	856152	0	0
GrantKnown_A	378853553	378724491	0	0
IdxKnown_A	378853553	378724491	0	0
IndexIsCorrect_A	378853553	856152	0	0
LockArbDecision_A	378853553	0	0	0
NoReadyValidNoGrant_A	378853553	317227738	0	0
ReadyAndValidImplyGrant_A	378853553	856152	0	0
ReqAndReadyImplyGrant_A	378853553	856152	0	0
ReqImpliesValid_A	378853553	12329293	0	0
ReqStaysHighUntilGranted0_M	378853553	0	0	0
RoundRobin_A	378853553	27841	0	900
ValidKnown_A	378853553	378724491	0	0
gen_data_port_assertion.DataFlow_A	378853553	856152	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	856152	0	0
T1	21409	754	0	0
T2	22360	767	0	0
T3	10214	66	0	0
T4	3142	141	0	0
T7	31480	386	0	0
T8	227259	2340	0	0
T9	21351	757	0	0
T10	2639	185	0	0
T11	386942	0	0	0
T12	7834	285	0	0
T13	0	159	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	856152	0	0
T1	21409	754	0	0
T2	22360	767	0	0
T3	10214	66	0	0
T4	3142	141	0	0
T7	31480	386	0	0
T8	227259	2340	0	0
T9	21351	757	0	0
T10	2639	185	0	0
T11	386942	0	0	0
T12	7834	285	0	0
T13	0	159	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	856152	0	0
T1	21409	754	0	0
T2	22360	767	0	0
T3	10214	66	0	0
T4	3142	141	0	0
T7	31480	386	0	0
T8	227259	2340	0	0
T9	21351	757	0	0
T10	2639	185	0	0
T11	386942	0	0	0
T12	7834	285	0	0
T13	0	159	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	317227738	0	0
T1	21409	1	0	0
T2	22360	1	0	0
T3	10214	8795	0	0
T4	3142	1	0	0
T7	31480	25054	0	0
T8	227259	189628	0	0
T9	21351	1	0	0
T10	2639	1	0	0
T11	386942	322526	0	0
T12	7834	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	856152	0	0
T1	21409	754	0	0
T2	22360	767	0	0
T3	10214	66	0	0
T4	3142	141	0	0
T7	31480	386	0	0
T8	227259	2340	0	0
T9	21351	757	0	0
T10	2639	185	0	0
T11	386942	0	0	0
T12	7834	285	0	0
T13	0	159	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	856152	0	0
T1	21409	754	0	0
T2	22360	767	0	0
T3	10214	66	0	0
T4	3142	141	0	0
T7	31480	386	0	0
T8	227259	2340	0	0
T9	21351	757	0	0
T10	2639	185	0	0
T11	386942	0	0	0
T12	7834	285	0	0
T13	0	159	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	12329293	0	0
T1	21409	754	0	0
T2	22360	767	0	0
T3	10214	481	0	0
T4	3142	141	0	0
T7	31480	2682	0	0
T8	227259	19089	0	0
T9	21351	757	0	0
T10	2639	185	0	0
T11	386942	0	0	0
T12	7834	285	0	0
T13	0	1338	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	27841	0	900
T1	21409	8	0	1
T2	22360	0	0	1
T3	10214	0	0	1
T4	3142	2	0	1
T7	31480	1	0	1
T8	227259	1	0	1
T9	21351	10	0	1
T10	2639	6	0	1
T11	386942	0	0	1
T12	7834	2	0	1
T14	0	1	0	0
T15	0	3	0	0
T16	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	378724491	0	0
T1	21409	20674	0	0
T2	22360	22342	0	0
T3	10214	10135	0	0
T4	3142	3065	0	0
T7	31480	31467	0	0
T8	227259	227173	0	0
T9	21351	21275	0	0
T10	2639	2633	0	0
T11	386942	386918	0	0
T12	7834	7766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378853553	856152	0	0
T1	21409	754	0	0
T2	22360	767	0	0
T3	10214	66	0	0
T4	3142	141	0	0
T7	31480	386	0	0
T8	227259	2340	0	0
T9	21351	757	0	0
T10	2639	185	0	0
T11	386942	0	0	0
T12	7834	285	0	0
T13	0	159	0	0