Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1639074	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

261111

1

T1

97

T2

2

T3

307

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	646193	1			T1	243		T2	20		T3	802
values[0x0]	610438	1			T1	227		T2	5		T3	744
values[0x1]	643554	1			T1	243		T2	20		T3	772

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1267480	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

632705

1

T1

243

T2

17

T3

765

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30713	1			T1	23		T2	1		T3	31
valid_sources[0x01]	29043	1			T1	22		T2	2		T3	26
valid_sources[0x02]	29003	1			T1	13		T3	24		T7	39
valid_sources[0x03]	30060	1			T1	8		T3	38		T7	38
valid_sources[0x04]	28715	1			T1	13		T3	47		T7	26
valid_sources[0x05]	30255	1			T1	7		T2	5		T3	21
valid_sources[0x06]	29088	1			T1	12		T2	1		T3	41
valid_sources[0x07]	28757	1			T1	9		T3	38		T7	41
valid_sources[0x08]	30150	1			T1	29		T3	39		T7	39
valid_sources[0x09]	29097	1			T3	35		T7	30		T4	7
valid_sources[0x0a]	29966	1			T1	26		T3	37		T7	41
valid_sources[0x0b]	29804	1			T3	40		T7	47		T4	11
valid_sources[0x0c]	29075	1			T1	9		T3	27		T7	37
valid_sources[0x0d]	29584	1			T1	16		T2	1		T3	37
valid_sources[0x0e]	28651	1			T3	22		T7	27		T4	7
valid_sources[0x0f]	29730	1			T1	11		T3	46		T7	30
valid_sources[0x10]	30229	1			T1	8		T3	38		T7	32
valid_sources[0x11]	29926	1			T1	1		T3	37		T7	41
valid_sources[0x12]	30080	1			T1	4		T3	36		T7	44
valid_sources[0x13]	30275	1			T1	20		T2	1		T3	39
valid_sources[0x14]	31788	1			T1	21		T3	47		T7	35
valid_sources[0x15]	29712	1			T3	34		T7	41		T4	4
valid_sources[0x16]	29234	1			T1	7		T2	1		T3	40
valid_sources[0x17]	28555	1			T1	7		T3	32		T7	43
valid_sources[0x18]	30484	1			T1	19		T3	45		T7	34
valid_sources[0x19]	28979	1			T1	13		T3	34		T7	25
valid_sources[0x1a]	29167	1			T3	41		T7	41		T4	7
valid_sources[0x1b]	29910	1			T1	10		T3	29		T7	42
valid_sources[0x1c]	30891	1			T1	10		T2	1		T3	32
valid_sources[0x1d]	30166	1			T1	18		T3	40		T7	33
valid_sources[0x1e]	30152	1			T1	8		T3	33		T7	32
valid_sources[0x1f]	28499	1			T1	17		T2	3		T3	28
valid_sources[0x20]	29987	1			T1	3		T3	49		T7	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27460

1

T1

14

T3

34

T7

29

values[0x0]

all_enables

biggest_size

206066

1

T1

77

T2

2

T3

230

values[0x1]

all_enables

biggest_size

27585

1

T1

6

T3

43

T7

36

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1649258	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

268270

1

T1

95

T2

3

T3

353

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	655217	1			T1	187		T2	9		T3	771
values[0x0]	603898	1			T1	203		T3	786		T7	855
values[0x1]	658413	1			T1	190		T2	13		T3	781

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1265643	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

651885

1

T1

201

T2

10

T3

818

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30096	1			T1	11		T2	1		T3	19
valid_sources[0x01]	28789	1			T1	17		T3	31		T7	54
valid_sources[0x02]	29406	1			T1	8		T3	26		T7	36
valid_sources[0x03]	30650	1			T1	12		T3	48		T7	22
valid_sources[0x04]	30098	1			T1	4		T2	1		T3	54
valid_sources[0x05]	30117	1			T1	14		T3	21		T7	12
valid_sources[0x06]	29351	1			T1	9		T3	39		T7	66
valid_sources[0x07]	30782	1			T1	32		T2	2		T3	39
valid_sources[0x08]	29021	1			T1	4		T3	35		T7	68
valid_sources[0x09]	29731	1			T1	16		T3	71		T7	48
valid_sources[0x0a]	29613	1			T1	5		T3	53		T7	91
valid_sources[0x0b]	30464	1			T1	10		T3	10		T7	77
valid_sources[0x0c]	30417	1			T1	8		T3	33		T7	37
valid_sources[0x0d]	29793	1			T1	10		T3	23		T7	10
valid_sources[0x0e]	29745	1			T1	3		T3	11		T7	41
valid_sources[0x0f]	29988	1			T1	1		T2	1		T3	69
valid_sources[0x10]	30506	1			T1	9		T3	9		T7	79
valid_sources[0x11]	29620	1			T1	24		T2	1		T3	40
valid_sources[0x12]	29839	1			T1	4		T3	61		T7	27
valid_sources[0x13]	29816	1			T1	4		T2	2		T3	37
valid_sources[0x14]	30591	1			T1	7		T3	15		T7	22
valid_sources[0x15]	30046	1			T1	7		T3	37		T7	33
valid_sources[0x16]	29816	1			T1	8		T2	1		T3	12
valid_sources[0x17]	29261	1			T3	29		T7	28		T4	1
valid_sources[0x18]	30379	1			T1	15		T3	31		T7	35
valid_sources[0x19]	29659	1			T1	13		T3	17		T7	30
valid_sources[0x1a]	30648	1			T1	12		T3	55		T7	59
valid_sources[0x1b]	29533	1			T1	9		T3	44		T7	33
valid_sources[0x1c]	30455	1			T1	9		T3	38		T7	37
valid_sources[0x1d]	30046	1			T1	7		T2	1		T3	35
valid_sources[0x1e]	30239	1			T1	6		T2	2		T3	28
valid_sources[0x1f]	29068	1			T1	9		T3	48		T7	28
valid_sources[0x20]	30460	1			T1	11		T3	55		T7	56

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28177

1

T1

11

T2

3

T3

28

values[0x0]

all_enables

biggest_size

211877

1

T1

79

T3

300

T7

319

values[0x1]

all_enables

biggest_size

28216

1

T1

5

T3

25

T7

33

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1652264	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

263239

1

T1

97

T2

2

T3

308

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	649723	1			T1	263		T2	20		T3	732
values[0x0]	615392	1			T1	236		T2	1		T3	738
values[0x1]	650388	1			T1	302		T2	12		T3	746

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1276618	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

638885

1

T1

259

T2

12

T3

726

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29764	1			T1	12		T3	29		T7	24
valid_sources[0x01]	30446	1			T1	14		T2	1		T3	27
valid_sources[0x02]	29262	1			T1	7		T2	1		T3	44
valid_sources[0x03]	30241	1			T1	11		T2	2		T3	31
valid_sources[0x04]	28718	1			T1	12		T3	16		T7	68
valid_sources[0x05]	29523	1			T1	19		T2	1		T3	43
valid_sources[0x06]	29176	1			T1	15		T3	8		T7	31
valid_sources[0x07]	29946	1			T1	13		T2	1		T3	5
valid_sources[0x08]	29995	1			T1	22		T3	41		T7	18
valid_sources[0x09]	29086	1			T1	14		T3	31		T7	37
valid_sources[0x0a]	30139	1			T1	18		T3	12		T7	35
valid_sources[0x0b]	28922	1			T1	11		T2	1		T3	43
valid_sources[0x0c]	29598	1			T1	17		T3	46		T7	44
valid_sources[0x0d]	29112	1			T1	11		T3	29		T7	30
valid_sources[0x0e]	29548	1			T1	9		T2	3		T3	13
valid_sources[0x0f]	29365	1			T1	9		T2	1		T3	26
valid_sources[0x10]	30136	1			T1	15		T3	18		T7	36
valid_sources[0x11]	29559	1			T1	18		T2	1		T3	33
valid_sources[0x12]	30784	1			T1	21		T2	1		T3	18
valid_sources[0x13]	30436	1			T1	16		T2	2		T3	25
valid_sources[0x14]	30538	1			T1	21		T2	1		T3	34
valid_sources[0x15]	30105	1			T1	9		T3	49		T7	18
valid_sources[0x16]	29570	1			T1	16		T3	45		T7	44
valid_sources[0x17]	29722	1			T1	12		T3	37		T7	32
valid_sources[0x18]	30103	1			T1	6		T3	42		T7	12
valid_sources[0x19]	30444	1			T1	12		T3	38		T7	36
valid_sources[0x1a]	29650	1			T1	8		T2	1		T3	32
valid_sources[0x1b]	29835	1			T1	18		T3	56		T7	55
valid_sources[0x1c]	29139	1			T1	10		T3	22		T7	24
valid_sources[0x1d]	30969	1			T1	13		T2	1		T3	38
valid_sources[0x1e]	29559	1			T1	20		T2	1		T3	58
valid_sources[0x1f]	30227	1			T1	13		T3	44		T7	8
valid_sources[0x20]	31224	1			T1	6		T3	41		T7	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27458

1

T1

9

T2

2

T3

26

values[0x0]

all_enables

biggest_size

207896

1

T1

80

T3

246

T7

277

values[0x1]

all_enables

biggest_size

27885

1

T1

8

T3

36

T7

30