Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8288798	0	0
GntImpliesValid_A	2147483647	8288798	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8288798	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	446504697	0	0
ReadyAndValidImplyGrant_A	2147483647	8288798	0	0
ReqAndReadyImplyGrant_A	2147483647	8288798	0	0
ReqImpliesValid_A	2147483647	34377257	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	57045	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8288798	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	549576	547752	0	0
T2	90456	89304	0	0
T3	1382928	1382184	0	0
T4	13915056	13912824	0	0
T5	6633264	6627336	0	0
T7	1689936	1689384	0	0
T8	161568	160152	0	0
T9	29064	28392	0	0
T10	236136	235512	0	0
T11	68448	68304	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8288798	0	0
T1	549576	2093	0	0
T2	90456	1290	0	0
T3	1382928	6872	0	0
T4	13915056	1193	0	0
T5	6633264	17660	0	0
T7	1689936	7330	0	0
T8	161568	3174	0	0
T9	29064	770	0	0
T10	236136	389	0	0
T11	68448	1737	0	0
T12	0	1534	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8288798	0	0
T1	549576	2093	0	0
T2	90456	1290	0	0
T3	1382928	6872	0	0
T4	13915056	1193	0	0
T5	6633264	17660	0	0
T7	1689936	7330	0	0
T8	161568	3174	0	0
T9	29064	770	0	0
T10	236136	389	0	0
T11	68448	1737	0	0
T12	0	1534	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	549576	547752	0	0
T2	90456	89304	0	0
T3	1382928	1382184	0	0
T4	13915056	13912824	0	0
T5	6633264	6627336	0	0
T7	1689936	1689384	0	0
T8	161568	160152	0	0
T9	29064	28392	0	0
T10	236136	235512	0	0
T11	68448	68304	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	549576	547752	0	0
T2	90456	89304	0	0
T3	1382928	1382184	0	0
T4	13915056	13912824	0	0
T5	6633264	6627336	0	0
T7	1689936	1689384	0	0
T8	161568	160152	0	0
T9	29064	28392	0	0
T10	236136	235512	0	0
T11	68448	68304	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8288798	0	0
T1	549576	2093	0	0
T2	90456	1290	0	0
T3	1382928	6872	0	0
T4	13915056	1193	0	0
T5	6633264	17660	0	0
T7	1689936	7330	0	0
T8	161568	3174	0	0
T9	29064	770	0	0
T10	236136	389	0	0
T11	68448	1737	0	0
T12	0	1534	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	446504697	0	0
T1	549576	34361	0	0
T2	90456	1658	0	0
T3	1382928	90432	0	0
T4	13915056	940077	0	0
T5	6633264	396256	0	0
T7	1689936	105843	0	0
T8	161568	4792	0	0
T9	29064	127	0	0
T10	236136	11374	0	0
T11	68448	1730	0	0
T12	0	4287	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8288798	0	0
T1	549576	2093	0	0
T2	90456	1290	0	0
T3	1382928	6872	0	0
T4	13915056	1193	0	0
T5	6633264	17660	0	0
T7	1689936	7330	0	0
T8	161568	3174	0	0
T9	29064	770	0	0
T10	236136	389	0	0
T11	68448	1737	0	0
T12	0	1534	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8288798	0	0
T1	549576	2093	0	0
T2	90456	1290	0	0
T3	1382928	6872	0	0
T4	13915056	1193	0	0
T5	6633264	17660	0	0
T7	1689936	7330	0	0
T8	161568	3174	0	0
T9	29064	770	0	0
T10	236136	389	0	0
T11	68448	1737	0	0
T12	0	1534	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34377257	0	0
T1	549576	4427	0	0
T2	90456	1486	0	0
T3	1382928	16170	0	0
T4	13915056	81669	0	0
T5	6633264	51029	0	0
T7	1689936	16688	0	0
T8	161568	3807	0	0
T9	29064	1282	0	0
T10	236136	858	0	0
T11	68448	1961	0	0
T12	0	2044	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	57045	0	21600
T2	3769	1	0	1
T3	57622	3	0	1
T4	579794	0	0	1
T5	552772	30	0	2
T7	70414	0	0	1
T8	13464	10	0	2
T9	2422	0	0	2
T10	19678	0	0	2
T11	5704	4	0	2
T12	1910122	0	0	2
T13	381485	25	0	1
T14	0	29	0	0
T15	0	2	0	0
T16	0	13	0	0
T17	0	19	0	0
T18	0	292	0	0
T19	0	7	0	0
T20	0	6	0	0
T21	0	351	0	0
T22	82067	0	0	1
T23	378674	0	0	1
T24	154171	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	549576	547752	0	0
T2	90456	89304	0	0
T3	1382928	1382184	0	0
T4	13915056	13912824	0	0
T5	6633264	6627336	0	0
T7	1689936	1689384	0	0
T8	161568	160152	0	0
T9	29064	28392	0	0
T10	236136	235512	0	0
T11	68448	68304	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8288798	0	0
T1	549576	2093	0	0
T2	90456	1290	0	0
T3	1382928	6872	0	0
T4	13915056	1193	0	0
T5	6633264	17660	0	0
T7	1689936	7330	0	0
T8	161568	3174	0	0
T9	29064	770	0	0
T10	236136	389	0	0
T11	68448	1737	0	0
T12	0	1534	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	928401	0	0
GntImpliesValid_A	413303374	928401	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	928401	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	11629289	0	0
ReadyAndValidImplyGrant_A	413303374	928401	0	0
ReqAndReadyImplyGrant_A	413303374	928401	0	0
ReqImpliesValid_A	413303374	2574896	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	928401	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	928401	0	0
T1	22899	214	0	0
T2	3769	126	0	0
T3	57622	788	0	0
T4	579794	147	0	0
T5	276386	3191	0	0
T7	70414	849	0	0
T8	6732	338	0	0
T9	1211	84	0	0
T10	9839	28	0	0
T11	2852	173	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	928401	0	0
T1	22899	214	0	0
T2	3769	126	0	0
T3	57622	788	0	0
T4	579794	147	0	0
T5	276386	3191	0	0
T7	70414	849	0	0
T8	6732	338	0	0
T9	1211	84	0	0
T10	9839	28	0	0
T11	2852	173	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	928401	0	0
T1	22899	214	0	0
T2	3769	126	0	0
T3	57622	788	0	0
T4	579794	147	0	0
T5	276386	3191	0	0
T7	70414	849	0	0
T8	6732	338	0	0
T9	1211	84	0	0
T10	9839	28	0	0
T11	2852	173	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	11629289	0	0
T1	22899	1482	0	0
T2	3769	113	0	0
T3	57622	5313	0	0
T4	579794	47737	0	0
T5	276386	20120	0	0
T7	70414	6147	0	0
T8	6732	271	0	0
T9	1211	56	0	0
T10	9839	223	0	0
T11	2852	116	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	928401	0	0
T1	22899	214	0	0
T2	3769	126	0	0
T3	57622	788	0	0
T4	579794	147	0	0
T5	276386	3191	0	0
T7	70414	849	0	0
T8	6732	338	0	0
T9	1211	84	0	0
T10	9839	28	0	0
T11	2852	173	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	928401	0	0
T1	22899	214	0	0
T2	3769	126	0	0
T3	57622	788	0	0
T4	579794	147	0	0
T5	276386	3191	0	0
T7	70414	849	0	0
T8	6732	338	0	0
T9	1211	84	0	0
T10	9839	28	0	0
T11	2852	173	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	2574896	0	0
T1	22899	524	0	0
T2	3769	140	0	0
T3	57622	1394	0	0
T4	579794	3705	0	0
T5	276386	10839	0	0
T7	70414	1504	0	0
T8	6732	406	0	0
T9	1211	113	0	0
T10	9839	39	0	0
T11	2852	231	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	928401	0	0
T1	22899	214	0	0
T2	3769	126	0	0
T3	57622	788	0	0
T4	579794	147	0	0
T5	276386	3191	0	0
T7	70414	849	0	0
T8	6732	338	0	0
T9	1211	84	0	0
T10	9839	28	0	0
T11	2852	173	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	915439	0	0
GntImpliesValid_A	413303374	915439	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	915439	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	11687141	0	0
ReadyAndValidImplyGrant_A	413303374	915439	0	0
ReqAndReadyImplyGrant_A	413303374	915439	0	0
ReqImpliesValid_A	413303374	2451042	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	915439	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	915439	0	0
T1	22899	197	0	0
T2	3769	142	0	0
T3	57622	786	0	0
T4	579794	146	0	0
T5	276386	1629	0	0
T7	70414	837	0	0
T8	6732	350	0	0
T9	1211	62	0	0
T10	9839	51	0	0
T11	2852	147	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	915439	0	0
T1	22899	197	0	0
T2	3769	142	0	0
T3	57622	786	0	0
T4	579794	146	0	0
T5	276386	1629	0	0
T7	70414	837	0	0
T8	6732	350	0	0
T9	1211	62	0	0
T10	9839	51	0	0
T11	2852	147	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	915439	0	0
T1	22899	197	0	0
T2	3769	142	0	0
T3	57622	786	0	0
T4	579794	146	0	0
T5	276386	1629	0	0
T7	70414	837	0	0
T8	6732	350	0	0
T9	1211	62	0	0
T10	9839	51	0	0
T11	2852	147	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	11687141	0	0
T1	22899	1478	0	0
T2	3769	121	0	0
T3	57622	5633	0	0
T4	579794	45470	0	0
T5	276386	12260	0	0
T7	70414	6179	0	0
T8	6732	277	0	0
T9	1211	49	0	0
T10	9839	414	0	0
T11	2852	110	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	915439	0	0
T1	22899	197	0	0
T2	3769	142	0	0
T3	57622	786	0	0
T4	579794	146	0	0
T5	276386	1629	0	0
T7	70414	837	0	0
T8	6732	350	0	0
T9	1211	62	0	0
T10	9839	51	0	0
T11	2852	147	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	915439	0	0
T1	22899	197	0	0
T2	3769	142	0	0
T3	57622	786	0	0
T4	579794	146	0	0
T5	276386	1629	0	0
T7	70414	837	0	0
T8	6732	350	0	0
T9	1211	62	0	0
T10	9839	51	0	0
T11	2852	147	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	2451042	0	0
T1	22899	336	0	0
T2	3769	164	0	0
T3	57622	1575	0	0
T4	579794	8419	0	0
T5	276386	2247	0	0
T7	70414	1508	0	0
T8	6732	424	0	0
T9	1211	76	0	0
T10	9839	114	0	0
T11	2852	185	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	915439	0	0
T1	22899	197	0	0
T2	3769	142	0	0
T3	57622	786	0	0
T4	579794	146	0	0
T5	276386	1629	0	0
T7	70414	837	0	0
T8	6732	350	0	0
T9	1211	62	0	0
T10	9839	51	0	0
T11	2852	147	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	232455	0	0
GntImpliesValid_A	413303374	232455	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	232455	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	2861378	0	0
ReadyAndValidImplyGrant_A	413303374	232455	0	0
ReqAndReadyImplyGrant_A	413303374	232455	0	0
ReqImpliesValid_A	413303374	577714	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	232455	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	232455	0	0
T1	22899	62	0	0
T2	3769	50	0	0
T3	57622	189	0	0
T4	579794	24	0	0
T5	276386	431	0	0
T7	70414	208	0	0
T8	6732	84	0	0
T9	1211	0	0	0
T10	9839	13	0	0
T11	2852	49	0	0
T12	0	85	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	232455	0	0
T1	22899	62	0	0
T2	3769	50	0	0
T3	57622	189	0	0
T4	579794	24	0	0
T5	276386	431	0	0
T7	70414	208	0	0
T8	6732	84	0	0
T9	1211	0	0	0
T10	9839	13	0	0
T11	2852	49	0	0
T12	0	85	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	232455	0	0
T1	22899	62	0	0
T2	3769	50	0	0
T3	57622	189	0	0
T4	579794	24	0	0
T5	276386	431	0	0
T7	70414	208	0	0
T8	6732	84	0	0
T9	1211	0	0	0
T10	9839	13	0	0
T11	2852	49	0	0
T12	0	85	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	2861378	0	0
T1	22899	430	0	0
T2	3769	45	0	0
T3	57622	1363	0	0
T4	579794	4565	0	0
T5	276386	3216	0	0
T7	70414	1581	0	0
T8	6732	80	0	0
T9	1211	1	0	0
T10	9839	121	0	0
T11	2852	45	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	232455	0	0
T1	22899	62	0	0
T2	3769	50	0	0
T3	57622	189	0	0
T4	579794	24	0	0
T5	276386	431	0	0
T7	70414	208	0	0
T8	6732	84	0	0
T9	1211	0	0	0
T10	9839	13	0	0
T11	2852	49	0	0
T12	0	85	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	232455	0	0
T1	22899	62	0	0
T2	3769	50	0	0
T3	57622	189	0	0
T4	579794	24	0	0
T5	276386	431	0	0
T7	70414	208	0	0
T8	6732	84	0	0
T9	1211	0	0	0
T10	9839	13	0	0
T11	2852	49	0	0
T12	0	85	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	577714	0	0
T1	22899	99	0	0
T2	3769	56	0	0
T3	57622	236	0	0
T4	579794	1119	0	0
T5	276386	482	0	0
T7	70414	286	0	0
T8	6732	89	0	0
T9	1211	0	0	0
T10	9839	13	0	0
T11	2852	54	0	0
T12	0	109	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	232455	0	0
T1	22899	62	0	0
T2	3769	50	0	0
T3	57622	189	0	0
T4	579794	24	0	0
T5	276386	431	0	0
T7	70414	208	0	0
T8	6732	84	0	0
T9	1211	0	0	0
T10	9839	13	0	0
T11	2852	49	0	0
T12	0	85	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	225585	0	0
GntImpliesValid_A	413303374	225585	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	225585	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	2886132	0	0
ReadyAndValidImplyGrant_A	413303374	225585	0	0
ReqAndReadyImplyGrant_A	413303374	225585	0	0
ReqImpliesValid_A	413303374	606436	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	225585	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	225585	0	0
T1	22899	58	0	0
T2	3769	36	0	0
T3	57622	201	0	0
T4	579794	27	0	0
T5	276386	391	0	0
T7	70414	214	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	8	0	0
T11	2852	51	0	0
T12	0	77	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	225585	0	0
T1	22899	58	0	0
T2	3769	36	0	0
T3	57622	201	0	0
T4	579794	27	0	0
T5	276386	391	0	0
T7	70414	214	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	8	0	0
T11	2852	51	0	0
T12	0	77	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	225585	0	0
T1	22899	58	0	0
T2	3769	36	0	0
T3	57622	201	0	0
T4	579794	27	0	0
T5	276386	391	0	0
T7	70414	214	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	8	0	0
T11	2852	51	0	0
T12	0	77	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	2886132	0	0
T1	22899	423	0	0
T2	3769	35	0	0
T3	57622	1386	0	0
T4	579794	8751	0	0
T5	276386	2988	0	0
T7	70414	1491	0	0
T8	6732	87	0	0
T9	1211	1	0	0
T10	9839	64	0	0
T11	2852	50	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	225585	0	0
T1	22899	58	0	0
T2	3769	36	0	0
T3	57622	201	0	0
T4	579794	27	0	0
T5	276386	391	0	0
T7	70414	214	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	8	0	0
T11	2852	51	0	0
T12	0	77	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	225585	0	0
T1	22899	58	0	0
T2	3769	36	0	0
T3	57622	201	0	0
T4	579794	27	0	0
T5	276386	391	0	0
T7	70414	214	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	8	0	0
T11	2852	51	0	0
T12	0	77	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	606436	0	0
T1	22899	74	0	0
T2	3769	38	0	0
T3	57622	251	0	0
T4	579794	558	0	0
T5	276386	465	0	0
T7	70414	341	0	0
T8	6732	96	0	0
T9	1211	0	0	0
T10	9839	8	0	0
T11	2852	53	0	0
T12	0	92	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	225585	0	0
T1	22899	58	0	0
T2	3769	36	0	0
T3	57622	201	0	0
T4	579794	27	0	0
T5	276386	391	0	0
T7	70414	214	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	8	0	0
T11	2852	51	0	0
T12	0	77	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	229231	0	0
GntImpliesValid_A	413303374	229231	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	229231	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	4779555	0	0
ReadyAndValidImplyGrant_A	413303374	229231	0	0
ReqAndReadyImplyGrant_A	413303374	229231	0	0
ReqImpliesValid_A	413303374	1160782	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	229231	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	229231	0	0
T1	22899	78	0	0
T2	3769	39	0	0
T3	57622	195	0	0
T4	579794	42	0	0
T5	276386	911	0	0
T7	70414	215	0	0
T8	6732	75	0	0
T9	1211	0	0	0
T10	9839	9	0	0
T11	2852	57	0	0
T12	0	82	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	229231	0	0
T1	22899	78	0	0
T2	3769	39	0	0
T3	57622	195	0	0
T4	579794	42	0	0
T5	276386	911	0	0
T7	70414	215	0	0
T8	6732	75	0	0
T9	1211	0	0	0
T10	9839	9	0	0
T11	2852	57	0	0
T12	0	82	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	229231	0	0
T1	22899	78	0	0
T2	3769	39	0	0
T3	57622	195	0	0
T4	579794	42	0	0
T5	276386	911	0	0
T7	70414	215	0	0
T8	6732	75	0	0
T9	1211	0	0	0
T10	9839	9	0	0
T11	2852	57	0	0
T12	0	82	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	4779555	0	0
T1	22899	887	0	0
T2	3769	162	0	0
T3	57622	1563	0	0
T4	579794	32567	0	0
T5	276386	31164	0	0
T7	70414	1204	0	0
T8	6732	526	0	0
T9	1211	0	0	0
T10	9839	60	0	0
T11	2852	189	0	0
T12	0	1898	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	229231	0	0
T1	22899	78	0	0
T2	3769	39	0	0
T3	57622	195	0	0
T4	579794	42	0	0
T5	276386	911	0	0
T7	70414	215	0	0
T8	6732	75	0	0
T9	1211	0	0	0
T10	9839	9	0	0
T11	2852	57	0	0
T12	0	82	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	229231	0	0
T1	22899	78	0	0
T2	3769	39	0	0
T3	57622	195	0	0
T4	579794	42	0	0
T5	276386	911	0	0
T7	70414	215	0	0
T8	6732	75	0	0
T9	1211	0	0	0
T10	9839	9	0	0
T11	2852	57	0	0
T12	0	82	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	1160782	0	0
T1	22899	125	0	0
T2	3769	54	0	0
T3	57622	259	0	0
T4	579794	8079	0	0
T5	276386	8846	0	0
T7	70414	249	0	0
T8	6732	129	0	0
T9	1211	0	0	0
T10	9839	9	0	0
T11	2852	66	0	0
T12	0	220	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	229231	0	0
T1	22899	78	0	0
T2	3769	39	0	0
T3	57622	195	0	0
T4	579794	42	0	0
T5	276386	911	0	0
T7	70414	215	0	0
T8	6732	75	0	0
T9	1211	0	0	0
T10	9839	9	0	0
T11	2852	57	0	0
T12	0	82	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	224291	0	0
GntImpliesValid_A	413303374	224291	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	224291	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	4803974	0	0
ReadyAndValidImplyGrant_A	413303374	224291	0	0
ReqAndReadyImplyGrant_A	413303374	224291	0	0
ReqImpliesValid_A	413303374	1218471	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	224291	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	224291	0	0
T1	22899	64	0	0
T2	3769	48	0	0
T3	57622	192	0	0
T4	579794	46	0	0
T5	276386	409	0	0
T7	70414	201	0	0
T8	6732	71	0	0
T9	1211	0	0	0
T10	9839	15	0	0
T11	2852	46	0	0
T12	0	75	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	224291	0	0
T1	22899	64	0	0
T2	3769	48	0	0
T3	57622	192	0	0
T4	579794	46	0	0
T5	276386	409	0	0
T7	70414	201	0	0
T8	6732	71	0	0
T9	1211	0	0	0
T10	9839	15	0	0
T11	2852	46	0	0
T12	0	75	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	224291	0	0
T1	22899	64	0	0
T2	3769	48	0	0
T3	57622	192	0	0
T4	579794	46	0	0
T5	276386	409	0	0
T7	70414	201	0	0
T8	6732	71	0	0
T9	1211	0	0	0
T10	9839	15	0	0
T11	2852	46	0	0
T12	0	75	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	4803974	0	0
T1	22899	790	0	0
T2	3769	258	0	0
T3	57622	1375	0	0
T4	579794	25903	0	0
T5	276386	18977	0	0
T7	70414	1305	0	0
T8	6732	346	0	0
T9	1211	0	0	0
T10	9839	119	0	0
T11	2852	153	0	0
T12	0	688	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	224291	0	0
T1	22899	64	0	0
T2	3769	48	0	0
T3	57622	192	0	0
T4	579794	46	0	0
T5	276386	409	0	0
T7	70414	201	0	0
T8	6732	71	0	0
T9	1211	0	0	0
T10	9839	15	0	0
T11	2852	46	0	0
T12	0	75	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	224291	0	0
T1	22899	64	0	0
T2	3769	48	0	0
T3	57622	192	0	0
T4	579794	46	0	0
T5	276386	409	0	0
T7	70414	201	0	0
T8	6732	71	0	0
T9	1211	0	0	0
T10	9839	15	0	0
T11	2852	46	0	0
T12	0	75	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	1218471	0	0
T1	22899	106	0	0
T2	3769	99	0	0
T3	57622	263	0	0
T4	579794	2132	0	0
T5	276386	1837	0	0
T7	70414	280	0	0
T8	6732	93	0	0
T9	1211	0	0	0
T10	9839	17	0	0
T11	2852	55	0	0
T12	0	122	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	224291	0	0
T1	22899	64	0	0
T2	3769	48	0	0
T3	57622	192	0	0
T4	579794	46	0	0
T5	276386	409	0	0
T7	70414	201	0	0
T8	6732	71	0	0
T9	1211	0	0	0
T10	9839	15	0	0
T11	2852	46	0	0
T12	0	75	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	230827	0	0
GntImpliesValid_A	413303374	230827	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	230827	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	5066894	0	0
ReadyAndValidImplyGrant_A	413303374	230827	0	0
ReqAndReadyImplyGrant_A	413303374	230827	0	0
ReqImpliesValid_A	413303374	1239232	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	230827	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	230827	0	0
T1	22899	52	0	0
T2	3769	41	0	0
T3	57622	195	0	0
T4	579794	24	0	0
T5	276386	384	0	0
T7	70414	196	0	0
T8	6732	87	0	0
T9	1211	0	0	0
T10	9839	10	0	0
T11	2852	62	0	0
T12	0	73	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	230827	0	0
T1	22899	52	0	0
T2	3769	41	0	0
T3	57622	195	0	0
T4	579794	24	0	0
T5	276386	384	0	0
T7	70414	196	0	0
T8	6732	87	0	0
T9	1211	0	0	0
T10	9839	10	0	0
T11	2852	62	0	0
T12	0	73	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	230827	0	0
T1	22899	52	0	0
T2	3769	41	0	0
T3	57622	195	0	0
T4	579794	24	0	0
T5	276386	384	0	0
T7	70414	196	0	0
T8	6732	87	0	0
T9	1211	0	0	0
T10	9839	10	0	0
T11	2852	62	0	0
T12	0	73	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	5066894	0	0
T1	22899	1037	0	0
T2	3769	168	0	0
T3	57622	1311	0	0
T4	579794	63741	0	0
T5	276386	6266	0	0
T7	70414	2181	0	0
T8	6732	554	0	0
T9	1211	0	0	0
T10	9839	297	0	0
T11	2852	181	0	0
T12	0	560	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	230827	0	0
T1	22899	52	0	0
T2	3769	41	0	0
T3	57622	195	0	0
T4	579794	24	0	0
T5	276386	384	0	0
T7	70414	196	0	0
T8	6732	87	0	0
T9	1211	0	0	0
T10	9839	10	0	0
T11	2852	62	0	0
T12	0	73	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	230827	0	0
T1	22899	52	0	0
T2	3769	41	0	0
T3	57622	195	0	0
T4	579794	24	0	0
T5	276386	384	0	0
T7	70414	196	0	0
T8	6732	87	0	0
T9	1211	0	0	0
T10	9839	10	0	0
T11	2852	62	0	0
T12	0	73	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	1239232	0	0
T1	22899	120	0	0
T2	3769	71	0	0
T3	57622	256	0	0
T4	579794	431	0	0
T5	276386	659	0	0
T7	70414	295	0	0
T8	6732	118	0	0
T9	1211	0	0	0
T10	9839	20	0	0
T11	2852	95	0	0
T12	0	92	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	230827	0	0
T1	22899	52	0	0
T2	3769	41	0	0
T3	57622	195	0	0
T4	579794	24	0	0
T5	276386	384	0	0
T7	70414	196	0	0
T8	6732	87	0	0
T9	1211	0	0	0
T10	9839	10	0	0
T11	2852	62	0	0
T12	0	73	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	234184	0	0
GntImpliesValid_A	413303374	234184	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	234184	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	5189482	0	0
ReadyAndValidImplyGrant_A	413303374	234184	0	0
ReqAndReadyImplyGrant_A	413303374	234184	0	0
ReqImpliesValid_A	413303374	1243156	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	234184	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	234184	0	0
T1	22899	61	0	0
T2	3769	40	0	0
T3	57622	189	0	0
T4	579794	25	0	0
T5	276386	387	0	0
T7	70414	165	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	14	0	0
T11	2852	57	0	0
T12	0	86	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	234184	0	0
T1	22899	61	0	0
T2	3769	40	0	0
T3	57622	189	0	0
T4	579794	25	0	0
T5	276386	387	0	0
T7	70414	165	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	14	0	0
T11	2852	57	0	0
T12	0	86	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	234184	0	0
T1	22899	61	0	0
T2	3769	40	0	0
T3	57622	189	0	0
T4	579794	25	0	0
T5	276386	387	0	0
T7	70414	165	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	14	0	0
T11	2852	57	0	0
T12	0	86	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	5189482	0	0
T1	22899	695	0	0
T2	3769	239	0	0
T3	57622	1553	0	0
T4	579794	8685	0	0
T5	276386	5677	0	0
T7	70414	1276	0	0
T8	6732	1418	0	0
T9	1211	0	0	0
T10	9839	125	0	0
T11	2852	171	0	0
T12	0	1141	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	234184	0	0
T1	22899	61	0	0
T2	3769	40	0	0
T3	57622	189	0	0
T4	579794	25	0	0
T5	276386	387	0	0
T7	70414	165	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	14	0	0
T11	2852	57	0	0
T12	0	86	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	234184	0	0
T1	22899	61	0	0
T2	3769	40	0	0
T3	57622	189	0	0
T4	579794	25	0	0
T5	276386	387	0	0
T7	70414	165	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	14	0	0
T11	2852	57	0	0
T12	0	86	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	1243156	0	0
T1	22899	73	0	0
T2	3769	68	0	0
T3	57622	265	0	0
T4	579794	818	0	0
T5	276386	482	0	0
T7	70414	246	0	0
T8	6732	391	0	0
T9	1211	0	0	0
T10	9839	31	0	0
T11	2852	84	0	0
T12	0	197	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	234184	0	0
T1	22899	61	0	0
T2	3769	40	0	0
T3	57622	189	0	0
T4	579794	25	0	0
T5	276386	387	0	0
T7	70414	165	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	14	0	0
T11	2852	57	0	0
T12	0	86	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	233303	0	0
GntImpliesValid_A	413303374	233303	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	233303	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	2977633	0	0
ReadyAndValidImplyGrant_A	413303374	233303	0	0
ReqAndReadyImplyGrant_A	413303374	233303	0	0
ReqImpliesValid_A	413303374	608946	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	233303	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	233303	0	0
T1	22899	71	0	0
T2	3769	44	0	0
T3	57622	190	0	0
T4	579794	35	0	0
T5	276386	463	0	0
T7	70414	188	0	0
T8	6732	105	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	57	0	0
T12	0	89	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	233303	0	0
T1	22899	71	0	0
T2	3769	44	0	0
T3	57622	190	0	0
T4	579794	35	0	0
T5	276386	463	0	0
T7	70414	188	0	0
T8	6732	105	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	57	0	0
T12	0	89	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	233303	0	0
T1	22899	71	0	0
T2	3769	44	0	0
T3	57622	190	0	0
T4	579794	35	0	0
T5	276386	463	0	0
T7	70414	188	0	0
T8	6732	105	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	57	0	0
T12	0	89	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	2977633	0	0
T1	22899	480	0	0
T2	3769	39	0	0
T3	57622	1409	0	0
T4	579794	15426	0	0
T5	276386	3345	0	0
T7	70414	1463	0	0
T8	6732	100	0	0
T9	1211	1	0	0
T10	9839	87	0	0
T11	2852	54	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	233303	0	0
T1	22899	71	0	0
T2	3769	44	0	0
T3	57622	190	0	0
T4	579794	35	0	0
T5	276386	463	0	0
T7	70414	188	0	0
T8	6732	105	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	57	0	0
T12	0	89	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	233303	0	0
T1	22899	71	0	0
T2	3769	44	0	0
T3	57622	190	0	0
T4	579794	35	0	0
T5	276386	463	0	0
T7	70414	188	0	0
T8	6732	105	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	57	0	0
T12	0	89	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	608946	0	0
T1	22899	113	0	0
T2	3769	50	0	0
T3	57622	236	0	0
T4	579794	35	0	0
T5	276386	492	0	0
T7	70414	230	0	0
T8	6732	111	0	0
T9	1211	0	0	0
T10	9839	25	0	0
T11	2852	61	0	0
T12	0	108	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	233303	0	0
T1	22899	71	0	0
T2	3769	44	0	0
T3	57622	190	0	0
T4	579794	35	0	0
T5	276386	463	0	0
T7	70414	188	0	0
T8	6732	105	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	57	0	0
T12	0	89	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	224688	0	0
GntImpliesValid_A	413303374	224688	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	224688	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	2829738	0	0
ReadyAndValidImplyGrant_A	413303374	224688	0	0
ReqAndReadyImplyGrant_A	413303374	224688	0	0
ReqImpliesValid_A	413303374	524542	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	224688	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	224688	0	0
T1	22899	57	0	0
T2	3769	38	0	0
T3	57622	175	0	0
T4	579794	23	0	0
T5	276386	383	0	0
T7	70414	213	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	50	0	0
T12	0	90	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	224688	0	0
T1	22899	57	0	0
T2	3769	38	0	0
T3	57622	175	0	0
T4	579794	23	0	0
T5	276386	383	0	0
T7	70414	213	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	50	0	0
T12	0	90	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	224688	0	0
T1	22899	57	0	0
T2	3769	38	0	0
T3	57622	175	0	0
T4	579794	23	0	0
T5	276386	383	0	0
T7	70414	213	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	50	0	0
T12	0	90	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	2829738	0	0
T1	22899	469	0	0
T2	3769	38	0	0
T3	57622	1262	0	0
T4	579794	8600	0	0
T5	276386	2984	0	0
T7	70414	1541	0	0
T8	6732	87	0	0
T9	1211	1	0	0
T10	9839	71	0	0
T11	2852	48	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	224688	0	0
T1	22899	57	0	0
T2	3769	38	0	0
T3	57622	175	0	0
T4	579794	23	0	0
T5	276386	383	0	0
T7	70414	213	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	50	0	0
T12	0	90	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	224688	0	0
T1	22899	57	0	0
T2	3769	38	0	0
T3	57622	175	0	0
T4	579794	23	0	0
T5	276386	383	0	0
T7	70414	213	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	50	0	0
T12	0	90	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	524542	0	0
T1	22899	75	0	0
T2	3769	39	0	0
T3	57622	236	0	0
T4	579794	23	0	0
T5	276386	431	0	0
T7	70414	292	0	0
T8	6732	96	0	0
T9	1211	0	0	0
T10	9839	29	0	0
T11	2852	53	0	0
T12	0	100	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	224688	0	0
T1	22899	57	0	0
T2	3769	38	0	0
T3	57622	175	0	0
T4	579794	23	0	0
T5	276386	383	0	0
T7	70414	213	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	50	0	0
T12	0	90	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	224274	0	0
GntImpliesValid_A	413303374	224274	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	224274	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	2862215	0	0
ReadyAndValidImplyGrant_A	413303374	224274	0	0
ReqAndReadyImplyGrant_A	413303374	224274	0	0
ReqImpliesValid_A	413303374	560027	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	224274	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	224274	0	0
T1	22899	70	0	0
T2	3769	38	0	0
T3	57622	185	0	0
T4	579794	32	0	0
T5	276386	407	0	0
T7	70414	211	0	0
T8	6732	117	0	0
T9	1211	0	0	0
T10	9839	5	0	0
T11	2852	56	0	0
T12	0	86	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	224274	0	0
T1	22899	70	0	0
T2	3769	38	0	0
T3	57622	185	0	0
T4	579794	32	0	0
T5	276386	407	0	0
T7	70414	211	0	0
T8	6732	117	0	0
T9	1211	0	0	0
T10	9839	5	0	0
T11	2852	56	0	0
T12	0	86	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	224274	0	0
T1	22899	70	0	0
T2	3769	38	0	0
T3	57622	185	0	0
T4	579794	32	0	0
T5	276386	407	0	0
T7	70414	211	0	0
T8	6732	117	0	0
T9	1211	0	0	0
T10	9839	5	0	0
T11	2852	56	0	0
T12	0	86	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	2862215	0	0
T1	22899	515	0	0
T2	3769	37	0	0
T3	57622	1336	0	0
T4	579794	10921	0	0
T5	276386	3066	0	0
T7	70414	1679	0	0
T8	6732	116	0	0
T9	1211	1	0	0
T10	9839	32	0	0
T11	2852	53	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	224274	0	0
T1	22899	70	0	0
T2	3769	38	0	0
T3	57622	185	0	0
T4	579794	32	0	0
T5	276386	407	0	0
T7	70414	211	0	0
T8	6732	117	0	0
T9	1211	0	0	0
T10	9839	5	0	0
T11	2852	56	0	0
T12	0	86	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	224274	0	0
T1	22899	70	0	0
T2	3769	38	0	0
T3	57622	185	0	0
T4	579794	32	0	0
T5	276386	407	0	0
T7	70414	211	0	0
T8	6732	117	0	0
T9	1211	0	0	0
T10	9839	5	0	0
T11	2852	56	0	0
T12	0	86	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	560027	0	0
T1	22899	116	0	0
T2	3769	40	0	0
T3	57622	220	0	0
T4	579794	589	0	0
T5	276386	474	0	0
T7	70414	264	0	0
T8	6732	119	0	0
T9	1211	0	0	0
T10	9839	5	0	0
T11	2852	60	0	0
T12	0	93	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	224274	0	0
T1	22899	70	0	0
T2	3769	38	0	0
T3	57622	185	0	0
T4	579794	32	0	0
T5	276386	407	0	0
T7	70414	211	0	0
T8	6732	117	0	0
T9	1211	0	0	0
T10	9839	5	0	0
T11	2852	56	0	0
T12	0	86	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	221995	0	0
GntImpliesValid_A	413303374	221995	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	221995	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	2925212	0	0
ReadyAndValidImplyGrant_A	413303374	221995	0	0
ReqAndReadyImplyGrant_A	413303374	221995	0	0
ReqImpliesValid_A	413303374	550473	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	221995	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	221995	0	0
T1	22899	55	0	0
T2	3769	40	0	0
T3	57622	195	0	0
T4	579794	35	0	0
T5	276386	392	0	0
T7	70414	193	0	0
T8	6732	107	0	0
T9	1211	0	0	0
T10	9839	16	0	0
T11	2852	46	0	0
T12	0	77	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	221995	0	0
T1	22899	55	0	0
T2	3769	40	0	0
T3	57622	195	0	0
T4	579794	35	0	0
T5	276386	392	0	0
T7	70414	193	0	0
T8	6732	107	0	0
T9	1211	0	0	0
T10	9839	16	0	0
T11	2852	46	0	0
T12	0	77	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	221995	0	0
T1	22899	55	0	0
T2	3769	40	0	0
T3	57622	195	0	0
T4	579794	35	0	0
T5	276386	392	0	0
T7	70414	193	0	0
T8	6732	107	0	0
T9	1211	0	0	0
T10	9839	16	0	0
T11	2852	46	0	0
T12	0	77	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	2925212	0	0
T1	22899	385	0	0
T2	3769	40	0	0
T3	57622	1600	0	0
T4	579794	13450	0	0
T5	276386	2927	0	0
T7	70414	1425	0	0
T8	6732	95	0	0
T9	1211	1	0	0
T10	9839	119	0	0
T11	2852	43	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	221995	0	0
T1	22899	55	0	0
T2	3769	40	0	0
T3	57622	195	0	0
T4	579794	35	0	0
T5	276386	392	0	0
T7	70414	193	0	0
T8	6732	107	0	0
T9	1211	0	0	0
T10	9839	16	0	0
T11	2852	46	0	0
T12	0	77	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	221995	0	0
T1	22899	55	0	0
T2	3769	40	0	0
T3	57622	195	0	0
T4	579794	35	0	0
T5	276386	392	0	0
T7	70414	193	0	0
T8	6732	107	0	0
T9	1211	0	0	0
T10	9839	16	0	0
T11	2852	46	0	0
T12	0	77	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	550473	0	0
T1	22899	85	0	0
T2	3769	41	0	0
T3	57622	236	0	0
T4	579794	1250	0	0
T5	276386	426	0	0
T7	70414	261	0	0
T8	6732	120	0	0
T9	1211	0	0	0
T10	9839	20	0	0
T11	2852	50	0	0
T12	0	90	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	221995	0	0
T1	22899	55	0	0
T2	3769	40	0	0
T3	57622	195	0	0
T4	579794	35	0	0
T5	276386	392	0	0
T7	70414	193	0	0
T8	6732	107	0	0
T9	1211	0	0	0
T10	9839	16	0	0
T11	2852	46	0	0
T12	0	77	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	226754	0	0
GntImpliesValid_A	413303374	226754	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	226754	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	2900106	0	0
ReadyAndValidImplyGrant_A	413303374	226754	0	0
ReqAndReadyImplyGrant_A	413303374	226754	0	0
ReqImpliesValid_A	413303374	589337	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	226754	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	226754	0	0
T1	22899	63	0	0
T2	3769	27	0	0
T3	57622	217	0	0
T4	579794	26	0	0
T5	276386	419	0	0
T7	70414	174	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	12	0	0
T11	2852	47	0	0
T12	0	97	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	226754	0	0
T1	22899	63	0	0
T2	3769	27	0	0
T3	57622	217	0	0
T4	579794	26	0	0
T5	276386	419	0	0
T7	70414	174	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	12	0	0
T11	2852	47	0	0
T12	0	97	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	226754	0	0
T1	22899	63	0	0
T2	3769	27	0	0
T3	57622	217	0	0
T4	579794	26	0	0
T5	276386	419	0	0
T7	70414	174	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	12	0	0
T11	2852	47	0	0
T12	0	97	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	2900106	0	0
T1	22899	482	0	0
T2	3769	28	0	0
T3	57622	1641	0	0
T4	579794	6987	0	0
T5	276386	3352	0	0
T7	70414	1333	0	0
T8	6732	81	0	0
T9	1211	1	0	0
T10	9839	78	0	0
T11	2852	46	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	226754	0	0
T1	22899	63	0	0
T2	3769	27	0	0
T3	57622	217	0	0
T4	579794	26	0	0
T5	276386	419	0	0
T7	70414	174	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	12	0	0
T11	2852	47	0	0
T12	0	97	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	226754	0	0
T1	22899	63	0	0
T2	3769	27	0	0
T3	57622	217	0	0
T4	579794	26	0	0
T5	276386	419	0	0
T7	70414	174	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	12	0	0
T11	2852	47	0	0
T12	0	97	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	589337	0	0
T1	22899	91	0	0
T2	3769	27	0	0
T3	57622	362	0	0
T4	579794	597	0	0
T5	276386	463	0	0
T7	70414	186	0	0
T8	6732	96	0	0
T9	1211	0	0	0
T10	9839	12	0	0
T11	2852	49	0	0
T12	0	120	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	226754	0	0
T1	22899	63	0	0
T2	3769	27	0	0
T3	57622	217	0	0
T4	579794	26	0	0
T5	276386	419	0	0
T7	70414	174	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	12	0	0
T11	2852	47	0	0
T12	0	97	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	222709	0	0
GntImpliesValid_A	413303374	222709	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	222709	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	2883711	0	0
ReadyAndValidImplyGrant_A	413303374	222709	0	0
ReqAndReadyImplyGrant_A	413303374	222709	0	0
ReqImpliesValid_A	413303374	560921	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	222709	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	222709	0	0
T1	22899	60	0	0
T2	3769	36	0	0
T3	57622	176	0	0
T4	579794	23	0	0
T5	276386	401	0	0
T7	70414	207	0	0
T8	6732	100	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	55	0	0
T12	0	76	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	222709	0	0
T1	22899	60	0	0
T2	3769	36	0	0
T3	57622	176	0	0
T4	579794	23	0	0
T5	276386	401	0	0
T7	70414	207	0	0
T8	6732	100	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	55	0	0
T12	0	76	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	222709	0	0
T1	22899	60	0	0
T2	3769	36	0	0
T3	57622	176	0	0
T4	579794	23	0	0
T5	276386	401	0	0
T7	70414	207	0	0
T8	6732	100	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	55	0	0
T12	0	76	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	2883711	0	0
T1	22899	462	0	0
T2	3769	34	0	0
T3	57622	1406	0	0
T4	579794	4918	0	0
T5	276386	3158	0	0
T7	70414	1524	0	0
T8	6732	92	0	0
T9	1211	1	0	0
T10	9839	103	0	0
T11	2852	55	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	222709	0	0
T1	22899	60	0	0
T2	3769	36	0	0
T3	57622	176	0	0
T4	579794	23	0	0
T5	276386	401	0	0
T7	70414	207	0	0
T8	6732	100	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	55	0	0
T12	0	76	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	222709	0	0
T1	22899	60	0	0
T2	3769	36	0	0
T3	57622	176	0	0
T4	579794	23	0	0
T5	276386	401	0	0
T7	70414	207	0	0
T8	6732	100	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	55	0	0
T12	0	76	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	560921	0	0
T1	22899	85	0	0
T2	3769	39	0	0
T3	57622	224	0	0
T4	579794	829	0	0
T5	276386	451	0	0
T7	70414	278	0	0
T8	6732	109	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	56	0	0
T12	0	89	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	222709	0	0
T1	22899	60	0	0
T2	3769	36	0	0
T3	57622	176	0	0
T4	579794	23	0	0
T5	276386	401	0	0
T7	70414	207	0	0
T8	6732	100	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	55	0	0
T12	0	76	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	225526	0	0
GntImpliesValid_A	413303374	225526	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	225526	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	2880802	0	0
ReadyAndValidImplyGrant_A	413303374	225526	0	0
ReqAndReadyImplyGrant_A	413303374	225526	0	0
ReqImpliesValid_A	413303374	595176	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	225526	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	225526	0	0
T1	22899	68	0	0
T2	3769	39	0	0
T3	57622	160	0	0
T4	579794	40	0	0
T5	276386	426	0	0
T7	70414	210	0	0
T8	6732	78	0	0
T9	1211	0	0	0
T10	9839	12	0	0
T11	2852	70	0	0
T12	0	81	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	225526	0	0
T1	22899	68	0	0
T2	3769	39	0	0
T3	57622	160	0	0
T4	579794	40	0	0
T5	276386	426	0	0
T7	70414	210	0	0
T8	6732	78	0	0
T9	1211	0	0	0
T10	9839	12	0	0
T11	2852	70	0	0
T12	0	81	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	225526	0	0
T1	22899	68	0	0
T2	3769	39	0	0
T3	57622	160	0	0
T4	579794	40	0	0
T5	276386	426	0	0
T7	70414	210	0	0
T8	6732	78	0	0
T9	1211	0	0	0
T10	9839	12	0	0
T11	2852	70	0	0
T12	0	81	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	2880802	0	0
T1	22899	515	0	0
T2	3769	39	0	0
T3	57622	1163	0	0
T4	579794	10887	0	0
T5	276386	3036	0	0
T7	70414	1636	0	0
T8	6732	76	0	0
T9	1211	1	0	0
T10	9839	97	0	0
T11	2852	67	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	225526	0	0
T1	22899	68	0	0
T2	3769	39	0	0
T3	57622	160	0	0
T4	579794	40	0	0
T5	276386	426	0	0
T7	70414	210	0	0
T8	6732	78	0	0
T9	1211	0	0	0
T10	9839	12	0	0
T11	2852	70	0	0
T12	0	81	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	225526	0	0
T1	22899	68	0	0
T2	3769	39	0	0
T3	57622	160	0	0
T4	579794	40	0	0
T5	276386	426	0	0
T7	70414	210	0	0
T8	6732	78	0	0
T9	1211	0	0	0
T10	9839	12	0	0
T11	2852	70	0	0
T12	0	81	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	595176	0	0
T1	22899	98	0	0
T2	3769	40	0	0
T3	57622	180	0	0
T4	579794	565	0	0
T5	276386	523	0	0
T7	70414	418	0	0
T8	6732	81	0	0
T9	1211	0	0	0
T10	9839	12	0	0
T11	2852	74	0	0
T12	0	88	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	225526	0	0
T1	22899	68	0	0
T2	3769	39	0	0
T3	57622	160	0	0
T4	579794	40	0	0
T5	276386	426	0	0
T7	70414	210	0	0
T8	6732	78	0	0
T9	1211	0	0	0
T10	9839	12	0	0
T11	2852	70	0	0
T12	0	81	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	227856	0	0
GntImpliesValid_A	413303374	227856	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	227856	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	2929082	0	0
ReadyAndValidImplyGrant_A	413303374	227856	0	0
ReqAndReadyImplyGrant_A	413303374	227856	0	0
ReqImpliesValid_A	413303374	571990	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	227856	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	227856	0	0
T1	22899	61	0	0
T2	3769	42	0	0
T3	57622	207	0	0
T4	579794	22	0	0
T5	276386	385	0	0
T7	70414	176	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	6	0	0
T11	2852	48	0	0
T12	0	77	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	227856	0	0
T1	22899	61	0	0
T2	3769	42	0	0
T3	57622	207	0	0
T4	579794	22	0	0
T5	276386	385	0	0
T7	70414	176	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	6	0	0
T11	2852	48	0	0
T12	0	77	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	227856	0	0
T1	22899	61	0	0
T2	3769	42	0	0
T3	57622	207	0	0
T4	579794	22	0	0
T5	276386	385	0	0
T7	70414	176	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	6	0	0
T11	2852	48	0	0
T12	0	77	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	2929082	0	0
T1	22899	521	0	0
T2	3769	40	0	0
T3	57622	1430	0	0
T4	579794	9822	0	0
T5	276386	2973	0	0
T7	70414	1302	0	0
T8	6732	87	0	0
T9	1211	1	0	0
T10	9839	29	0	0
T11	2852	47	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	227856	0	0
T1	22899	61	0	0
T2	3769	42	0	0
T3	57622	207	0	0
T4	579794	22	0	0
T5	276386	385	0	0
T7	70414	176	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	6	0	0
T11	2852	48	0	0
T12	0	77	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	227856	0	0
T1	22899	61	0	0
T2	3769	42	0	0
T3	57622	207	0	0
T4	579794	22	0	0
T5	276386	385	0	0
T7	70414	176	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	6	0	0
T11	2852	48	0	0
T12	0	77	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	571990	0	0
T1	22899	78	0	0
T2	3769	45	0	0
T3	57622	295	0	0
T4	579794	315	0	0
T5	276386	430	0	0
T7	70414	223	0	0
T8	6732	96	0	0
T9	1211	0	0	0
T10	9839	6	0	0
T11	2852	50	0	0
T12	0	79	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	227856	0	0
T1	22899	61	0	0
T2	3769	42	0	0
T3	57622	207	0	0
T4	579794	22	0	0
T5	276386	385	0	0
T7	70414	176	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	6	0	0
T11	2852	48	0	0
T12	0	77	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	253267	0	0
GntImpliesValid_A	413303374	253267	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	253267	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	3026655	0	0
ReadyAndValidImplyGrant_A	413303374	253267	0	0
ReqAndReadyImplyGrant_A	413303374	253267	0	0
ReqImpliesValid_A	413303374	606343	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	253267	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	253267	0	0
T1	22899	78	0	0
T2	3769	60	0	0
T3	57622	177	0	0
T4	579794	27	0	0
T5	276386	454	0	0
T7	70414	192	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	5	0	0
T11	2852	62	0	0
T12	0	84	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	253267	0	0
T1	22899	78	0	0
T2	3769	60	0	0
T3	57622	177	0	0
T4	579794	27	0	0
T5	276386	454	0	0
T7	70414	192	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	5	0	0
T11	2852	62	0	0
T12	0	84	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	253267	0	0
T1	22899	78	0	0
T2	3769	60	0	0
T3	57622	177	0	0
T4	579794	27	0	0
T5	276386	454	0	0
T7	70414	192	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	5	0	0
T11	2852	62	0	0
T12	0	84	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	3026655	0	0
T1	22899	609	0	0
T2	3769	56	0	0
T3	57622	1429	0	0
T4	579794	10416	0	0
T5	276386	3441	0	0
T7	70414	1348	0	0
T8	6732	86	0	0
T9	1211	1	0	0
T10	9839	30	0	0
T11	2852	59	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	253267	0	0
T1	22899	78	0	0
T2	3769	60	0	0
T3	57622	177	0	0
T4	579794	27	0	0
T5	276386	454	0	0
T7	70414	192	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	5	0	0
T11	2852	62	0	0
T12	0	84	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	253267	0	0
T1	22899	78	0	0
T2	3769	60	0	0
T3	57622	177	0	0
T4	579794	27	0	0
T5	276386	454	0	0
T7	70414	192	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	5	0	0
T11	2852	62	0	0
T12	0	84	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	606343	0	0
T1	22899	118	0	0
T2	3769	65	0	0
T3	57622	259	0	0
T4	579794	27	0	0
T5	276386	526	0	0
T7	70414	287	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	5	0	0
T11	2852	66	0	0
T12	0	91	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	253267	0	0
T1	22899	78	0	0
T2	3769	60	0	0
T3	57622	177	0	0
T4	579794	27	0	0
T5	276386	454	0	0
T7	70414	192	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	5	0	0
T11	2852	62	0	0
T12	0	84	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	233676	0	0
GntImpliesValid_A	413303374	233676	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	233676	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	2927898	0	0
ReadyAndValidImplyGrant_A	413303374	233676	0	0
ReqAndReadyImplyGrant_A	413303374	233676	0	0
ReqImpliesValid_A	413303374	617091	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	233676	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	233676	0	0
T1	22899	65	0	0
T2	3769	25	0	0
T3	57622	181	0	0
T4	579794	31	0	0
T5	276386	382	0	0
T7	70414	203	0	0
T8	6732	86	0	0
T9	1211	0	0	0
T10	9839	13	0	0
T11	2852	47	0	0
T12	0	73	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	233676	0	0
T1	22899	65	0	0
T2	3769	25	0	0
T3	57622	181	0	0
T4	579794	31	0	0
T5	276386	382	0	0
T7	70414	203	0	0
T8	6732	86	0	0
T9	1211	0	0	0
T10	9839	13	0	0
T11	2852	47	0	0
T12	0	73	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	233676	0	0
T1	22899	65	0	0
T2	3769	25	0	0
T3	57622	181	0	0
T4	579794	31	0	0
T5	276386	382	0	0
T7	70414	203	0	0
T8	6732	86	0	0
T9	1211	0	0	0
T10	9839	13	0	0
T11	2852	47	0	0
T12	0	73	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	2927898	0	0
T1	22899	486	0	0
T2	3769	25	0	0
T3	57622	1402	0	0
T4	579794	11790	0	0
T5	276386	3023	0	0
T7	70414	1606	0	0
T8	6732	82	0	0
T9	1211	1	0	0
T10	9839	105	0	0
T11	2852	45	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	233676	0	0
T1	22899	65	0	0
T2	3769	25	0	0
T3	57622	181	0	0
T4	579794	31	0	0
T5	276386	382	0	0
T7	70414	203	0	0
T8	6732	86	0	0
T9	1211	0	0	0
T10	9839	13	0	0
T11	2852	47	0	0
T12	0	73	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	233676	0	0
T1	22899	65	0	0
T2	3769	25	0	0
T3	57622	181	0	0
T4	579794	31	0	0
T5	276386	382	0	0
T7	70414	203	0	0
T8	6732	86	0	0
T9	1211	0	0	0
T10	9839	13	0	0
T11	2852	47	0	0
T12	0	73	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	617091	0	0
T1	22899	93	0	0
T2	3769	26	0	0
T3	57622	231	0	0
T4	579794	507	0	0
T5	276386	423	0	0
T7	70414	319	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	14	0	0
T11	2852	50	0	0
T12	0	89	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	233676	0	0
T1	22899	65	0	0
T2	3769	25	0	0
T3	57622	181	0	0
T4	579794	31	0	0
T5	276386	382	0	0
T7	70414	203	0	0
T8	6732	86	0	0
T9	1211	0	0	0
T10	9839	13	0	0
T11	2852	47	0	0
T12	0	73	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	231487	0	0
GntImpliesValid_A	413303374	231487	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	231487	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	2904790	0	0
ReadyAndValidImplyGrant_A	413303374	231487	0	0
ReqAndReadyImplyGrant_A	413303374	231487	0	0
ReqImpliesValid_A	413303374	564094	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	231487	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	231487	0	0
T1	22899	66	0	0
T2	3769	42	0	0
T3	57622	170	0	0
T4	579794	27	0	0
T5	276386	393	0	0
T7	70414	220	0	0
T8	6732	84	0	0
T9	1211	0	0	0
T10	9839	8	0	0
T11	2852	48	0	0
T12	0	73	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	231487	0	0
T1	22899	66	0	0
T2	3769	42	0	0
T3	57622	170	0	0
T4	579794	27	0	0
T5	276386	393	0	0
T7	70414	220	0	0
T8	6732	84	0	0
T9	1211	0	0	0
T10	9839	8	0	0
T11	2852	48	0	0
T12	0	73	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	231487	0	0
T1	22899	66	0	0
T2	3769	42	0	0
T3	57622	170	0	0
T4	579794	27	0	0
T5	276386	393	0	0
T7	70414	220	0	0
T8	6732	84	0	0
T9	1211	0	0	0
T10	9839	8	0	0
T11	2852	48	0	0
T12	0	73	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	2904790	0	0
T1	22899	495	0	0
T2	3769	42	0	0
T3	57622	1291	0	0
T4	579794	10025	0	0
T5	276386	3010	0	0
T7	70414	1591	0	0
T8	6732	83	0	0
T9	1211	1	0	0
T10	9839	77	0	0
T11	2852	48	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	231487	0	0
T1	22899	66	0	0
T2	3769	42	0	0
T3	57622	170	0	0
T4	579794	27	0	0
T5	276386	393	0	0
T7	70414	220	0	0
T8	6732	84	0	0
T9	1211	0	0	0
T10	9839	8	0	0
T11	2852	48	0	0
T12	0	73	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	231487	0	0
T1	22899	66	0	0
T2	3769	42	0	0
T3	57622	170	0	0
T4	579794	27	0	0
T5	276386	393	0	0
T7	70414	220	0	0
T8	6732	84	0	0
T9	1211	0	0	0
T10	9839	8	0	0
T11	2852	48	0	0
T12	0	73	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	564094	0	0
T1	22899	80	0	0
T2	3769	43	0	0
T3	57622	250	0	0
T4	579794	315	0	0
T5	276386	465	0	0
T7	70414	374	0	0
T8	6732	86	0	0
T9	1211	0	0	0
T10	9839	8	0	0
T11	2852	49	0	0
T12	0	79	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	231487	0	0
T1	22899	66	0	0
T2	3769	42	0	0
T3	57622	170	0	0
T4	579794	27	0	0
T5	276386	393	0	0
T7	70414	220	0	0
T8	6732	84	0	0
T9	1211	0	0	0
T10	9839	8	0	0
T11	2852	48	0	0
T12	0	73	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	222451	0	0
GntImpliesValid_A	413303374	222451	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	222451	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	2814387	0	0
ReadyAndValidImplyGrant_A	413303374	222451	0	0
ReqAndReadyImplyGrant_A	413303374	222451	0	0
ReqImpliesValid_A	413303374	554211	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	222451	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	222451	0	0
T1	22899	66	0	0
T2	3769	41	0	0
T3	57622	183	0	0
T4	579794	33	0	0
T5	276386	398	0	0
T7	70414	230	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	17	0	0
T11	2852	51	0	0
T12	0	90	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	222451	0	0
T1	22899	66	0	0
T2	3769	41	0	0
T3	57622	183	0	0
T4	579794	33	0	0
T5	276386	398	0	0
T7	70414	230	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	17	0	0
T11	2852	51	0	0
T12	0	90	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	222451	0	0
T1	22899	66	0	0
T2	3769	41	0	0
T3	57622	183	0	0
T4	579794	33	0	0
T5	276386	398	0	0
T7	70414	230	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	17	0	0
T11	2852	51	0	0
T12	0	90	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	2814387	0	0
T1	22899	434	0	0
T2	3769	42	0	0
T3	57622	1318	0	0
T4	579794	12982	0	0
T5	276386	2986	0	0
T7	70414	1675	0	0
T8	6732	88	0	0
T9	1211	1	0	0
T10	9839	131	0	0
T11	2852	48	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	222451	0	0
T1	22899	66	0	0
T2	3769	41	0	0
T3	57622	183	0	0
T4	579794	33	0	0
T5	276386	398	0	0
T7	70414	230	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	17	0	0
T11	2852	51	0	0
T12	0	90	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	222451	0	0
T1	22899	66	0	0
T2	3769	41	0	0
T3	57622	183	0	0
T4	579794	33	0	0
T5	276386	398	0	0
T7	70414	230	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	17	0	0
T11	2852	51	0	0
T12	0	90	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	554211	0	0
T1	22899	87	0	0
T2	3769	41	0	0
T3	57622	255	0	0
T4	579794	771	0	0
T5	276386	437	0	0
T7	70414	371	0	0
T8	6732	95	0	0
T9	1211	0	0	0
T10	9839	33	0	0
T11	2852	55	0	0
T12	0	106	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	222451	0	0
T1	22899	66	0	0
T2	3769	41	0	0
T3	57622	183	0	0
T4	579794	33	0	0
T5	276386	398	0	0
T7	70414	230	0	0
T8	6732	91	0	0
T9	1211	0	0	0
T10	9839	17	0	0
T11	2852	51	0	0
T12	0	90	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	234025	0	0
GntImpliesValid_A	413303374	234025	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	234025	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	2902655	0	0
ReadyAndValidImplyGrant_A	413303374	234025	0	0
ReqAndReadyImplyGrant_A	413303374	234025	0	0
ReqImpliesValid_A	413303374	610711	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	234025	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	234025	0	0
T1	22899	63	0	0
T2	3769	25	0	0
T3	57622	220	0	0
T4	579794	32	0	0
T5	276386	417	0	0
T7	70414	198	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	51	0	0
T12	0	63	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	234025	0	0
T1	22899	63	0	0
T2	3769	25	0	0
T3	57622	220	0	0
T4	579794	32	0	0
T5	276386	417	0	0
T7	70414	198	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	51	0	0
T12	0	63	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	234025	0	0
T1	22899	63	0	0
T2	3769	25	0	0
T3	57622	220	0	0
T4	579794	32	0	0
T5	276386	417	0	0
T7	70414	198	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	51	0	0
T12	0	63	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	2902655	0	0
T1	22899	518	0	0
T2	3769	25	0	0
T3	57622	1573	0	0
T4	579794	8064	0	0
T5	276386	3150	0	0
T7	70414	1432	0	0
T8	6732	85	0	0
T9	1211	1	0	0
T10	9839	74	0	0
T11	2852	48	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	234025	0	0
T1	22899	63	0	0
T2	3769	25	0	0
T3	57622	220	0	0
T4	579794	32	0	0
T5	276386	417	0	0
T7	70414	198	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	51	0	0
T12	0	63	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	234025	0	0
T1	22899	63	0	0
T2	3769	25	0	0
T3	57622	220	0	0
T4	579794	32	0	0
T5	276386	417	0	0
T7	70414	198	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	51	0	0
T12	0	63	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	610711	0	0
T1	22899	79	0	0
T2	3769	26	0	0
T3	57622	339	0	0
T4	579794	339	0	0
T5	276386	454	0	0
T7	70414	275	0	0
T8	6732	92	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	55	0	0
T12	0	80	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	234025	0	0
T1	22899	63	0	0
T2	3769	25	0	0
T3	57622	220	0	0
T4	579794	32	0	0
T5	276386	417	0	0
T7	70414	198	0	0
T8	6732	88	0	0
T9	1211	0	0	0
T10	9839	11	0	0
T11	2852	51	0	0
T12	0	63	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	227282	0	0
GntImpliesValid_A	413303374	227282	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	227282	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	2879046	0	0
ReadyAndValidImplyGrant_A	413303374	227282	0	0
ReqAndReadyImplyGrant_A	413303374	227282	0	0
ReqImpliesValid_A	413303374	556697	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	0	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	227282	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	227282	0	0
T1	22899	60	0	0
T2	3769	32	0	0
T3	57622	182	0	0
T4	579794	28	0	0
T5	276386	401	0	0
T7	70414	185	0	0
T8	6732	74	0	0
T9	1211	473	0	0
T10	9839	13	0	0
T11	2852	54	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	227282	0	0
T1	22899	60	0	0
T2	3769	32	0	0
T3	57622	182	0	0
T4	579794	28	0	0
T5	276386	401	0	0
T7	70414	185	0	0
T8	6732	74	0	0
T9	1211	473	0	0
T10	9839	13	0	0
T11	2852	54	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	227282	0	0
T1	22899	60	0	0
T2	3769	32	0	0
T3	57622	182	0	0
T4	579794	28	0	0
T5	276386	401	0	0
T7	70414	185	0	0
T8	6732	74	0	0
T9	1211	473	0	0
T10	9839	13	0	0
T11	2852	54	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	2879046	0	0
T1	22899	453	0	0
T2	3769	30	0	0
T3	57622	1383	0	0
T4	579794	10184	0	0
T5	276386	3074	0	0
T7	70414	1387	0	0
T8	6732	73	0	0
T9	1211	5	0	0
T10	9839	90	0	0
T11	2852	52	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	227282	0	0
T1	22899	60	0	0
T2	3769	32	0	0
T3	57622	182	0	0
T4	579794	28	0	0
T5	276386	401	0	0
T7	70414	185	0	0
T8	6732	74	0	0
T9	1211	473	0	0
T10	9839	13	0	0
T11	2852	54	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	227282	0	0
T1	22899	60	0	0
T2	3769	32	0	0
T3	57622	182	0	0
T4	579794	28	0	0
T5	276386	401	0	0
T7	70414	185	0	0
T8	6732	74	0	0
T9	1211	473	0	0
T10	9839	13	0	0
T11	2852	54	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	556697	0	0
T1	22899	93	0	0
T2	3769	35	0	0
T3	57622	227	0	0
T4	579794	1228	0	0
T5	276386	461	0	0
T7	70414	253	0	0
T8	6732	76	0	0
T9	1211	942	0	0
T10	9839	19	0	0
T11	2852	57	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	227282	0	0
T1	22899	60	0	0
T2	3769	32	0	0
T3	57622	182	0	0
T4	579794	28	0	0
T5	276386	401	0	0
T7	70414	185	0	0
T8	6732	74	0	0
T9	1211	473	0	0
T10	9839	13	0	0
T11	2852	54	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	941147	0	0
GntImpliesValid_A	413303374	941147	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	941147	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	11004175	0	0
ReadyAndValidImplyGrant_A	413303374	941147	0	0
ReqAndReadyImplyGrant_A	413303374	941147	0	0
ReqImpliesValid_A	413303374	2364961	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	22176	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	941147	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	941147	0	0
T1	22899	209	0	0
T2	3769	108	0	0
T3	57622	740	0	0
T4	579794	158	0	0
T5	276386	2477	0	0
T7	70414	819	0	0
T8	6732	362	0	0
T9	1211	73	0	0
T10	9839	44	0	0
T11	2852	190	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	941147	0	0
T1	22899	209	0	0
T2	3769	108	0	0
T3	57622	740	0	0
T4	579794	158	0	0
T5	276386	2477	0	0
T7	70414	819	0	0
T8	6732	362	0	0
T9	1211	73	0	0
T10	9839	44	0	0
T11	2852	190	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	941147	0	0
T1	22899	209	0	0
T2	3769	108	0	0
T3	57622	740	0	0
T4	579794	158	0	0
T5	276386	2477	0	0
T7	70414	819	0	0
T8	6732	362	0	0
T9	1211	73	0	0
T10	9839	44	0	0
T11	2852	190	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	11004175	0	0
T1	22899	1311	0	0
T2	3769	1	0	0
T3	57622	4974	0	0
T4	579794	50398	0	0
T5	276386	13046	0	0
T7	70414	5294	0	0
T8	6732	1	0	0
T9	1211	1	0	0
T10	9839	300	0	0
T11	2852	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	941147	0	0
T1	22899	209	0	0
T2	3769	108	0	0
T3	57622	740	0	0
T4	579794	158	0	0
T5	276386	2477	0	0
T7	70414	819	0	0
T8	6732	362	0	0
T9	1211	73	0	0
T10	9839	44	0	0
T11	2852	190	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	941147	0	0
T1	22899	209	0	0
T2	3769	108	0	0
T3	57622	740	0	0
T4	579794	158	0	0
T5	276386	2477	0	0
T7	70414	819	0	0
T8	6732	362	0	0
T9	1211	73	0	0
T10	9839	44	0	0
T11	2852	190	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	2364961	0	0
T1	22899	355	0	0
T2	3769	108	0	0
T3	57622	1306	0	0
T4	579794	3159	0	0
T5	276386	4850	0	0
T7	70414	1343	0	0
T8	6732	362	0	0
T9	1211	73	0	0
T10	9839	58	0	0
T11	2852	190	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	22176	0	900
T5	276386	29	0	1
T8	6732	6	0	1
T9	1211	0	0	1
T10	9839	0	0	1
T11	2852	1	0	1
T12	955061	0	0	1
T13	381485	0	0	1
T14	0	14	0	0
T16	0	9	0	0
T17	0	4	0	0
T18	0	292	0	0
T19	0	7	0	0
T20	0	6	0	0
T21	0	351	0	0
T22	82067	0	0	1
T23	378674	0	0	1
T24	154171	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	941147	0	0
T1	22899	209	0	0
T2	3769	108	0	0
T3	57622	740	0	0
T4	579794	158	0	0
T5	276386	2477	0	0
T7	70414	819	0	0
T8	6732	362	0	0
T9	1211	73	0	0
T10	9839	44	0	0
T11	2852	190	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413303374	413182995	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413303374	917945	0	0
GntImpliesValid_A	413303374	917945	0	0
GrantKnown_A	413303374	413182995	0	0
IdxKnown_A	413303374	413182995	0	0
IndexIsCorrect_A	413303374	917945	0	0
LockArbDecision_A	413303374	0	0	0
NoReadyValidNoGrant_A	413303374	345952747	0	0
ReadyAndValidImplyGrant_A	413303374	917945	0	0
ReqAndReadyImplyGrant_A	413303374	917945	0	0
ReqImpliesValid_A	413303374	12870008	0	0
ReqStaysHighUntilGranted0_M	413303374	0	0	0
RoundRobin_A	413303374	34869	0	900
ValidKnown_A	413303374	413182995	0	0
gen_data_port_assertion.DataFlow_A	413303374	917945	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	917945	0	0
T1	22899	195	0	0
T2	3769	131	0	0
T3	57622	779	0	0
T4	579794	140	0	0
T5	276386	1729	0	0
T7	70414	826	0	0
T8	6732	340	0	0
T9	1211	78	0	0
T10	9839	46	0	0
T11	2852	163	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	917945	0	0
T1	22899	195	0	0
T2	3769	131	0	0
T3	57622	779	0	0
T4	579794	140	0	0
T5	276386	1729	0	0
T7	70414	826	0	0
T8	6732	340	0	0
T9	1211	78	0	0
T10	9839	46	0	0
T11	2852	163	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	917945	0	0
T1	22899	195	0	0
T2	3769	131	0	0
T3	57622	779	0	0
T4	579794	140	0	0
T5	276386	1729	0	0
T7	70414	826	0	0
T8	6732	340	0	0
T9	1211	78	0	0
T10	9839	46	0	0
T11	2852	163	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	345952747	0	0
T1	22899	19004	0	0
T2	3769	1	0	0
T3	57622	46318	0	0
T4	579794	507788	0	0
T5	276386	239017	0	0
T7	70414	58243	0	0
T8	6732	1	0	0
T9	1211	1	0	0
T10	9839	8528	0	0
T11	2852	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	917945	0	0
T1	22899	195	0	0
T2	3769	131	0	0
T3	57622	779	0	0
T4	579794	140	0	0
T5	276386	1729	0	0
T7	70414	826	0	0
T8	6732	340	0	0
T9	1211	78	0	0
T10	9839	46	0	0
T11	2852	163	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	917945	0	0
T1	22899	195	0	0
T2	3769	131	0	0
T3	57622	779	0	0
T4	579794	140	0	0
T5	276386	1729	0	0
T7	70414	826	0	0
T8	6732	340	0	0
T9	1211	78	0	0
T10	9839	46	0	0
T11	2852	163	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	12870008	0	0
T1	22899	1324	0	0
T2	3769	131	0	0
T3	57622	6815	0	0
T4	579794	45859	0	0
T5	276386	13866	0	0
T7	70414	6605	0	0
T8	6732	340	0	0
T9	1211	78	0	0
T10	9839	339	0	0
T11	2852	163	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	34869	0	900
T2	3769	1	0	1
T3	57622	3	0	1
T4	579794	0	0	1
T5	276386	1	0	1
T7	70414	0	0	1
T8	6732	4	0	1
T9	1211	0	0	1
T10	9839	0	0	1
T11	2852	3	0	1
T12	955061	0	0	1
T13	0	25	0	0
T14	0	15	0	0
T15	0	2	0	0
T16	0	4	0	0
T17	0	15	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	413182995	0	0
T1	22899	22823	0	0
T2	3769	3721	0	0
T3	57622	57591	0	0
T4	579794	579701	0	0
T5	276386	276139	0	0
T7	70414	70391	0	0
T8	6732	6673	0	0
T9	1211	1183	0	0
T10	9839	9813	0	0
T11	2852	2846	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413303374	917945	0	0
T1	22899	195	0	0
T2	3769	131	0	0
T3	57622	779	0	0
T4	579794	140	0	0
T5	276386	1729	0	0
T7	70414	826	0	0
T8	6732	340	0	0
T9	1211	78	0	0
T10	9839	46	0	0
T11	2852	163	0	0