Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1591103 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 252040 1 T1 285 T2 78 T3 23


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 626307 1 T1 722 T2 174 T3 53
values[0x0] 590222 1 T1 643 T2 189 T3 53
values[0x1] 626614 1 T1 694 T2 180 T3 59


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1229580 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 613563 1 T1 693 T2 178 T3 59


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28956 1 T1 130 T2 2 T3 4
valid_sources[0x01] 29641 1 T1 30 T2 23 T7 77
valid_sources[0x02] 29332 1 T1 25 T2 1 T7 73
valid_sources[0x03] 29280 1 T1 8 T3 1 T7 70
valid_sources[0x04] 28977 1 T1 47 T7 65 T8 27
valid_sources[0x05] 29057 1 T1 2 T3 3 T7 69
valid_sources[0x06] 28550 1 T1 25 T3 7 T7 66
valid_sources[0x07] 28869 1 T1 15 T2 12 T3 4
valid_sources[0x08] 28628 1 T1 5 T3 5 T7 60
valid_sources[0x09] 28151 1 T1 5 T3 2 T7 70
valid_sources[0x0a] 28154 1 T1 64 T2 18 T3 5
valid_sources[0x0b] 27954 1 T1 90 T3 1 T7 72
valid_sources[0x0c] 28223 1 T1 30 T3 2 T7 84
valid_sources[0x0d] 28045 1 T1 26 T3 4 T7 83
valid_sources[0x0e] 29855 1 T1 35 T2 1 T7 78
valid_sources[0x0f] 28105 1 T1 7 T2 14 T3 5
valid_sources[0x10] 28365 1 T1 126 T3 10 T7 89
valid_sources[0x11] 28826 1 T2 16 T3 9 T7 93
valid_sources[0x12] 28081 1 T1 30 T3 1 T7 84
valid_sources[0x13] 27918 1 T1 40 T2 1 T3 1
valid_sources[0x14] 28108 1 T1 38 T2 18 T7 87
valid_sources[0x15] 28680 1 T2 15 T3 1 T7 86
valid_sources[0x16] 29787 1 T2 3 T3 1 T7 82
valid_sources[0x17] 28145 1 T1 46 T2 19 T3 8
valid_sources[0x18] 29112 1 T1 42 T2 18 T3 2
valid_sources[0x19] 28887 1 T2 5 T7 88 T8 13
valid_sources[0x1a] 28397 1 T1 62 T3 1 T7 79
valid_sources[0x1b] 28890 1 T1 21 T2 9 T3 2
valid_sources[0x1c] 29174 1 T1 77 T2 9 T3 1
valid_sources[0x1d] 28970 1 T1 35 T2 5 T3 1
valid_sources[0x1e] 29217 1 T1 38 T2 32 T3 5
valid_sources[0x1f] 29734 1 T1 63 T2 12 T7 68
valid_sources[0x20] 28340 1 T1 23 T2 5 T3 2


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26556 1 T1 43 T2 8 T3 3
values[0x0] all_enables biggest_size 198831 1 T1 217 T2 62 T3 18
values[0x1] all_enables biggest_size 26653 1 T1 25 T2 8 T3 2


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1612598 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 261754 1 T1 274 T2 100 T3 19


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 643577 1 T1 749 T2 199 T3 55
values[0x0] 588686 1 T1 649 T2 205 T3 45
values[0x1] 642089 1 T1 650 T2 200 T3 63


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1237317 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 637035 1 T1 695 T2 218 T3 62


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28772 1 T1 27 T2 10 T3 3
valid_sources[0x01] 29200 1 T1 19 T2 6 T3 2
valid_sources[0x02] 28706 1 T1 4 T2 8 T3 4
valid_sources[0x03] 29695 1 T1 22 T2 10 T3 8
valid_sources[0x04] 29022 1 T1 35 T2 11 T3 1
valid_sources[0x05] 29252 1 T1 17 T2 10 T3 2
valid_sources[0x06] 29369 1 T1 45 T2 7 T7 48
valid_sources[0x07] 29485 1 T1 31 T2 8 T3 2
valid_sources[0x08] 30056 1 T1 99 T2 15 T3 3
valid_sources[0x09] 28809 1 T1 11 T2 8 T3 3
valid_sources[0x0a] 30003 1 T1 24 T2 8 T3 1
valid_sources[0x0b] 28439 1 T1 29 T2 6 T3 7
valid_sources[0x0c] 29871 1 T1 23 T2 12 T3 1
valid_sources[0x0d] 28498 1 T1 14 T2 8 T3 1
valid_sources[0x0e] 29876 1 T1 61 T2 10 T7 39
valid_sources[0x0f] 29384 1 T1 10 T2 4 T3 2
valid_sources[0x10] 29393 1 T1 21 T2 16 T3 6
valid_sources[0x11] 29594 1 T1 18 T2 11 T3 3
valid_sources[0x12] 28820 1 T1 10 T2 6 T3 2
valid_sources[0x13] 29642 1 T1 51 T2 7 T3 3
valid_sources[0x14] 28042 1 T1 63 T2 9 T3 3
valid_sources[0x15] 29055 1 T1 44 T2 7 T3 6
valid_sources[0x16] 30352 1 T1 58 T2 16 T3 4
valid_sources[0x17] 29100 1 T1 32 T2 3 T3 2
valid_sources[0x18] 29348 1 T1 5 T2 11 T7 69
valid_sources[0x19] 28966 1 T1 115 T2 11 T7 84
valid_sources[0x1a] 29124 1 T2 8 T3 4 T7 60
valid_sources[0x1b] 30033 1 T1 11 T2 7 T3 4
valid_sources[0x1c] 29155 1 T1 37 T2 3 T3 2
valid_sources[0x1d] 28995 1 T1 109 T2 8 T3 1
valid_sources[0x1e] 29050 1 T1 55 T2 8 T3 2
valid_sources[0x1f] 29606 1 T1 15 T2 8 T3 8
valid_sources[0x20] 28367 1 T1 1 T2 10 T3 1


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 28106 1 T1 20 T2 9 T3 4
values[0x0] all_enables biggest_size 205974 1 T1 232 T2 81 T3 14
values[0x1] all_enables biggest_size 27674 1 T1 22 T2 10 T3 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1609537 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 255129 1 T1 325 T2 79 T3 14


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 635050 1 T1 790 T2 202 T3 48
values[0x0] 596340 1 T1 736 T2 200 T3 40
values[0x1] 633276 1 T1 758 T2 210 T3 37


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1242914 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 621752 1 T1 803 T2 192 T3 39


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28303 1 T1 30 T2 18 T7 65
valid_sources[0x01] 30036 1 T1 30 T2 8 T7 75
valid_sources[0x02] 29593 1 T1 44 T2 2 T7 71
valid_sources[0x03] 29326 1 T1 40 T2 6 T7 82
valid_sources[0x04] 28820 1 T1 49 T2 10 T7 77
valid_sources[0x05] 28215 1 T1 47 T2 5 T3 15
valid_sources[0x06] 29792 1 T1 23 T2 9 T7 81
valid_sources[0x07] 29517 1 T1 36 T2 15 T7 75
valid_sources[0x08] 30071 1 T1 32 T2 6 T3 3
valid_sources[0x09] 28525 1 T1 30 T2 23 T3 9
valid_sources[0x0a] 29639 1 T1 35 T2 3 T3 1
valid_sources[0x0b] 29116 1 T1 32 T2 16 T7 85
valid_sources[0x0c] 29022 1 T1 31 T2 10 T7 74
valid_sources[0x0d] 28963 1 T1 44 T2 13 T7 78
valid_sources[0x0e] 29321 1 T1 28 T2 5 T3 10
valid_sources[0x0f] 29308 1 T1 40 T2 5 T7 69
valid_sources[0x10] 28421 1 T1 27 T2 11 T7 62
valid_sources[0x11] 29047 1 T1 43 T2 25 T7 84
valid_sources[0x12] 29278 1 T1 27 T2 12 T7 82
valid_sources[0x13] 29689 1 T1 27 T2 16 T7 80
valid_sources[0x14] 29620 1 T1 30 T2 6 T7 73
valid_sources[0x15] 28989 1 T1 28 T2 23 T7 74
valid_sources[0x16] 29086 1 T1 41 T2 1 T7 75
valid_sources[0x17] 27721 1 T1 38 T2 24 T3 2
valid_sources[0x18] 29986 1 T1 37 T2 14 T7 92
valid_sources[0x19] 27830 1 T1 35 T2 1 T7 82
valid_sources[0x1a] 29607 1 T1 33 T2 10 T7 77
valid_sources[0x1b] 29528 1 T1 35 T2 2 T7 69
valid_sources[0x1c] 30100 1 T1 40 T2 5 T7 78
valid_sources[0x1d] 28895 1 T1 45 T2 18 T7 75
valid_sources[0x1e] 28898 1 T1 33 T2 7 T3 8
valid_sources[0x1f] 28946 1 T1 33 T2 7 T7 63
valid_sources[0x20] 28312 1 T1 31 T7 67 T8 33


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 27262 1 T1 34 T2 3 T3 1
values[0x0] all_enables biggest_size 200621 1 T1 257 T2 69 T3 12
values[0x1] all_enables biggest_size 27246 1 T1 34 T2 7 T3 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%