Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8538734	0	0
GntImpliesValid_A	2147483647	8538734	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8538734	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	448590231	0	0
ReadyAndValidImplyGrant_A	2147483647	8538734	0	0
ReqAndReadyImplyGrant_A	2147483647	8538734	0	0
ReqImpliesValid_A	2147483647	35375181	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	66589	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8538734	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1148784	1147536	0	0
T2	18134880	18133728	0	0
T3	3327840	3325848	0	0
T7	16891416	16891248	0	0
T8	852600	851496	0	0
T9	8673624	8673528	0	0
T10	620184	619560	0	0
T11	281184	279696	0	0
T12	2285832	2266896	0	0
T13	6100800	6099864	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8538734	0	0
T1	1148784	3288	0	0
T2	18134880	1758	0	0
T3	3327840	453	0	0
T7	16891416	14108	0	0
T8	852600	2131	0	0
T9	8673624	8554	0	0
T10	620184	1656	0	0
T11	281184	909	0	0
T12	2285832	54253	0	0
T13	6100800	399	0	0
T14	0	17638	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8538734	0	0
T1	1148784	3288	0	0
T2	18134880	1758	0	0
T3	3327840	453	0	0
T7	16891416	14108	0	0
T8	852600	2131	0	0
T9	8673624	8554	0	0
T10	620184	1656	0	0
T11	281184	909	0	0
T12	2285832	54253	0	0
T13	6100800	399	0	0
T14	0	17638	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1148784	1147536	0	0
T2	18134880	18133728	0	0
T3	3327840	3325848	0	0
T7	16891416	16891248	0	0
T8	852600	851496	0	0
T9	8673624	8673528	0	0
T10	620184	619560	0	0
T11	281184	279696	0	0
T12	2285832	2266896	0	0
T13	6100800	6099864	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1148784	1147536	0	0
T2	18134880	18133728	0	0
T3	3327840	3325848	0	0
T7	16891416	16891248	0	0
T8	852600	851496	0	0
T9	8673624	8673528	0	0
T10	620184	619560	0	0
T11	281184	279696	0	0
T12	2285832	2266896	0	0
T13	6100800	6099864	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8538734	0	0
T1	1148784	3288	0	0
T2	18134880	1758	0	0
T3	3327840	453	0	0
T7	16891416	14108	0	0
T8	852600	2131	0	0
T9	8673624	8554	0	0
T10	620184	1656	0	0
T11	281184	909	0	0
T12	2285832	54253	0	0
T13	6100800	399	0	0
T14	0	17638	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	448590231	0	0
T1	1148784	64067	0	0
T2	18134880	1169259	0	0
T3	3327840	117314	0	0
T7	16891416	619427	0	0
T8	852600	47972	0	0
T9	8673624	2809036	0	0
T10	620184	33687	0	0
T11	281184	17367	0	0
T12	2285832	57114	0	0
T13	6100800	213150	0	0
T14	0	15889	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8538734	0	0
T1	1148784	3288	0	0
T2	18134880	1758	0	0
T3	3327840	453	0	0
T7	16891416	14108	0	0
T8	852600	2131	0	0
T9	8673624	8554	0	0
T10	620184	1656	0	0
T11	281184	909	0	0
T12	2285832	54253	0	0
T13	6100800	399	0	0
T14	0	17638	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8538734	0	0
T1	1148784	3288	0	0
T2	18134880	1758	0	0
T3	3327840	453	0	0
T7	16891416	14108	0	0
T8	852600	2131	0	0
T9	8673624	8554	0	0
T10	620184	1656	0	0
T11	281184	909	0	0
T12	2285832	54253	0	0
T13	6100800	399	0	0
T14	0	17638	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35375181	0	0
T1	1148784	6712	0	0
T2	18134880	132793	0	0
T3	3327840	778	0	0
T7	16891416	41423	0	0
T8	852600	4729	0	0
T9	8673624	534405	0	0
T10	620184	3424	0	0
T11	281184	2380	0	0
T12	2285832	65707	0	0
T13	6100800	727	0	0
T14	0	24591	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	66589	0	21600
T1	47866	1	0	1
T2	755620	0	0	1
T3	138660	0	0	1
T7	1407618	67	0	2
T8	71050	0	0	2
T9	722802	0	0	2
T10	51682	0	0	2
T11	23432	0	0	2
T12	190486	395	0	2
T13	508400	0	0	2
T14	99729	666	0	1
T15	0	345	0	0
T16	0	2	0	0
T17	0	1375	0	0
T18	0	10	0	0
T19	0	2	0	0
T20	0	990	0	0
T21	0	2	0	0
T22	0	4	0	0
T23	270562	0	0	1
T24	1839	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1148784	1147536	0	0
T2	18134880	18133728	0	0
T3	3327840	3325848	0	0
T7	16891416	16891248	0	0
T8	852600	851496	0	0
T9	8673624	8673528	0	0
T10	620184	619560	0	0
T11	281184	279696	0	0
T12	2285832	2266896	0	0
T13	6100800	6099864	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8538734	0	0
T1	1148784	3288	0	0
T2	18134880	1758	0	0
T3	3327840	453	0	0
T7	16891416	14108	0	0
T8	852600	2131	0	0
T9	8673624	8554	0	0
T10	620184	1656	0	0
T11	281184	909	0	0
T12	2285832	54253	0	0
T13	6100800	399	0	0
T14	0	17638	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	963266	0	0
GntImpliesValid_A	410625352	963266	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	963266	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	12533399	0	0
ReadyAndValidImplyGrant_A	410625352	963266	0	0
ReqAndReadyImplyGrant_A	410625352	963266	0	0
ReqImpliesValid_A	410625352	2668427	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	963266	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	963266	0	0
T1	47866	339	0	0
T2	755620	191	0	0
T3	138660	52	0	0
T7	703809	717	0	0
T8	35525	233	0	0
T9	361401	1026	0	0
T10	25841	186	0	0
T11	11716	102	0	0
T12	95243	5609	0	0
T13	254200	55	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	963266	0	0
T1	47866	339	0	0
T2	755620	191	0	0
T3	138660	52	0	0
T7	703809	717	0	0
T8	35525	233	0	0
T9	361401	1026	0	0
T10	25841	186	0	0
T11	11716	102	0	0
T12	95243	5609	0	0
T13	254200	55	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	963266	0	0
T1	47866	339	0	0
T2	755620	191	0	0
T3	138660	52	0	0
T7	703809	717	0	0
T8	35525	233	0	0
T9	361401	1026	0	0
T10	25841	186	0	0
T11	11716	102	0	0
T12	95243	5609	0	0
T13	254200	55	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	12533399	0	0
T1	47866	2370	0	0
T2	755620	64253	0	0
T3	138660	205	0	0
T7	703809	2937	0	0
T8	35525	1824	0	0
T9	361401	340316	0	0
T10	25841	1468	0	0
T11	11716	744	0	0
T12	95243	4373	0	0
T13	254200	241	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	963266	0	0
T1	47866	339	0	0
T2	755620	191	0	0
T3	138660	52	0	0
T7	703809	717	0	0
T8	35525	233	0	0
T9	361401	1026	0	0
T10	25841	186	0	0
T11	11716	102	0	0
T12	95243	5609	0	0
T13	254200	55	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	963266	0	0
T1	47866	339	0	0
T2	755620	191	0	0
T3	138660	52	0	0
T7	703809	717	0	0
T8	35525	233	0	0
T9	361401	1026	0	0
T10	25841	186	0	0
T11	11716	102	0	0
T12	95243	5609	0	0
T13	254200	55	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	2668427	0	0
T1	47866	495	0	0
T2	755620	4956	0	0
T3	138660	72	0	0
T7	703809	1001	0	0
T8	35525	348	0	0
T9	361401	32643	0	0
T10	25841	280	0	0
T11	11716	180	0	0
T12	95243	6853	0	0
T13	254200	79	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	963266	0	0
T1	47866	339	0	0
T2	755620	191	0	0
T3	138660	52	0	0
T7	703809	717	0	0
T8	35525	233	0	0
T9	361401	1026	0	0
T10	25841	186	0	0
T11	11716	102	0	0
T12	95243	5609	0	0
T13	254200	55	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	961911	0	0
GntImpliesValid_A	410625352	961911	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	961911	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	12344537	0	0
ReadyAndValidImplyGrant_A	410625352	961911	0	0
ReqAndReadyImplyGrant_A	410625352	961911	0	0
ReqImpliesValid_A	410625352	2643442	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	961911	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	961911	0	0
T1	47866	340	0	0
T2	755620	201	0	0
T3	138660	47	0	0
T7	703809	1548	0	0
T8	35525	225	0	0
T9	361401	968	0	0
T10	25841	199	0	0
T11	11716	116	0	0
T12	95243	5578	0	0
T13	254200	63	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	961911	0	0
T1	47866	340	0	0
T2	755620	201	0	0
T3	138660	47	0	0
T7	703809	1548	0	0
T8	35525	225	0	0
T9	361401	968	0	0
T10	25841	199	0	0
T11	11716	116	0	0
T12	95243	5578	0	0
T13	254200	63	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	961911	0	0
T1	47866	340	0	0
T2	755620	201	0	0
T3	138660	47	0	0
T7	703809	1548	0	0
T8	35525	225	0	0
T9	361401	968	0	0
T10	25841	199	0	0
T11	11716	116	0	0
T12	95243	5578	0	0
T13	254200	63	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	12344537	0	0
T1	47866	2374	0	0
T2	755620	67609	0	0
T3	138660	243	0	0
T7	703809	5713	0	0
T8	35525	1649	0	0
T9	361401	308836	0	0
T10	25841	1431	0	0
T11	11716	791	0	0
T12	95243	4386	0	0
T13	254200	264	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	961911	0	0
T1	47866	340	0	0
T2	755620	201	0	0
T3	138660	47	0	0
T7	703809	1548	0	0
T8	35525	225	0	0
T9	361401	968	0	0
T10	25841	199	0	0
T11	11716	116	0	0
T12	95243	5578	0	0
T13	254200	63	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	961911	0	0
T1	47866	340	0	0
T2	755620	201	0	0
T3	138660	47	0	0
T7	703809	1548	0	0
T8	35525	225	0	0
T9	361401	968	0	0
T10	25841	199	0	0
T11	11716	116	0	0
T12	95243	5578	0	0
T13	254200	63	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	2643442	0	0
T1	47866	569	0	0
T2	755620	7102	0	0
T3	138660	57	0	0
T7	703809	2989	0	0
T8	35525	316	0	0
T9	361401	35305	0	0
T10	25841	330	0	0
T11	11716	214	0	0
T12	95243	6778	0	0
T13	254200	103	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	961911	0	0
T1	47866	340	0	0
T2	755620	201	0	0
T3	138660	47	0	0
T7	703809	1548	0	0
T8	35525	225	0	0
T9	361401	968	0	0
T10	25841	199	0	0
T11	11716	116	0	0
T12	95243	5578	0	0
T13	254200	63	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	232131	0	0
GntImpliesValid_A	410625352	232131	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	232131	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	3074160	0	0
ReadyAndValidImplyGrant_A	410625352	232131	0	0
ReqAndReadyImplyGrant_A	410625352	232131	0	0
ReqImpliesValid_A	410625352	544011	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	232131	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	232131	0	0
T1	47866	99	0	0
T2	755620	40	0	0
T3	138660	18	0	0
T7	703809	1091	0	0
T8	35525	71	0	0
T9	361401	207	0	0
T10	25841	54	0	0
T11	11716	31	0	0
T12	95243	1037	0	0
T13	254200	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	232131	0	0
T1	47866	99	0	0
T2	755620	40	0	0
T3	138660	18	0	0
T7	703809	1091	0	0
T8	35525	71	0	0
T9	361401	207	0	0
T10	25841	54	0	0
T11	11716	31	0	0
T12	95243	1037	0	0
T13	254200	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	232131	0	0
T1	47866	99	0	0
T2	755620	40	0	0
T3	138660	18	0	0
T7	703809	1091	0	0
T8	35525	71	0	0
T9	361401	207	0	0
T10	25841	54	0	0
T11	11716	31	0	0
T12	95243	1037	0	0
T13	254200	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	3074160	0	0
T1	47866	692	0	0
T2	755620	13392	0	0
T3	138660	76	0	0
T7	703809	3660	0	0
T8	35525	548	0	0
T9	361401	66205	0	0
T10	25841	408	0	0
T11	11716	238	0	0
T12	95243	1019	0	0
T13	254200	22	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	232131	0	0
T1	47866	99	0	0
T2	755620	40	0	0
T3	138660	18	0	0
T7	703809	1091	0	0
T8	35525	71	0	0
T9	361401	207	0	0
T10	25841	54	0	0
T11	11716	31	0	0
T12	95243	1037	0	0
T13	254200	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	232131	0	0
T1	47866	99	0	0
T2	755620	40	0	0
T3	138660	18	0	0
T7	703809	1091	0	0
T8	35525	71	0	0
T9	361401	207	0	0
T10	25841	54	0	0
T11	11716	31	0	0
T12	95243	1037	0	0
T13	254200	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	544011	0	0
T1	47866	172	0	0
T2	755620	699	0	0
T3	138660	20	0	0
T7	703809	2621	0	0
T8	35525	91	0	0
T9	361401	1402	0	0
T10	25841	59	0	0
T11	11716	54	0	0
T12	95243	1063	0	0
T13	254200	5	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	232131	0	0
T1	47866	99	0	0
T2	755620	40	0	0
T3	138660	18	0	0
T7	703809	1091	0	0
T8	35525	71	0	0
T9	361401	207	0	0
T10	25841	54	0	0
T11	11716	31	0	0
T12	95243	1037	0	0
T13	254200	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	234347	0	0
GntImpliesValid_A	410625352	234347	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	234347	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	3107153	0	0
ReadyAndValidImplyGrant_A	410625352	234347	0	0
ReqAndReadyImplyGrant_A	410625352	234347	0	0
ReqImpliesValid_A	410625352	617512	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	234347	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	234347	0	0
T1	47866	95	0	0
T2	755620	56	0	0
T3	138660	8	0	0
T7	703809	550	0	0
T8	35525	62	0	0
T9	361401	231	0	0
T10	25841	49	0	0
T11	11716	14	0	0
T12	95243	2025	0	0
T13	254200	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	234347	0	0
T1	47866	95	0	0
T2	755620	56	0	0
T3	138660	8	0	0
T7	703809	550	0	0
T8	35525	62	0	0
T9	361401	231	0	0
T10	25841	49	0	0
T11	11716	14	0	0
T12	95243	2025	0	0
T13	254200	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	234347	0	0
T1	47866	95	0	0
T2	755620	56	0	0
T3	138660	8	0	0
T7	703809	550	0	0
T8	35525	62	0	0
T9	361401	231	0	0
T10	25841	49	0	0
T11	11716	14	0	0
T12	95243	2025	0	0
T13	254200	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	3107153	0	0
T1	47866	701	0	0
T2	755620	17131	0	0
T3	138660	34	0	0
T7	703809	1965	0	0
T8	35525	472	0	0
T9	361401	71794	0	0
T10	25841	356	0	0
T11	11716	90	0	0
T12	95243	1465	0	0
T13	254200	65	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	234347	0	0
T1	47866	95	0	0
T2	755620	56	0	0
T3	138660	8	0	0
T7	703809	550	0	0
T8	35525	62	0	0
T9	361401	231	0	0
T10	25841	49	0	0
T11	11716	14	0	0
T12	95243	2025	0	0
T13	254200	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	234347	0	0
T1	47866	95	0	0
T2	755620	56	0	0
T3	138660	8	0	0
T7	703809	550	0	0
T8	35525	62	0	0
T9	361401	231	0	0
T10	25841	49	0	0
T11	11716	14	0	0
T12	95243	2025	0	0
T13	254200	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	617512	0	0
T1	47866	124	0	0
T2	755620	1880	0	0
T3	138660	8	0	0
T7	703809	1280	0	0
T8	35525	78	0	0
T9	361401	4410	0	0
T10	25841	62	0	0
T11	11716	23	0	0
T12	95243	2593	0	0
T13	254200	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	234347	0	0
T1	47866	95	0	0
T2	755620	56	0	0
T3	138660	8	0	0
T7	703809	550	0	0
T8	35525	62	0	0
T9	361401	231	0	0
T10	25841	49	0	0
T11	11716	14	0	0
T12	95243	2025	0	0
T13	254200	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	233977	0	0
GntImpliesValid_A	410625352	233977	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	233977	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	4474106	0	0
ReadyAndValidImplyGrant_A	410625352	233977	0	0
ReqAndReadyImplyGrant_A	410625352	233977	0	0
ReqImpliesValid_A	410625352	1095729	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	233977	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	233977	0	0
T1	47866	87	0	0
T2	755620	41	0	0
T3	138660	9	0	0
T7	703809	0	0	0
T8	35525	61	0	0
T9	361401	253	0	0
T10	25841	41	0	0
T11	11716	23	0	0
T12	95243	1111	0	0
T13	254200	12	0	0
T14	0	1749	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	233977	0	0
T1	47866	87	0	0
T2	755620	41	0	0
T3	138660	9	0	0
T7	703809	0	0	0
T8	35525	61	0	0
T9	361401	253	0	0
T10	25841	41	0	0
T11	11716	23	0	0
T12	95243	1111	0	0
T13	254200	12	0	0
T14	0	1749	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	233977	0	0
T1	47866	87	0	0
T2	755620	41	0	0
T3	138660	9	0	0
T7	703809	0	0	0
T8	35525	61	0	0
T9	361401	253	0	0
T10	25841	41	0	0
T11	11716	23	0	0
T12	95243	1111	0	0
T13	254200	12	0	0
T14	0	1749	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	4474106	0	0
T1	47866	1570	0	0
T2	755620	15177	0	0
T3	138660	83	0	0
T7	703809	0	0	0
T8	35525	724	0	0
T9	361401	75910	0	0
T10	25841	357	0	0
T11	11716	457	0	0
T12	95243	5064	0	0
T13	254200	85	0	0
T14	0	4995	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	233977	0	0
T1	47866	87	0	0
T2	755620	41	0	0
T3	138660	9	0	0
T7	703809	0	0	0
T8	35525	61	0	0
T9	361401	253	0	0
T10	25841	41	0	0
T11	11716	23	0	0
T12	95243	1111	0	0
T13	254200	12	0	0
T14	0	1749	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	233977	0	0
T1	47866	87	0	0
T2	755620	41	0	0
T3	138660	9	0	0
T7	703809	0	0	0
T8	35525	61	0	0
T9	361401	253	0	0
T10	25841	41	0	0
T11	11716	23	0	0
T12	95243	1111	0	0
T13	254200	12	0	0
T14	0	1749	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	1095729	0	0
T1	47866	230	0	0
T2	755620	1454	0	0
T3	138660	9	0	0
T7	703809	0	0	0
T8	35525	100	0	0
T9	361401	3565	0	0
T10	25841	49	0	0
T11	11716	72	0	0
T12	95243	1411	0	0
T13	254200	41	0	0
T14	0	3230	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	233977	0	0
T1	47866	87	0	0
T2	755620	41	0	0
T3	138660	9	0	0
T7	703809	0	0	0
T8	35525	61	0	0
T9	361401	253	0	0
T10	25841	41	0	0
T11	11716	23	0	0
T12	95243	1111	0	0
T13	254200	12	0	0
T14	0	1749	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	225012	0	0
GntImpliesValid_A	410625352	225012	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	225012	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	4990214	0	0
ReadyAndValidImplyGrant_A	410625352	225012	0	0
ReqAndReadyImplyGrant_A	410625352	225012	0	0
ReqImpliesValid_A	410625352	955429	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	225012	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	225012	0	0
T1	47866	114	0	0
T2	755620	42	0	0
T3	138660	8	0	0
T7	703809	469	0	0
T8	35525	54	0	0
T9	361401	227	0	0
T10	25841	44	0	0
T11	11716	35	0	0
T12	95243	1645	0	0
T13	254200	3	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	225012	0	0
T1	47866	114	0	0
T2	755620	42	0	0
T3	138660	8	0	0
T7	703809	469	0	0
T8	35525	54	0	0
T9	361401	227	0	0
T10	25841	44	0	0
T11	11716	35	0	0
T12	95243	1645	0	0
T13	254200	3	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	225012	0	0
T1	47866	114	0	0
T2	755620	42	0	0
T3	138660	8	0	0
T7	703809	469	0	0
T8	35525	54	0	0
T9	361401	227	0	0
T10	25841	44	0	0
T11	11716	35	0	0
T12	95243	1645	0	0
T13	254200	3	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	4990214	0	0
T1	47866	1151	0	0
T2	755620	13302	0	0
T3	138660	148	0	0
T7	703809	3193	0	0
T8	35525	2239	0	0
T9	361401	64788	0	0
T10	25841	548	0	0
T11	11716	856	0	0
T12	95243	10752	0	0
T13	254200	41	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	225012	0	0
T1	47866	114	0	0
T2	755620	42	0	0
T3	138660	8	0	0
T7	703809	469	0	0
T8	35525	54	0	0
T9	361401	227	0	0
T10	25841	44	0	0
T11	11716	35	0	0
T12	95243	1645	0	0
T13	254200	3	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	225012	0	0
T1	47866	114	0	0
T2	755620	42	0	0
T3	138660	8	0	0
T7	703809	469	0	0
T8	35525	54	0	0
T9	361401	227	0	0
T10	25841	44	0	0
T11	11716	35	0	0
T12	95243	1645	0	0
T13	254200	3	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	955429	0	0
T1	47866	192	0	0
T2	755620	1507	0	0
T3	138660	8	0	0
T7	703809	1942	0	0
T8	35525	244	0	0
T9	361401	3130	0	0
T10	25841	74	0	0
T11	11716	166	0	0
T12	95243	4324	0	0
T13	254200	3	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	225012	0	0
T1	47866	114	0	0
T2	755620	42	0	0
T3	138660	8	0	0
T7	703809	469	0	0
T8	35525	54	0	0
T9	361401	227	0	0
T10	25841	44	0	0
T11	11716	35	0	0
T12	95243	1645	0	0
T13	254200	3	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	235852	0	0
GntImpliesValid_A	410625352	235852	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	235852	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	4315384	0	0
ReadyAndValidImplyGrant_A	410625352	235852	0	0
ReqAndReadyImplyGrant_A	410625352	235852	0	0
ReqImpliesValid_A	410625352	1218957	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	235852	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	235852	0	0
T1	47866	102	0	0
T2	755620	51	0	0
T3	138660	14	0	0
T7	703809	0	0	0
T8	35525	59	0	0
T9	361401	223	0	0
T10	25841	50	0	0
T11	11716	22	0	0
T12	95243	1475	0	0
T13	254200	9	0	0
T14	0	1987	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	235852	0	0
T1	47866	102	0	0
T2	755620	51	0	0
T3	138660	14	0	0
T7	703809	0	0	0
T8	35525	59	0	0
T9	361401	223	0	0
T10	25841	50	0	0
T11	11716	22	0	0
T12	95243	1475	0	0
T13	254200	9	0	0
T14	0	1987	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	235852	0	0
T1	47866	102	0	0
T2	755620	51	0	0
T3	138660	14	0	0
T7	703809	0	0	0
T8	35525	59	0	0
T9	361401	223	0	0
T10	25841	50	0	0
T11	11716	22	0	0
T12	95243	1475	0	0
T13	254200	9	0	0
T14	0	1987	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	4315384	0	0
T1	47866	898	0	0
T2	755620	17663	0	0
T3	138660	265	0	0
T7	703809	0	0	0
T8	35525	1308	0	0
T9	361401	108917	0	0
T10	25841	398	0	0
T11	11716	272	0	0
T12	95243	7234	0	0
T13	254200	52	0	0
T14	0	5205	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	235852	0	0
T1	47866	102	0	0
T2	755620	51	0	0
T3	138660	14	0	0
T7	703809	0	0	0
T8	35525	59	0	0
T9	361401	223	0	0
T10	25841	50	0	0
T11	11716	22	0	0
T12	95243	1475	0	0
T13	254200	9	0	0
T14	0	1987	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	235852	0	0
T1	47866	102	0	0
T2	755620	51	0	0
T3	138660	14	0	0
T7	703809	0	0	0
T8	35525	59	0	0
T9	361401	223	0	0
T10	25841	50	0	0
T11	11716	22	0	0
T12	95243	1475	0	0
T13	254200	9	0	0
T14	0	1987	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	1218957	0	0
T1	47866	130	0	0
T2	755620	290	0	0
T3	138660	47	0	0
T7	703809	0	0	0
T8	35525	122	0	0
T9	361401	10080	0	0
T10	25841	61	0	0
T11	11716	22	0	0
T12	95243	2650	0	0
T13	254200	13	0	0
T14	0	3744	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	235852	0	0
T1	47866	102	0	0
T2	755620	51	0	0
T3	138660	14	0	0
T7	703809	0	0	0
T8	35525	59	0	0
T9	361401	223	0	0
T10	25841	50	0	0
T11	11716	22	0	0
T12	95243	1475	0	0
T13	254200	9	0	0
T14	0	1987	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	227371	0	0
GntImpliesValid_A	410625352	227371	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	227371	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	5537837	0	0
ReadyAndValidImplyGrant_A	410625352	227371	0	0
ReqAndReadyImplyGrant_A	410625352	227371	0	0
ReqImpliesValid_A	410625352	1230027	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	227371	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	227371	0	0
T1	47866	93	0	0
T2	755620	41	0	0
T3	138660	10	0	0
T7	703809	0	0	0
T8	35525	47	0	0
T9	361401	258	0	0
T10	25841	28	0	0
T11	11716	20	0	0
T12	95243	997	0	0
T13	254200	9	0	0
T14	0	1716	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	227371	0	0
T1	47866	93	0	0
T2	755620	41	0	0
T3	138660	10	0	0
T7	703809	0	0	0
T8	35525	47	0	0
T9	361401	258	0	0
T10	25841	28	0	0
T11	11716	20	0	0
T12	95243	997	0	0
T13	254200	9	0	0
T14	0	1716	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	227371	0	0
T1	47866	93	0	0
T2	755620	41	0	0
T3	138660	10	0	0
T7	703809	0	0	0
T8	35525	47	0	0
T9	361401	258	0	0
T10	25841	28	0	0
T11	11716	20	0	0
T12	95243	997	0	0
T13	254200	9	0	0
T14	0	1716	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	5537837	0	0
T1	47866	1163	0	0
T2	755620	24629	0	0
T3	138660	109	0	0
T7	703809	0	0	0
T8	35525	912	0	0
T9	361401	72410	0	0
T10	25841	565	0	0
T11	11716	1147	0	0
T12	95243	4717	0	0
T13	254200	77	0	0
T14	0	5689	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	227371	0	0
T1	47866	93	0	0
T2	755620	41	0	0
T3	138660	10	0	0
T7	703809	0	0	0
T8	35525	47	0	0
T9	361401	258	0	0
T10	25841	28	0	0
T11	11716	20	0	0
T12	95243	997	0	0
T13	254200	9	0	0
T14	0	1716	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	227371	0	0
T1	47866	93	0	0
T2	755620	41	0	0
T3	138660	10	0	0
T7	703809	0	0	0
T8	35525	47	0	0
T9	361401	258	0	0
T10	25841	28	0	0
T11	11716	20	0	0
T12	95243	997	0	0
T13	254200	9	0	0
T14	0	1716	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	1230027	0	0
T1	47866	157	0	0
T2	755620	2559	0	0
T3	138660	24	0	0
T7	703809	0	0	0
T8	35525	116	0	0
T9	361401	3077	0	0
T10	25841	28	0	0
T11	11716	206	0	0
T12	95243	1249	0	0
T13	254200	17	0	0
T14	0	2925	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	227371	0	0
T1	47866	93	0	0
T2	755620	41	0	0
T3	138660	10	0	0
T7	703809	0	0	0
T8	35525	47	0	0
T9	361401	258	0	0
T10	25841	28	0	0
T11	11716	20	0	0
T12	95243	997	0	0
T13	254200	9	0	0
T14	0	1716	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	235449	0	0
GntImpliesValid_A	410625352	235449	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	235449	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	3051054	0	0
ReadyAndValidImplyGrant_A	410625352	235449	0	0
ReqAndReadyImplyGrant_A	410625352	235449	0	0
ReqImpliesValid_A	410625352	578099	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	235449	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	235449	0	0
T1	47866	99	0	0
T2	755620	60	0	0
T3	138660	4	0	0
T7	703809	0	0	0
T8	35525	47	0	0
T9	361401	228	0	0
T10	25841	39	0	0
T11	11716	23	0	0
T12	95243	1015	0	0
T13	254200	6	0	0
T14	0	2266	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	235449	0	0
T1	47866	99	0	0
T2	755620	60	0	0
T3	138660	4	0	0
T7	703809	0	0	0
T8	35525	47	0	0
T9	361401	228	0	0
T10	25841	39	0	0
T11	11716	23	0	0
T12	95243	1015	0	0
T13	254200	6	0	0
T14	0	2266	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	235449	0	0
T1	47866	99	0	0
T2	755620	60	0	0
T3	138660	4	0	0
T7	703809	0	0	0
T8	35525	47	0	0
T9	361401	228	0	0
T10	25841	39	0	0
T11	11716	23	0	0
T12	95243	1015	0	0
T13	254200	6	0	0
T14	0	2266	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	3051054	0	0
T1	47866	769	0	0
T2	755620	18322	0	0
T3	138660	24	0	0
T7	703809	1	0	0
T8	35525	340	0	0
T9	361401	71751	0	0
T10	25841	290	0	0
T11	11716	182	0	0
T12	95243	989	0	0
T13	254200	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	235449	0	0
T1	47866	99	0	0
T2	755620	60	0	0
T3	138660	4	0	0
T7	703809	0	0	0
T8	35525	47	0	0
T9	361401	228	0	0
T10	25841	39	0	0
T11	11716	23	0	0
T12	95243	1015	0	0
T13	254200	6	0	0
T14	0	2266	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	235449	0	0
T1	47866	99	0	0
T2	755620	60	0	0
T3	138660	4	0	0
T7	703809	0	0	0
T8	35525	47	0	0
T9	361401	228	0	0
T10	25841	39	0	0
T11	11716	23	0	0
T12	95243	1015	0	0
T13	254200	6	0	0
T14	0	2266	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	578099	0	0
T1	47866	124	0	0
T2	755620	915	0	0
T3	138660	4	0	0
T7	703809	0	0	0
T8	35525	47	0	0
T9	361401	1555	0	0
T10	25841	53	0	0
T11	11716	26	0	0
T12	95243	1049	0	0
T13	254200	6	0	0
T14	0	2603	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	235449	0	0
T1	47866	99	0	0
T2	755620	60	0	0
T3	138660	4	0	0
T7	703809	0	0	0
T8	35525	47	0	0
T9	361401	228	0	0
T10	25841	39	0	0
T11	11716	23	0	0
T12	95243	1015	0	0
T13	254200	6	0	0
T14	0	2266	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	228052	0	0
GntImpliesValid_A	410625352	228052	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	228052	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	3071242	0	0
ReadyAndValidImplyGrant_A	410625352	228052	0	0
ReqAndReadyImplyGrant_A	410625352	228052	0	0
ReqImpliesValid_A	410625352	554918	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	228052	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	228052	0	0
T1	47866	85	0	0
T2	755620	47	0	0
T3	138660	19	0	0
T7	703809	511	0	0
T8	35525	57	0	0
T9	361401	248	0	0
T10	25841	44	0	0
T11	11716	18	0	0
T12	95243	1521	0	0
T13	254200	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	228052	0	0
T1	47866	85	0	0
T2	755620	47	0	0
T3	138660	19	0	0
T7	703809	511	0	0
T8	35525	57	0	0
T9	361401	248	0	0
T10	25841	44	0	0
T11	11716	18	0	0
T12	95243	1521	0	0
T13	254200	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	228052	0	0
T1	47866	85	0	0
T2	755620	47	0	0
T3	138660	19	0	0
T7	703809	511	0	0
T8	35525	57	0	0
T9	361401	248	0	0
T10	25841	44	0	0
T11	11716	18	0	0
T12	95243	1521	0	0
T13	254200	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	3071242	0	0
T1	47866	633	0	0
T2	755620	15460	0	0
T3	138660	96	0	0
T7	703809	1658	0	0
T8	35525	405	0	0
T9	361401	84440	0	0
T10	25841	295	0	0
T11	11716	95	0	0
T12	95243	1282	0	0
T13	254200	22	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	228052	0	0
T1	47866	85	0	0
T2	755620	47	0	0
T3	138660	19	0	0
T7	703809	511	0	0
T8	35525	57	0	0
T9	361401	248	0	0
T10	25841	44	0	0
T11	11716	18	0	0
T12	95243	1521	0	0
T13	254200	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	228052	0	0
T1	47866	85	0	0
T2	755620	47	0	0
T3	138660	19	0	0
T7	703809	511	0	0
T8	35525	57	0	0
T9	361401	248	0	0
T10	25841	44	0	0
T11	11716	18	0	0
T12	95243	1521	0	0
T13	254200	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	554918	0	0
T1	47866	163	0	0
T2	755620	405	0	0
T3	138660	26	0	0
T7	703809	1178	0	0
T8	35525	72	0	0
T9	361401	7679	0	0
T10	25841	88	0	0
T11	11716	24	0	0
T12	95243	1768	0	0
T13	254200	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	228052	0	0
T1	47866	85	0	0
T2	755620	47	0	0
T3	138660	19	0	0
T7	703809	511	0	0
T8	35525	57	0	0
T9	361401	248	0	0
T10	25841	44	0	0
T11	11716	18	0	0
T12	95243	1521	0	0
T13	254200	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	240833	0	0
GntImpliesValid_A	410625352	240833	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	240833	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	3147880	0	0
ReadyAndValidImplyGrant_A	410625352	240833	0	0
ReqAndReadyImplyGrant_A	410625352	240833	0	0
ReqImpliesValid_A	410625352	592266	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	240833	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	240833	0	0
T1	47866	81	0	0
T2	755620	64	0	0
T3	138660	8	0	0
T7	703809	0	0	0
T8	35525	64	0	0
T9	361401	249	0	0
T10	25841	42	0	0
T11	11716	21	0	0
T12	95243	2002	0	0
T13	254200	9	0	0
T14	0	1114	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	240833	0	0
T1	47866	81	0	0
T2	755620	64	0	0
T3	138660	8	0	0
T7	703809	0	0	0
T8	35525	64	0	0
T9	361401	249	0	0
T10	25841	42	0	0
T11	11716	21	0	0
T12	95243	2002	0	0
T13	254200	9	0	0
T14	0	1114	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	240833	0	0
T1	47866	81	0	0
T2	755620	64	0	0
T3	138660	8	0	0
T7	703809	0	0	0
T8	35525	64	0	0
T9	361401	249	0	0
T10	25841	42	0	0
T11	11716	21	0	0
T12	95243	2002	0	0
T13	254200	9	0	0
T14	0	1114	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	3147880	0	0
T1	47866	544	0	0
T2	755620	21392	0	0
T3	138660	42	0	0
T7	703809	1	0	0
T8	35525	500	0	0
T9	361401	78770	0	0
T10	25841	278	0	0
T11	11716	155	0	0
T12	95243	1571	0	0
T13	254200	47	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	240833	0	0
T1	47866	81	0	0
T2	755620	64	0	0
T3	138660	8	0	0
T7	703809	0	0	0
T8	35525	64	0	0
T9	361401	249	0	0
T10	25841	42	0	0
T11	11716	21	0	0
T12	95243	2002	0	0
T13	254200	9	0	0
T14	0	1114	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	240833	0	0
T1	47866	81	0	0
T2	755620	64	0	0
T3	138660	8	0	0
T7	703809	0	0	0
T8	35525	64	0	0
T9	361401	249	0	0
T10	25841	42	0	0
T11	11716	21	0	0
T12	95243	2002	0	0
T13	254200	9	0	0
T14	0	1114	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	592266	0	0
T1	47866	81	0	0
T2	755620	2792	0	0
T3	138660	15	0	0
T7	703809	0	0	0
T8	35525	84	0	0
T9	361401	4641	0	0
T10	25841	42	0	0
T11	11716	25	0	0
T12	95243	2441	0	0
T13	254200	9	0	0
T14	0	1133	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	240833	0	0
T1	47866	81	0	0
T2	755620	64	0	0
T3	138660	8	0	0
T7	703809	0	0	0
T8	35525	64	0	0
T9	361401	249	0	0
T10	25841	42	0	0
T11	11716	21	0	0
T12	95243	2002	0	0
T13	254200	9	0	0
T14	0	1114	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	237619	0	0
GntImpliesValid_A	410625352	237619	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	237619	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	3066339	0	0
ReadyAndValidImplyGrant_A	410625352	237619	0	0
ReqAndReadyImplyGrant_A	410625352	237619	0	0
ReqImpliesValid_A	410625352	614267	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	237619	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	237619	0	0
T1	47866	88	0	0
T2	755620	45	0	0
T3	138660	5	0	0
T7	703809	517	0	0
T8	35525	68	0	0
T9	361401	263	0	0
T10	25841	45	0	0
T11	11716	31	0	0
T12	95243	1057	0	0
T13	254200	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	237619	0	0
T1	47866	88	0	0
T2	755620	45	0	0
T3	138660	5	0	0
T7	703809	517	0	0
T8	35525	68	0	0
T9	361401	263	0	0
T10	25841	45	0	0
T11	11716	31	0	0
T12	95243	1057	0	0
T13	254200	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	237619	0	0
T1	47866	88	0	0
T2	755620	45	0	0
T3	138660	5	0	0
T7	703809	517	0	0
T8	35525	68	0	0
T9	361401	263	0	0
T10	25841	45	0	0
T11	11716	31	0	0
T12	95243	1057	0	0
T13	254200	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	3066339	0	0
T1	47866	618	0	0
T2	755620	13999	0	0
T3	138660	35	0	0
T7	703809	1623	0	0
T8	35525	486	0	0
T9	361401	79013	0	0
T10	25841	330	0	0
T11	11716	229	0	0
T12	95243	1030	0	0
T13	254200	39	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	237619	0	0
T1	47866	88	0	0
T2	755620	45	0	0
T3	138660	5	0	0
T7	703809	517	0	0
T8	35525	68	0	0
T9	361401	263	0	0
T10	25841	45	0	0
T11	11716	31	0	0
T12	95243	1057	0	0
T13	254200	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	237619	0	0
T1	47866	88	0	0
T2	755620	45	0	0
T3	138660	5	0	0
T7	703809	517	0	0
T8	35525	68	0	0
T9	361401	263	0	0
T10	25841	45	0	0
T11	11716	31	0	0
T12	95243	1057	0	0
T13	254200	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	614267	0	0
T1	47866	95	0	0
T2	755620	933	0	0
T3	138660	10	0	0
T7	703809	1221	0	0
T8	35525	72	0	0
T9	361401	4930	0	0
T10	25841	60	0	0
T11	11716	61	0	0
T12	95243	1092	0	0
T13	254200	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	237619	0	0
T1	47866	88	0	0
T2	755620	45	0	0
T3	138660	5	0	0
T7	703809	517	0	0
T8	35525	68	0	0
T9	361401	263	0	0
T10	25841	45	0	0
T11	11716	31	0	0
T12	95243	1057	0	0
T13	254200	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	228842	0	0
GntImpliesValid_A	410625352	228842	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	228842	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	2996711	0	0
ReadyAndValidImplyGrant_A	410625352	228842	0	0
ReqAndReadyImplyGrant_A	410625352	228842	0	0
ReqImpliesValid_A	410625352	546738	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	228842	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	228842	0	0
T1	47866	97	0	0
T2	755620	38	0	0
T3	138660	10	0	0
T7	703809	0	0	0
T8	35525	58	0	0
T9	361401	185	0	0
T10	25841	52	0	0
T11	11716	32	0	0
T12	95243	976	0	0
T13	254200	9	0	0
T14	0	2616	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	228842	0	0
T1	47866	97	0	0
T2	755620	38	0	0
T3	138660	10	0	0
T7	703809	0	0	0
T8	35525	58	0	0
T9	361401	185	0	0
T10	25841	52	0	0
T11	11716	32	0	0
T12	95243	976	0	0
T13	254200	9	0	0
T14	0	2616	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	228842	0	0
T1	47866	97	0	0
T2	755620	38	0	0
T3	138660	10	0	0
T7	703809	0	0	0
T8	35525	58	0	0
T9	361401	185	0	0
T10	25841	52	0	0
T11	11716	32	0	0
T12	95243	976	0	0
T13	254200	9	0	0
T14	0	2616	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	2996711	0	0
T1	47866	737	0	0
T2	755620	14530	0	0
T3	138660	46	0	0
T7	703809	1	0	0
T8	35525	431	0	0
T9	361401	58692	0	0
T10	25841	419	0	0
T11	11716	194	0	0
T12	95243	953	0	0
T13	254200	36	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	228842	0	0
T1	47866	97	0	0
T2	755620	38	0	0
T3	138660	10	0	0
T7	703809	0	0	0
T8	35525	58	0	0
T9	361401	185	0	0
T10	25841	52	0	0
T11	11716	32	0	0
T12	95243	976	0	0
T13	254200	9	0	0
T14	0	2616	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	228842	0	0
T1	47866	97	0	0
T2	755620	38	0	0
T3	138660	10	0	0
T7	703809	0	0	0
T8	35525	58	0	0
T9	361401	185	0	0
T10	25841	52	0	0
T11	11716	32	0	0
T12	95243	976	0	0
T13	254200	9	0	0
T14	0	2616	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	546738	0	0
T1	47866	107	0	0
T2	755620	117	0	0
T3	138660	10	0	0
T7	703809	0	0	0
T8	35525	59	0	0
T9	361401	1703	0	0
T10	25841	54	0	0
T11	11716	90	0	0
T12	95243	1007	0	0
T13	254200	9	0	0
T14	0	3251	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	228842	0	0
T1	47866	97	0	0
T2	755620	38	0	0
T3	138660	10	0	0
T7	703809	0	0	0
T8	35525	58	0	0
T9	361401	185	0	0
T10	25841	52	0	0
T11	11716	32	0	0
T12	95243	976	0	0
T13	254200	9	0	0
T14	0	2616	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	226821	0	0
GntImpliesValid_A	410625352	226821	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	226821	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	3097264	0	0
ReadyAndValidImplyGrant_A	410625352	226821	0	0
ReqAndReadyImplyGrant_A	410625352	226821	0	0
ReqImpliesValid_A	410625352	568722	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	226821	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	226821	0	0
T1	47866	97	0	0
T2	755620	51	0	0
T3	138660	14	0	0
T7	703809	463	0	0
T8	35525	48	0	0
T9	361401	219	0	0
T10	25841	34	0	0
T11	11716	21	0	0
T12	95243	1354	0	0
T13	254200	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	226821	0	0
T1	47866	97	0	0
T2	755620	51	0	0
T3	138660	14	0	0
T7	703809	463	0	0
T8	35525	48	0	0
T9	361401	219	0	0
T10	25841	34	0	0
T11	11716	21	0	0
T12	95243	1354	0	0
T13	254200	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	226821	0	0
T1	47866	97	0	0
T2	755620	51	0	0
T3	138660	14	0	0
T7	703809	463	0	0
T8	35525	48	0	0
T9	361401	219	0	0
T10	25841	34	0	0
T11	11716	21	0	0
T12	95243	1354	0	0
T13	254200	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	3097264	0	0
T1	47866	805	0	0
T2	755620	12471	0	0
T3	138660	47	0	0
T7	703809	1462	0	0
T8	35525	305	0	0
T9	361401	71763	0	0
T10	25841	227	0	0
T11	11716	134	0	0
T12	95243	1260	0	0
T13	254200	29	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	226821	0	0
T1	47866	97	0	0
T2	755620	51	0	0
T3	138660	14	0	0
T7	703809	463	0	0
T8	35525	48	0	0
T9	361401	219	0	0
T10	25841	34	0	0
T11	11716	21	0	0
T12	95243	1354	0	0
T13	254200	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	226821	0	0
T1	47866	97	0	0
T2	755620	51	0	0
T3	138660	14	0	0
T7	703809	463	0	0
T8	35525	48	0	0
T9	361401	219	0	0
T10	25841	34	0	0
T11	11716	21	0	0
T12	95243	1354	0	0
T13	254200	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	568722	0	0
T1	47866	121	0	0
T2	755620	3187	0	0
T3	138660	17	0	0
T7	703809	1136	0	0
T8	35525	50	0	0
T9	361401	3631	0	0
T10	25841	34	0	0
T11	11716	34	0	0
T12	95243	1455	0	0
T13	254200	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	226821	0	0
T1	47866	97	0	0
T2	755620	51	0	0
T3	138660	14	0	0
T7	703809	463	0	0
T8	35525	48	0	0
T9	361401	219	0	0
T10	25841	34	0	0
T11	11716	21	0	0
T12	95243	1354	0	0
T13	254200	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	237692	0	0
GntImpliesValid_A	410625352	237692	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	237692	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	3120240	0	0
ReadyAndValidImplyGrant_A	410625352	237692	0	0
ReqAndReadyImplyGrant_A	410625352	237692	0	0
ReqImpliesValid_A	410625352	646259	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	237692	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	237692	0	0
T1	47866	83	0	0
T2	755620	40	0	0
T3	138660	13	0	0
T7	703809	508	0	0
T8	35525	60	0	0
T9	361401	212	0	0
T10	25841	43	0	0
T11	11716	27	0	0
T12	95243	2178	0	0
T13	254200	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	237692	0	0
T1	47866	83	0	0
T2	755620	40	0	0
T3	138660	13	0	0
T7	703809	508	0	0
T8	35525	60	0	0
T9	361401	212	0	0
T10	25841	43	0	0
T11	11716	27	0	0
T12	95243	2178	0	0
T13	254200	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	237692	0	0
T1	47866	83	0	0
T2	755620	40	0	0
T3	138660	13	0	0
T7	703809	508	0	0
T8	35525	60	0	0
T9	361401	212	0	0
T10	25841	43	0	0
T11	11716	27	0	0
T12	95243	2178	0	0
T13	254200	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	3120240	0	0
T1	47866	557	0	0
T2	755620	15182	0	0
T3	138660	52	0	0
T7	703809	1710	0	0
T8	35525	450	0	0
T9	361401	69199	0	0
T10	25841	346	0	0
T11	11716	202	0	0
T12	95243	1450	0	0
T13	254200	63	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	237692	0	0
T1	47866	83	0	0
T2	755620	40	0	0
T3	138660	13	0	0
T7	703809	508	0	0
T8	35525	60	0	0
T9	361401	212	0	0
T10	25841	43	0	0
T11	11716	27	0	0
T12	95243	2178	0	0
T13	254200	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	237692	0	0
T1	47866	83	0	0
T2	755620	40	0	0
T3	138660	13	0	0
T7	703809	508	0	0
T8	35525	60	0	0
T9	361401	212	0	0
T10	25841	43	0	0
T11	11716	27	0	0
T12	95243	2178	0	0
T13	254200	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	646259	0	0
T1	47866	118	0	0
T2	755620	1712	0	0
T3	138660	13	0	0
T7	703809	1174	0	0
T8	35525	82	0	0
T9	361401	3116	0	0
T10	25841	64	0	0
T11	11716	27	0	0
T12	95243	2914	0	0
T13	254200	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	237692	0	0
T1	47866	83	0	0
T2	755620	40	0	0
T3	138660	13	0	0
T7	703809	508	0	0
T8	35525	60	0	0
T9	361401	212	0	0
T10	25841	43	0	0
T11	11716	27	0	0
T12	95243	2178	0	0
T13	254200	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	238109	0	0
GntImpliesValid_A	410625352	238109	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	238109	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	3078358	0	0
ReadyAndValidImplyGrant_A	410625352	238109	0	0
ReqAndReadyImplyGrant_A	410625352	238109	0	0
ReqImpliesValid_A	410625352	589114	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	238109	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	238109	0	0
T1	47866	90	0	0
T2	755620	45	0	0
T3	138660	18	0	0
T7	703809	541	0	0
T8	35525	70	0	0
T9	361401	237	0	0
T10	25841	54	0	0
T11	11716	22	0	0
T12	95243	1099	0	0
T13	254200	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	238109	0	0
T1	47866	90	0	0
T2	755620	45	0	0
T3	138660	18	0	0
T7	703809	541	0	0
T8	35525	70	0	0
T9	361401	237	0	0
T10	25841	54	0	0
T11	11716	22	0	0
T12	95243	1099	0	0
T13	254200	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	238109	0	0
T1	47866	90	0	0
T2	755620	45	0	0
T3	138660	18	0	0
T7	703809	541	0	0
T8	35525	70	0	0
T9	361401	237	0	0
T10	25841	54	0	0
T11	11716	22	0	0
T12	95243	1099	0	0
T13	254200	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	3078358	0	0
T1	47866	670	0	0
T2	755620	14125	0	0
T3	138660	67	0	0
T7	703809	1825	0	0
T8	35525	611	0	0
T9	361401	74972	0	0
T10	25841	416	0	0
T11	11716	169	0	0
T12	95243	1073	0	0
T13	254200	29	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	238109	0	0
T1	47866	90	0	0
T2	755620	45	0	0
T3	138660	18	0	0
T7	703809	541	0	0
T8	35525	70	0	0
T9	361401	237	0	0
T10	25841	54	0	0
T11	11716	22	0	0
T12	95243	1099	0	0
T13	254200	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	238109	0	0
T1	47866	90	0	0
T2	755620	45	0	0
T3	138660	18	0	0
T7	703809	541	0	0
T8	35525	70	0	0
T9	361401	237	0	0
T10	25841	54	0	0
T11	11716	22	0	0
T12	95243	1099	0	0
T13	254200	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	589114	0	0
T1	47866	139	0	0
T2	755620	237	0	0
T3	138660	21	0	0
T7	703809	1280	0	0
T8	35525	79	0	0
T9	361401	3163	0	0
T10	25841	78	0	0
T11	11716	22	0	0
T12	95243	1133	0	0
T13	254200	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	238109	0	0
T1	47866	90	0	0
T2	755620	45	0	0
T3	138660	18	0	0
T7	703809	541	0	0
T8	35525	70	0	0
T9	361401	237	0	0
T10	25841	54	0	0
T11	11716	22	0	0
T12	95243	1099	0	0
T13	254200	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	263731	0	0
GntImpliesValid_A	410625352	263731	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	263731	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	3216709	0	0
ReadyAndValidImplyGrant_A	410625352	263731	0	0
ReqAndReadyImplyGrant_A	410625352	263731	0	0
ReqImpliesValid_A	410625352	657360	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	263731	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	263731	0	0
T1	47866	174	0	0
T2	755620	40	0	0
T3	138660	16	0	0
T7	703809	0	0	0
T8	35525	99	0	0
T9	361401	228	0	0
T10	25841	76	0	0
T11	11716	30	0	0
T12	95243	1533	0	0
T13	254200	10	0	0
T14	0	2302	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	263731	0	0
T1	47866	174	0	0
T2	755620	40	0	0
T3	138660	16	0	0
T7	703809	0	0	0
T8	35525	99	0	0
T9	361401	228	0	0
T10	25841	76	0	0
T11	11716	30	0	0
T12	95243	1533	0	0
T13	254200	10	0	0
T14	0	2302	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	263731	0	0
T1	47866	174	0	0
T2	755620	40	0	0
T3	138660	16	0	0
T7	703809	0	0	0
T8	35525	99	0	0
T9	361401	228	0	0
T10	25841	76	0	0
T11	11716	30	0	0
T12	95243	1533	0	0
T13	254200	10	0	0
T14	0	2302	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	3216709	0	0
T1	47866	1410	0	0
T2	755620	11255	0	0
T3	138660	72	0	0
T7	703809	1	0	0
T8	35525	699	0	0
T9	361401	73272	0	0
T10	25841	588	0	0
T11	11716	212	0	0
T12	95243	1310	0	0
T13	254200	44	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	263731	0	0
T1	47866	174	0	0
T2	755620	40	0	0
T3	138660	16	0	0
T7	703809	0	0	0
T8	35525	99	0	0
T9	361401	228	0	0
T10	25841	76	0	0
T11	11716	30	0	0
T12	95243	1533	0	0
T13	254200	10	0	0
T14	0	2302	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	263731	0	0
T1	47866	174	0	0
T2	755620	40	0	0
T3	138660	16	0	0
T7	703809	0	0	0
T8	35525	99	0	0
T9	361401	228	0	0
T10	25841	76	0	0
T11	11716	30	0	0
T12	95243	1533	0	0
T13	254200	10	0	0
T14	0	2302	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	657360	0	0
T1	47866	250	0	0
T2	755620	1413	0	0
T3	138660	16	0	0
T7	703809	0	0	0
T8	35525	131	0	0
T9	361401	3762	0	0
T10	25841	92	0	0
T11	11716	41	0	0
T12	95243	1763	0	0
T13	254200	10	0	0
T14	0	2904	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	263731	0	0
T1	47866	174	0	0
T2	755620	40	0	0
T3	138660	16	0	0
T7	703809	0	0	0
T8	35525	99	0	0
T9	361401	228	0	0
T10	25841	76	0	0
T11	11716	30	0	0
T12	95243	1533	0	0
T13	254200	10	0	0
T14	0	2302	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	246604	0	0
GntImpliesValid_A	410625352	246604	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	246604	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	3118244	0	0
ReadyAndValidImplyGrant_A	410625352	246604	0	0
ReqAndReadyImplyGrant_A	410625352	246604	0	0
ReqImpliesValid_A	410625352	624142	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	246604	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	246604	0	0
T1	47866	89	0	0
T2	755620	43	0	0
T3	138660	15	0	0
T7	703809	0	0	0
T8	35525	65	0	0
T9	361401	222	0	0
T10	25841	47	0	0
T11	11716	23	0	0
T12	95243	1065	0	0
T13	254200	13	0	0
T14	0	2767	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	246604	0	0
T1	47866	89	0	0
T2	755620	43	0	0
T3	138660	15	0	0
T7	703809	0	0	0
T8	35525	65	0	0
T9	361401	222	0	0
T10	25841	47	0	0
T11	11716	23	0	0
T12	95243	1065	0	0
T13	254200	13	0	0
T14	0	2767	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	246604	0	0
T1	47866	89	0	0
T2	755620	43	0	0
T3	138660	15	0	0
T7	703809	0	0	0
T8	35525	65	0	0
T9	361401	222	0	0
T10	25841	47	0	0
T11	11716	23	0	0
T12	95243	1065	0	0
T13	254200	13	0	0
T14	0	2767	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	3118244	0	0
T1	47866	633	0	0
T2	755620	13984	0	0
T3	138660	48	0	0
T7	703809	1	0	0
T8	35525	482	0	0
T9	361401	75072	0	0
T10	25841	347	0	0
T11	11716	193	0	0
T12	95243	1037	0	0
T13	254200	59	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	246604	0	0
T1	47866	89	0	0
T2	755620	43	0	0
T3	138660	15	0	0
T7	703809	0	0	0
T8	35525	65	0	0
T9	361401	222	0	0
T10	25841	47	0	0
T11	11716	23	0	0
T12	95243	1065	0	0
T13	254200	13	0	0
T14	0	2767	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	246604	0	0
T1	47866	89	0	0
T2	755620	43	0	0
T3	138660	15	0	0
T7	703809	0	0	0
T8	35525	65	0	0
T9	361401	222	0	0
T10	25841	47	0	0
T11	11716	23	0	0
T12	95243	1065	0	0
T13	254200	13	0	0
T14	0	2767	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	624142	0	0
T1	47866	98	0	0
T2	755620	830	0	0
T3	138660	16	0	0
T7	703809	0	0	0
T8	35525	82	0	0
T9	361401	3141	0	0
T10	25841	63	0	0
T11	11716	37	0	0
T12	95243	1101	0	0
T13	254200	13	0	0
T14	0	3645	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	246604	0	0
T1	47866	89	0	0
T2	755620	43	0	0
T3	138660	15	0	0
T7	703809	0	0	0
T8	35525	65	0	0
T9	361401	222	0	0
T10	25841	47	0	0
T11	11716	23	0	0
T12	95243	1065	0	0
T13	254200	13	0	0
T14	0	2767	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	236930	0	0
GntImpliesValid_A	410625352	236930	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	236930	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	3099394	0	0
ReadyAndValidImplyGrant_A	410625352	236930	0	0
ReqAndReadyImplyGrant_A	410625352	236930	0	0
ReqImpliesValid_A	410625352	628715	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	236930	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	236930	0	0
T1	47866	101	0	0
T2	755620	46	0	0
T3	138660	14	0	0
T7	703809	509	0	0
T8	35525	69	0	0
T9	361401	230	0	0
T10	25841	55	0	0
T11	11716	29	0	0
T12	95243	2847	0	0
T13	254200	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	236930	0	0
T1	47866	101	0	0
T2	755620	46	0	0
T3	138660	14	0	0
T7	703809	509	0	0
T8	35525	69	0	0
T9	361401	230	0	0
T10	25841	55	0	0
T11	11716	29	0	0
T12	95243	2847	0	0
T13	254200	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	236930	0	0
T1	47866	101	0	0
T2	755620	46	0	0
T3	138660	14	0	0
T7	703809	509	0	0
T8	35525	69	0	0
T9	361401	230	0	0
T10	25841	55	0	0
T11	11716	29	0	0
T12	95243	2847	0	0
T13	254200	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	3099394	0	0
T1	47866	788	0	0
T2	755620	14562	0	0
T3	138660	52	0	0
T7	703809	1740	0	0
T8	35525	517	0	0
T9	361401	75989	0	0
T10	25841	400	0	0
T11	11716	231	0	0
T12	95243	1954	0	0
T13	254200	31	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	236930	0	0
T1	47866	101	0	0
T2	755620	46	0	0
T3	138660	14	0	0
T7	703809	509	0	0
T8	35525	69	0	0
T9	361401	230	0	0
T10	25841	55	0	0
T11	11716	29	0	0
T12	95243	2847	0	0
T13	254200	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	236930	0	0
T1	47866	101	0	0
T2	755620	46	0	0
T3	138660	14	0	0
T7	703809	509	0	0
T8	35525	69	0	0
T9	361401	230	0	0
T10	25841	55	0	0
T11	11716	29	0	0
T12	95243	2847	0	0
T13	254200	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	628715	0	0
T1	47866	115	0	0
T2	755620	251	0	0
T3	138660	19	0	0
T7	703809	1221	0	0
T8	35525	81	0	0
T9	361401	5822	0	0
T10	25841	79	0	0
T11	11716	54	0	0
T12	95243	3747	0	0
T13	254200	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	236930	0	0
T1	47866	101	0	0
T2	755620	46	0	0
T3	138660	14	0	0
T7	703809	509	0	0
T8	35525	69	0	0
T9	361401	230	0	0
T10	25841	55	0	0
T11	11716	29	0	0
T12	95243	2847	0	0
T13	254200	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	230182	0	0
GntImpliesValid_A	410625352	230182	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	230182	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	3063255	0	0
ReadyAndValidImplyGrant_A	410625352	230182	0	0
ReqAndReadyImplyGrant_A	410625352	230182	0	0
ReqImpliesValid_A	410625352	580193	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	230182	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	230182	0	0
T1	47866	84	0	0
T2	755620	47	0	0
T3	138660	11	0	0
T7	703809	487	0	0
T8	35525	56	0	0
T9	361401	242	0	0
T10	25841	51	0	0
T11	11716	20	0	0
T12	95243	2684	0	0
T13	254200	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	230182	0	0
T1	47866	84	0	0
T2	755620	47	0	0
T3	138660	11	0	0
T7	703809	487	0	0
T8	35525	56	0	0
T9	361401	242	0	0
T10	25841	51	0	0
T11	11716	20	0	0
T12	95243	2684	0	0
T13	254200	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	230182	0	0
T1	47866	84	0	0
T2	755620	47	0	0
T3	138660	11	0	0
T7	703809	487	0	0
T8	35525	56	0	0
T9	361401	242	0	0
T10	25841	51	0	0
T11	11716	20	0	0
T12	95243	2684	0	0
T13	254200	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	3063255	0	0
T1	47866	706	0	0
T2	755620	14676	0	0
T3	138660	48	0	0
T7	703809	1632	0	0
T8	35525	408	0	0
T9	361401	79524	0	0
T10	25841	396	0	0
T11	11716	138	0	0
T12	95243	1808	0	0
T13	254200	47	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	230182	0	0
T1	47866	84	0	0
T2	755620	47	0	0
T3	138660	11	0	0
T7	703809	487	0	0
T8	35525	56	0	0
T9	361401	242	0	0
T10	25841	51	0	0
T11	11716	20	0	0
T12	95243	2684	0	0
T13	254200	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	230182	0	0
T1	47866	84	0	0
T2	755620	47	0	0
T3	138660	11	0	0
T7	703809	487	0	0
T8	35525	56	0	0
T9	361401	242	0	0
T10	25841	51	0	0
T11	11716	20	0	0
T12	95243	2684	0	0
T13	254200	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	580193	0	0
T1	47866	131	0	0
T2	755620	451	0	0
T3	138660	11	0	0
T7	703809	1204	0	0
T8	35525	56	0	0
T9	361401	3224	0	0
T10	25841	76	0	0
T11	11716	28	0	0
T12	95243	3568	0	0
T13	254200	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	230182	0	0
T1	47866	84	0	0
T2	755620	47	0	0
T3	138660	11	0	0
T7	703809	487	0	0
T8	35525	56	0	0
T9	361401	242	0	0
T10	25841	51	0	0
T11	11716	20	0	0
T12	95243	2684	0	0
T13	254200	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	235494	0	0
GntImpliesValid_A	410625352	235494	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	235494	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	3024782	0	0
ReadyAndValidImplyGrant_A	410625352	235494	0	0
ReqAndReadyImplyGrant_A	410625352	235494	0	0
ReqImpliesValid_A	410625352	547915	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	235494	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	235494	0	0
T1	47866	102	0	0
T2	755620	44	0	0
T3	138660	17	0	0
T7	703809	569	0	0
T8	35525	45	0	0
T9	361401	237	0	0
T10	25841	38	0	0
T11	11716	12	0	0
T12	95243	1098	0	0
T13	254200	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	235494	0	0
T1	47866	102	0	0
T2	755620	44	0	0
T3	138660	17	0	0
T7	703809	569	0	0
T8	35525	45	0	0
T9	361401	237	0	0
T10	25841	38	0	0
T11	11716	12	0	0
T12	95243	1098	0	0
T13	254200	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	235494	0	0
T1	47866	102	0	0
T2	755620	44	0	0
T3	138660	17	0	0
T7	703809	569	0	0
T8	35525	45	0	0
T9	361401	237	0	0
T10	25841	38	0	0
T11	11716	12	0	0
T12	95243	1098	0	0
T13	254200	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	3024782	0	0
T1	47866	740	0	0
T2	755620	13687	0	0
T3	138660	62	0	0
T7	703809	1964	0	0
T8	35525	359	0	0
T9	361401	82106	0	0
T10	25841	280	0	0
T11	11716	79	0	0
T12	95243	1066	0	0
T13	254200	50	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	235494	0	0
T1	47866	102	0	0
T2	755620	44	0	0
T3	138660	17	0	0
T7	703809	569	0	0
T8	35525	45	0	0
T9	361401	237	0	0
T10	25841	38	0	0
T11	11716	12	0	0
T12	95243	1098	0	0
T13	254200	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	235494	0	0
T1	47866	102	0	0
T2	755620	44	0	0
T3	138660	17	0	0
T7	703809	569	0	0
T8	35525	45	0	0
T9	361401	237	0	0
T10	25841	38	0	0
T11	11716	12	0	0
T12	95243	1098	0	0
T13	254200	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	547915	0	0
T1	47866	170	0	0
T2	755620	1406	0	0
T3	138660	21	0	0
T7	703809	1277	0	0
T8	35525	58	0	0
T9	361401	3272	0	0
T10	25841	41	0	0
T11	11716	12	0	0
T12	95243	1138	0	0
T13	254200	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	235494	0	0
T1	47866	102	0	0
T2	755620	44	0	0
T3	138660	17	0	0
T7	703809	569	0	0
T8	35525	45	0	0
T9	361401	237	0	0
T10	25841	38	0	0
T11	11716	12	0	0
T12	95243	1098	0	0
T13	254200	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	240657	0	0
GntImpliesValid_A	410625352	240657	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	240657	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	3115549	0	0
ReadyAndValidImplyGrant_A	410625352	240657	0	0
ReqAndReadyImplyGrant_A	410625352	240657	0	0
ReqImpliesValid_A	410625352	653235	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	0	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	240657	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	240657	0	0
T1	47866	97	0	0
T2	755620	60	0	0
T3	138660	13	0	0
T7	703809	0	0	0
T8	35525	53	0	0
T9	361401	210	0	0
T10	25841	47	0	0
T11	11716	30	0	0
T12	95243	1567	0	0
T13	254200	6	0	0
T14	0	1121	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	240657	0	0
T1	47866	97	0	0
T2	755620	60	0	0
T3	138660	13	0	0
T7	703809	0	0	0
T8	35525	53	0	0
T9	361401	210	0	0
T10	25841	47	0	0
T11	11716	30	0	0
T12	95243	1567	0	0
T13	254200	6	0	0
T14	0	1121	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	240657	0	0
T1	47866	97	0	0
T2	755620	60	0	0
T3	138660	13	0	0
T7	703809	0	0	0
T8	35525	53	0	0
T9	361401	210	0	0
T10	25841	47	0	0
T11	11716	30	0	0
T12	95243	1567	0	0
T13	254200	6	0	0
T14	0	1121	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	3115549	0	0
T1	47866	706	0	0
T2	755620	16689	0	0
T3	138660	74	0	0
T7	703809	1	0	0
T8	35525	317	0	0
T9	361401	74267	0	0
T10	25841	358	0	0
T11	11716	299	0	0
T12	95243	1312	0	0
T13	254200	40	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	240657	0	0
T1	47866	97	0	0
T2	755620	60	0	0
T3	138660	13	0	0
T7	703809	0	0	0
T8	35525	53	0	0
T9	361401	210	0	0
T10	25841	47	0	0
T11	11716	30	0	0
T12	95243	1567	0	0
T13	254200	6	0	0
T14	0	1121	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	240657	0	0
T1	47866	97	0	0
T2	755620	60	0	0
T3	138660	13	0	0
T7	703809	0	0	0
T8	35525	53	0	0
T9	361401	210	0	0
T10	25841	47	0	0
T11	11716	30	0	0
T12	95243	1567	0	0
T13	254200	6	0	0
T14	0	1121	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	653235	0	0
T1	47866	136	0	0
T2	755620	1018	0	0
T3	138660	13	0	0
T7	703809	0	0	0
T8	35525	67	0	0
T9	361401	1253	0	0
T10	25841	57	0	0
T11	11716	42	0	0
T12	95243	1830	0	0
T13	254200	6	0	0
T14	0	1156	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	240657	0	0
T1	47866	97	0	0
T2	755620	60	0	0
T3	138660	13	0	0
T7	703809	0	0	0
T8	35525	53	0	0
T9	361401	210	0	0
T10	25841	47	0	0
T11	11716	30	0	0
T12	95243	1567	0	0
T13	254200	6	0	0
T14	0	1121	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	944464	0	0
GntImpliesValid_A	410625352	944464	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	944464	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	11896414	0	0
ReadyAndValidImplyGrant_A	410625352	944464	0	0
ReqAndReadyImplyGrant_A	410625352	944464	0	0
ReqImpliesValid_A	410625352	2369625	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	23889	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	944464	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	944464	0	0
T1	47866	334	0	0
T2	755620	208	0	0
T3	138660	60	0	0
T7	703809	1390	0	0
T8	35525	221	0	0
T9	361401	996	0	0
T10	25841	163	0	0
T11	11716	101	0	0
T12	95243	6400	0	0
T13	254200	50	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	944464	0	0
T1	47866	334	0	0
T2	755620	208	0	0
T3	138660	60	0	0
T7	703809	1390	0	0
T8	35525	221	0	0
T9	361401	996	0	0
T10	25841	163	0	0
T11	11716	101	0	0
T12	95243	6400	0	0
T13	254200	50	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	944464	0	0
T1	47866	334	0	0
T2	755620	208	0	0
T3	138660	60	0	0
T7	703809	1390	0	0
T8	35525	221	0	0
T9	361401	996	0	0
T10	25841	163	0	0
T11	11716	101	0	0
T12	95243	6400	0	0
T13	254200	50	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	11896414	0	0
T1	47866	2271	0	0
T2	755620	60028	0	0
T3	138660	203	0	0
T7	703809	3917	0	0
T8	35525	1440	0	0
T9	361401	325272	0	0
T10	25841	996	0	0
T11	11716	659	0	0
T12	95243	8	0	0
T13	254200	149	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	944464	0	0
T1	47866	334	0	0
T2	755620	208	0	0
T3	138660	60	0	0
T7	703809	1390	0	0
T8	35525	221	0	0
T9	361401	996	0	0
T10	25841	163	0	0
T11	11716	101	0	0
T12	95243	6400	0	0
T13	254200	50	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	944464	0	0
T1	47866	334	0	0
T2	755620	208	0	0
T3	138660	60	0	0
T7	703809	1390	0	0
T8	35525	221	0	0
T9	361401	996	0	0
T10	25841	163	0	0
T11	11716	101	0	0
T12	95243	6400	0	0
T13	254200	50	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	2369625	0	0
T1	47866	517	0	0
T2	755620	8125	0	0
T3	138660	83	0	0
T7	703809	2531	0	0
T8	35525	322	0	0
T9	361401	39760	0	0
T10	25841	179	0	0
T11	11716	180	0	0
T12	95243	6400	0	0
T13	254200	65	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	23889	0	900
T7	703809	6	0	1
T8	35525	0	0	1
T9	361401	0	0	1
T10	25841	0	0	1
T11	11716	0	0	1
T12	95243	97	0	1
T13	254200	0	0	1
T14	99729	130	0	1
T15	0	206	0	0
T16	0	1	0	0
T17	0	840	0	0
T18	0	7	0	0
T19	0	2	0	0
T20	0	45	0	0
T21	0	2	0	0
T23	270562	0	0	1
T24	1839	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	944464	0	0
T1	47866	334	0	0
T2	755620	208	0	0
T3	138660	60	0	0
T7	703809	1390	0	0
T8	35525	221	0	0
T9	361401	996	0	0
T10	25841	163	0	0
T11	11716	101	0	0
T12	95243	6400	0	0
T13	254200	50	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410625352	410501794	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410625352	953388	0	0
GntImpliesValid_A	410625352	953388	0	0
GrantKnown_A	410625352	410501794	0	0
IdxKnown_A	410625352	410501794	0	0
IndexIsCorrect_A	410625352	953388	0	0
LockArbDecision_A	410625352	0	0	0
NoReadyValidNoGrant_A	410625352	343050006	0	0
ReadyAndValidImplyGrant_A	410625352	953388	0	0
ReqAndReadyImplyGrant_A	410625352	953388	0	0
ReqImpliesValid_A	410625352	13650079	0	0
ReqStaysHighUntilGranted0_M	410625352	0	0	0
RoundRobin_A	410625352	42700	0	900
ValidKnown_A	410625352	410501794	0	0
gen_data_port_assertion.DataFlow_A	410625352	953388	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	953388	0	0
T1	47866	318	0	0
T2	755620	217	0	0
T3	138660	50	0	0
T7	703809	4238	0	0
T8	35525	239	0	0
T9	361401	955	0	0
T10	25841	175	0	0
T11	11716	106	0	0
T12	95243	6380	0	0
T13	254200	59	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	953388	0	0
T1	47866	318	0	0
T2	755620	217	0	0
T3	138660	50	0	0
T7	703809	4238	0	0
T8	35525	239	0	0
T9	361401	955	0	0
T10	25841	175	0	0
T11	11716	106	0	0
T12	95243	6380	0	0
T13	254200	59	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	953388	0	0
T1	47866	318	0	0
T2	755620	217	0	0
T3	138660	50	0	0
T7	703809	4238	0	0
T8	35525	239	0	0
T9	361401	955	0	0
T10	25841	175	0	0
T11	11716	106	0	0
T12	95243	6380	0	0
T13	254200	59	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	343050006	0	0
T1	47866	40561	0	0
T2	755620	665741	0	0
T3	138660	115183	0	0
T7	703809	584422	0	0
T8	35525	30546	0	0
T9	361401	325758	0	0
T10	25841	22190	0	0
T11	11716	9601	0	0
T12	95243	1	0	0
T13	254200	211586	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	953388	0	0
T1	47866	318	0	0
T2	755620	217	0	0
T3	138660	50	0	0
T7	703809	4238	0	0
T8	35525	239	0	0
T9	361401	955	0	0
T10	25841	175	0	0
T11	11716	106	0	0
T12	95243	6380	0	0
T13	254200	59	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	953388	0	0
T1	47866	318	0	0
T2	755620	217	0	0
T3	138660	50	0	0
T7	703809	4238	0	0
T8	35525	239	0	0
T9	361401	955	0	0
T10	25841	175	0	0
T11	11716	106	0	0
T12	95243	6380	0	0
T13	254200	59	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	13650079	0	0
T1	47866	2278	0	0
T2	755620	88554	0	0
T3	138660	238	0	0
T7	703809	19368	0	0
T8	35525	1972	0	0
T9	361401	350141	0	0
T10	25841	1421	0	0
T11	11716	740	0	0
T12	95243	6380	0	0
T13	254200	261	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	42700	0	900
T1	47866	1	0	1
T2	755620	0	0	1
T3	138660	0	0	1
T7	703809	61	0	1
T8	35525	0	0	1
T9	361401	0	0	1
T10	25841	0	0	1
T11	11716	0	0	1
T12	95243	298	0	1
T13	254200	0	0	1
T14	0	536	0	0
T15	0	139	0	0
T16	0	1	0	0
T17	0	535	0	0
T18	0	3	0	0
T20	0	945	0	0
T22	0	4	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	410501794	0	0
T1	47866	47814	0	0
T2	755620	755572	0	0
T3	138660	138577	0	0
T7	703809	703802	0	0
T8	35525	35479	0	0
T9	361401	361397	0	0
T10	25841	25815	0	0
T11	11716	11654	0	0
T12	95243	94454	0	0
T13	254200	254161	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410625352	953388	0	0
T1	47866	318	0	0
T2	755620	217	0	0
T3	138660	50	0	0
T7	703809	4238	0	0
T8	35525	239	0	0
T9	361401	955	0	0
T10	25841	175	0	0
T11	11716	106	0	0
T12	95243	6380	0	0
T13	254200	59	0	0