Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1574446	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

249449

1

T1

14

T2

310

T3

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	619615	1			T1	50		T2	776		T3	40
values[0x0]	585224	1			T1	7		T2	768		T3	27
values[0x1]	619056	1			T1	45		T2	771		T3	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1216795	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

607100

1

T1

48

T2

747

T3

36

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29134	1			T1	5		T2	37		T7	125
valid_sources[0x01]	28367	1			T2	37		T7	123		T4	26
valid_sources[0x02]	28961	1			T1	2		T2	30		T7	100
valid_sources[0x03]	29572	1			T1	1		T2	44		T7	194
valid_sources[0x04]	29156	1			T2	31		T3	14		T7	164
valid_sources[0x05]	28841	1			T2	40		T3	9		T7	152
valid_sources[0x06]	28068	1			T1	1		T2	37		T7	174
valid_sources[0x07]	27947	1			T1	8		T2	32		T7	133
valid_sources[0x08]	28500	1			T1	1		T2	52		T7	143
valid_sources[0x09]	27466	1			T1	2		T2	30		T7	165
valid_sources[0x0a]	28078	1			T2	30		T7	135		T4	21
valid_sources[0x0b]	28130	1			T1	1		T2	27		T7	113
valid_sources[0x0c]	28098	1			T1	1		T2	22		T7	145
valid_sources[0x0d]	29674	1			T2	36		T7	125		T4	40
valid_sources[0x0e]	28731	1			T1	1		T2	41		T7	176
valid_sources[0x0f]	27502	1			T2	42		T7	161		T4	12
valid_sources[0x10]	28517	1			T2	33		T7	139		T4	64
valid_sources[0x11]	28540	1			T1	1		T2	30		T3	1
valid_sources[0x12]	29249	1			T2	45		T7	127		T4	19
valid_sources[0x13]	28603	1			T2	34		T7	126		T4	26
valid_sources[0x14]	28191	1			T1	2		T2	46		T3	3
valid_sources[0x15]	27438	1			T1	3		T2	22		T3	10
valid_sources[0x16]	28517	1			T1	1		T2	34		T3	7
valid_sources[0x17]	27723	1			T2	33		T7	119		T4	14
valid_sources[0x18]	28581	1			T1	2		T2	33		T3	7
valid_sources[0x19]	27798	1			T2	40		T7	143		T4	14
valid_sources[0x1a]	28578	1			T1	2		T2	33		T7	124
valid_sources[0x1b]	28842	1			T1	2		T2	32		T3	11
valid_sources[0x1c]	28779	1			T1	3		T2	37		T7	103
valid_sources[0x1d]	28326	1			T1	1		T2	34		T7	99
valid_sources[0x1e]	28856	1			T2	33		T7	126		T4	20
valid_sources[0x1f]	28218	1			T2	41		T7	90		T4	20
valid_sources[0x20]	28680	1			T1	4		T2	41		T7	131

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26191

1

T1

5

T2

26

T3

1

values[0x0]

all_enables

biggest_size

196966

1

T1

2

T2

256

T3

13

values[0x1]

all_enables

biggest_size

26292

1

T1

7

T2

28

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1587596	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

258296

1

T1

5

T2

311

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	632090	1			T1	37		T2	758		T3	33
values[0x0]	581201	1			T1	9		T2	679		T3	44
values[0x1]	632601	1			T1	50		T2	723		T3	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1217368	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

628524

1

T1

29

T2

705

T3

34

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29120	1			T1	1		T2	30		T7	101
valid_sources[0x01]	29027	1			T1	2		T2	30		T3	2
valid_sources[0x02]	29136	1			T1	2		T2	24		T3	7
valid_sources[0x03]	29321	1			T1	1		T2	56		T3	1
valid_sources[0x04]	29337	1			T1	2		T2	24		T3	3
valid_sources[0x05]	28016	1			T2	32		T3	1		T7	161
valid_sources[0x06]	29049	1			T2	19		T3	3		T7	162
valid_sources[0x07]	28214	1			T1	6		T2	20		T3	1
valid_sources[0x08]	28450	1			T1	1		T2	16		T3	4
valid_sources[0x09]	28175	1			T1	2		T2	22		T3	1
valid_sources[0x0a]	28098	1			T2	64		T7	113		T4	1
valid_sources[0x0b]	28895	1			T2	51		T7	133		T4	24
valid_sources[0x0c]	29239	1			T1	1		T2	30		T3	1
valid_sources[0x0d]	28450	1			T1	1		T2	41		T7	92
valid_sources[0x0e]	28789	1			T2	29		T3	3		T7	138
valid_sources[0x0f]	28829	1			T1	3		T2	41		T3	5
valid_sources[0x10]	29061	1			T1	2		T2	64		T7	110
valid_sources[0x11]	28550	1			T1	2		T2	22		T7	108
valid_sources[0x12]	28624	1			T1	2		T2	5		T3	1
valid_sources[0x13]	29165	1			T1	1		T2	24		T3	2
valid_sources[0x14]	29373	1			T2	33		T3	4		T7	104
valid_sources[0x15]	28832	1			T2	15		T3	5		T7	128
valid_sources[0x16]	28323	1			T1	2		T2	67		T3	3
valid_sources[0x17]	29289	1			T1	2		T2	43		T3	1
valid_sources[0x18]	28808	1			T1	2		T2	14		T3	2
valid_sources[0x19]	28587	1			T1	1		T2	25		T3	1
valid_sources[0x1a]	28522	1			T2	12		T3	1		T7	103
valid_sources[0x1b]	28872	1			T1	5		T2	27		T7	143
valid_sources[0x1c]	28389	1			T1	2		T2	21		T3	2
valid_sources[0x1d]	29314	1			T1	2		T2	29		T3	1
valid_sources[0x1e]	29255	1			T2	45		T3	1		T7	131
valid_sources[0x1f]	29096	1			T2	61		T3	4		T7	97
valid_sources[0x20]	29643	1			T1	1		T2	6		T7	135

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27204

1

T1

3

T2

39

T3

1

values[0x0]

all_enables

biggest_size

203742

1

T1

1

T2

249

T3

16

values[0x1]

all_enables

biggest_size

27350

1

T1

1

T2

23

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1587740	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

252791

1

T1

10

T2

276

T3

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	624432	1			T1	33		T2	662		T3	45
values[0x0]	591932	1			T1	8		T2	650		T3	38
values[0x1]	624167	1			T1	42		T2	660		T3	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1227472	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

613059

1

T1

25

T2

660

T3

35

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29138	1			T1	2		T2	35		T3	3
valid_sources[0x01]	29093	1			T2	24		T3	2		T7	158
valid_sources[0x02]	29164	1			T1	1		T2	27		T7	218
valid_sources[0x03]	29017	1			T1	1		T2	29		T3	3
valid_sources[0x04]	29532	1			T1	3		T2	27		T3	2
valid_sources[0x05]	28502	1			T2	35		T3	2		T7	214
valid_sources[0x06]	27886	1			T2	31		T3	1		T7	175
valid_sources[0x07]	28314	1			T2	31		T3	2		T7	240
valid_sources[0x08]	28103	1			T1	1		T2	36		T3	3
valid_sources[0x09]	29105	1			T1	2		T2	22		T3	2
valid_sources[0x0a]	28765	1			T2	34		T3	2		T7	39
valid_sources[0x0b]	28478	1			T2	40		T3	3		T7	74
valid_sources[0x0c]	28662	1			T1	1		T2	36		T3	3
valid_sources[0x0d]	29367	1			T1	1		T2	26		T7	107
valid_sources[0x0e]	28438	1			T1	1		T2	33		T3	2
valid_sources[0x0f]	28316	1			T1	6		T2	32		T3	1
valid_sources[0x10]	27860	1			T1	3		T2	28		T3	2
valid_sources[0x11]	28841	1			T1	1		T2	28		T3	2
valid_sources[0x12]	28522	1			T2	32		T3	1		T7	100
valid_sources[0x13]	30347	1			T2	32		T7	192		T4	5
valid_sources[0x14]	28090	1			T1	1		T2	25		T3	2
valid_sources[0x15]	28549	1			T1	1		T2	31		T3	3
valid_sources[0x16]	28915	1			T2	35		T3	1		T7	127
valid_sources[0x17]	28323	1			T1	2		T2	32		T3	1
valid_sources[0x18]	28590	1			T1	1		T2	38		T3	1
valid_sources[0x19]	29121	1			T1	3		T2	23		T7	72
valid_sources[0x1a]	28433	1			T1	1		T2	41		T3	3
valid_sources[0x1b]	29465	1			T1	4		T2	31		T3	1
valid_sources[0x1c]	28156	1			T2	26		T3	1		T7	36
valid_sources[0x1d]	28786	1			T1	1		T2	33		T3	2
valid_sources[0x1e]	28501	1			T1	1		T2	28		T7	109
valid_sources[0x1f]	29105	1			T1	1		T2	31		T3	1
valid_sources[0x20]	28948	1			T1	2		T2	44		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26478

1

T1

1

T2

37

T3

1

values[0x0]

all_enables

biggest_size

199649

1

T1

6

T2

220

T3

10

values[0x1]

all_enables

biggest_size

26664

1

T1

3

T2

19

T3

1