Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7968046	0	0
GntImpliesValid_A	2147483647	7968046	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7968046	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	466255630	0	0
ReadyAndValidImplyGrant_A	2147483647	7968046	0	0
ReqAndReadyImplyGrant_A	2147483647	7968046	0	0
ReqImpliesValid_A	2147483647	36062731	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	41727	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7968046	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	315264	314040	0	0
T2	5927592	5927520	0	0
T3	3637968	3637704	0	0
T4	820584	819552	0	0
T7	873240	868800	0	0
T8	13145856	13145760	0	0
T9	12664752	12664656	0	0
T10	57672	56184	0	0
T11	6379128	6377208	0	0
T12	2699424	2699304	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7968046	0	0
T1	315264	6173	0	0
T2	5927592	6446	0	0
T3	3637968	321	0	0
T4	820584	2002	0	0
T7	873240	19470	0	0
T8	13145856	11202	0	0
T9	12664752	11319	0	0
T10	57672	460	0	0
T11	6379128	426	0	0
T12	2699424	3854	0	0
T13	0	406	0	0
T14	0	62	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7968046	0	0
T1	315264	6173	0	0
T2	5927592	6446	0	0
T3	3637968	321	0	0
T4	820584	2002	0	0
T7	873240	19470	0	0
T8	13145856	11202	0	0
T9	12664752	11319	0	0
T10	57672	460	0	0
T11	6379128	426	0	0
T12	2699424	3854	0	0
T13	0	406	0	0
T14	0	62	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	315264	314040	0	0
T2	5927592	5927520	0	0
T3	3637968	3637704	0	0
T4	820584	819552	0	0
T7	873240	868800	0	0
T8	13145856	13145760	0	0
T9	12664752	12664656	0	0
T10	57672	56184	0	0
T11	6379128	6377208	0	0
T12	2699424	2699304	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	315264	314040	0	0
T2	5927592	5927520	0	0
T3	3637968	3637704	0	0
T4	820584	819552	0	0
T7	873240	868800	0	0
T8	13145856	13145760	0	0
T9	12664752	12664656	0	0
T10	57672	56184	0	0
T11	6379128	6377208	0	0
T12	2699424	2699304	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7968046	0	0
T1	315264	6173	0	0
T2	5927592	6446	0	0
T3	3637968	321	0	0
T4	820584	2002	0	0
T7	873240	19470	0	0
T8	13145856	11202	0	0
T9	12664752	11319	0	0
T10	57672	460	0	0
T11	6379128	426	0	0
T12	2699424	3854	0	0
T13	0	406	0	0
T14	0	62	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	466255630	0	0
T1	315264	9857	0	0
T2	5927592	2212958	0	0
T3	3637968	127364	0	0
T4	820584	46409	0	0
T7	873240	25079	0	0
T8	13145856	486945	0	0
T9	12664752	482010	0	0
T10	57672	735	0	0
T11	6379128	222958	0	0
T12	2699424	956903	0	0
T13	0	317	0	0
T14	0	171	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7968046	0	0
T1	315264	6173	0	0
T2	5927592	6446	0	0
T3	3637968	321	0	0
T4	820584	2002	0	0
T7	873240	19470	0	0
T8	13145856	11202	0	0
T9	12664752	11319	0	0
T10	57672	460	0	0
T11	6379128	426	0	0
T12	2699424	3854	0	0
T13	0	406	0	0
T14	0	62	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7968046	0	0
T1	315264	6173	0	0
T2	5927592	6446	0	0
T3	3637968	321	0	0
T4	820584	2002	0	0
T7	873240	19470	0	0
T8	13145856	11202	0	0
T9	12664752	11319	0	0
T10	57672	460	0	0
T11	6379128	426	0	0
T12	2699424	3854	0	0
T13	0	406	0	0
T14	0	62	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36062731	0	0
T1	315264	7564	0	0
T2	5927592	411428	0	0
T3	3637968	534	0	0
T4	820584	4227	0	0
T7	873240	21544	0	0
T8	13145856	31863	0	0
T9	12664752	29652	0	0
T10	57672	504	0	0
T11	6379128	696	0	0
T12	2699424	6908	0	0
T13	0	456	0	0
T14	0	90	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41727	0	21600
T1	26272	19	0	2
T2	493966	0	0	2
T3	303164	0	0	2
T4	68382	0	0	2
T7	72770	87	0	2
T8	1095488	34	0	2
T9	1055396	9	0	2
T10	4806	0	0	2
T11	531594	0	0	2
T12	224952	0	0	2
T13	0	5	0	0
T15	0	428	0	0
T16	0	410	0	0
T17	0	23	0	0
T18	0	2	0	0
T19	0	33	0	0
T20	0	3	0	0
T21	0	6	0	0
T22	0	4	0	0
T23	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	315264	314040	0	0
T2	5927592	5927520	0	0
T3	3637968	3637704	0	0
T4	820584	819552	0	0
T7	873240	868800	0	0
T8	13145856	13145760	0	0
T9	12664752	12664656	0	0
T10	57672	56184	0	0
T11	6379128	6377208	0	0
T12	2699424	2699304	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7968046	0	0
T1	315264	6173	0	0
T2	5927592	6446	0	0
T3	3637968	321	0	0
T4	820584	2002	0	0
T7	873240	19470	0	0
T8	13145856	11202	0	0
T9	12664752	11319	0	0
T10	57672	460	0	0
T11	6379128	426	0	0
T12	2699424	3854	0	0
T13	0	406	0	0
T14	0	62	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	872317	0	0
GntImpliesValid_A	422224717	872317	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	872317	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	12847434	0	0
ReadyAndValidImplyGrant_A	422224717	872317	0	0
ReqAndReadyImplyGrant_A	422224717	872317	0	0
ReqImpliesValid_A	422224717	2455409	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	872317	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	872317	0	0
T1	13136	719	0	0
T2	246983	686	0	0
T3	151582	49	0	0
T4	34191	206	0	0
T7	36385	2130	0	0
T8	547744	579	0	0
T9	527698	821	0	0
T10	2403	41	0	0
T11	265797	76	0	0
T12	112476	437	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	872317	0	0
T1	13136	719	0	0
T2	246983	686	0	0
T3	151582	49	0	0
T4	34191	206	0	0
T7	36385	2130	0	0
T8	547744	579	0	0
T9	527698	821	0	0
T10	2403	41	0	0
T11	265797	76	0	0
T12	112476	437	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	872317	0	0
T1	13136	719	0	0
T2	246983	686	0	0
T3	151582	49	0	0
T4	34191	206	0	0
T7	36385	2130	0	0
T8	547744	579	0	0
T9	527698	821	0	0
T10	2403	41	0	0
T11	265797	76	0	0
T12	112476	437	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	12847434	0	0
T1	13136	535	0	0
T2	246983	229105	0	0
T3	151582	204	0	0
T4	34191	1617	0	0
T7	36385	1741	0	0
T8	547744	2421	0	0
T9	527698	3423	0	0
T10	2403	38	0	0
T11	265797	295	0	0
T12	112476	1824	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	872317	0	0
T1	13136	719	0	0
T2	246983	686	0	0
T3	151582	49	0	0
T4	34191	206	0	0
T7	36385	2130	0	0
T8	547744	579	0	0
T9	527698	821	0	0
T10	2403	41	0	0
T11	265797	76	0	0
T12	112476	437	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	872317	0	0
T1	13136	719	0	0
T2	246983	686	0	0
T3	151582	49	0	0
T4	34191	206	0	0
T7	36385	2130	0	0
T8	547744	579	0	0
T9	527698	821	0	0
T10	2403	41	0	0
T11	265797	76	0	0
T12	112476	437	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	2455409	0	0
T1	13136	904	0	0
T2	246983	25094	0	0
T3	151582	87	0	0
T4	34191	299	0	0
T7	36385	2522	0	0
T8	547744	819	0	0
T9	527698	1165	0	0
T10	2403	45	0	0
T11	265797	112	0	0
T12	112476	568	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	872317	0	0
T1	13136	719	0	0
T2	246983	686	0	0
T3	151582	49	0	0
T4	34191	206	0	0
T7	36385	2130	0	0
T8	547744	579	0	0
T9	527698	821	0	0
T10	2403	41	0	0
T11	265797	76	0	0
T12	112476	437	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	877993	0	0
GntImpliesValid_A	422224717	877993	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	877993	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	13050141	0	0
ReadyAndValidImplyGrant_A	422224717	877993	0	0
ReqAndReadyImplyGrant_A	422224717	877993	0	0
ReqImpliesValid_A	422224717	2585788	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	877993	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	877993	0	0
T1	13136	673	0	0
T2	246983	714	0	0
T3	151582	40	0	0
T4	34191	202	0	0
T7	36385	2089	0	0
T8	547744	2057	0	0
T9	527698	1470	0	0
T10	2403	53	0	0
T11	265797	51	0	0
T12	112476	399	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	877993	0	0
T1	13136	673	0	0
T2	246983	714	0	0
T3	151582	40	0	0
T4	34191	202	0	0
T7	36385	2089	0	0
T8	547744	2057	0	0
T9	527698	1470	0	0
T10	2403	53	0	0
T11	265797	51	0	0
T12	112476	399	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	877993	0	0
T1	13136	673	0	0
T2	246983	714	0	0
T3	151582	40	0	0
T4	34191	202	0	0
T7	36385	2089	0	0
T8	547744	2057	0	0
T9	527698	1470	0	0
T10	2403	53	0	0
T11	265797	51	0	0
T12	112476	399	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	13050141	0	0
T1	13136	499	0	0
T2	246983	239227	0	0
T3	151582	155	0	0
T4	34191	1432	0	0
T7	36385	1714	0	0
T8	547744	7129	0	0
T9	527698	5377	0	0
T10	2403	42	0	0
T11	265797	208	0	0
T12	112476	1575	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	877993	0	0
T1	13136	673	0	0
T2	246983	714	0	0
T3	151582	40	0	0
T4	34191	202	0	0
T7	36385	2089	0	0
T8	547744	2057	0	0
T9	527698	1470	0	0
T10	2403	53	0	0
T11	265797	51	0	0
T12	112476	399	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	877993	0	0
T1	13136	673	0	0
T2	246983	714	0	0
T3	151582	40	0	0
T4	34191	202	0	0
T7	36385	2089	0	0
T8	547744	2057	0	0
T9	527698	1470	0	0
T10	2403	53	0	0
T11	265797	51	0	0
T12	112476	399	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	2585788	0	0
T1	13136	848	0	0
T2	246983	25832	0	0
T3	151582	67	0	0
T4	34191	306	0	0
T7	36385	2467	0	0
T8	547744	4458	0	0
T9	527698	2809	0	0
T10	2403	65	0	0
T11	265797	58	0	0
T12	112476	575	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	877993	0	0
T1	13136	673	0	0
T2	246983	714	0	0
T3	151582	40	0	0
T4	34191	202	0	0
T7	36385	2089	0	0
T8	547744	2057	0	0
T9	527698	1470	0	0
T10	2403	53	0	0
T11	265797	51	0	0
T12	112476	399	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	222140	0	0
GntImpliesValid_A	422224717	222140	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	222140	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	3265872	0	0
ReadyAndValidImplyGrant_A	422224717	222140	0	0
ReqAndReadyImplyGrant_A	422224717	222140	0	0
ReqImpliesValid_A	422224717	580407	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	222140	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	222140	0	0
T1	13136	174	0	0
T2	246983	166	0	0
T3	151582	7	0	0
T4	34191	52	0	0
T7	36385	545	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	11	0	0
T11	265797	6	0	0
T12	112476	129	0	0
T13	0	33	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	222140	0	0
T1	13136	174	0	0
T2	246983	166	0	0
T3	151582	7	0	0
T4	34191	52	0	0
T7	36385	545	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	11	0	0
T11	265797	6	0	0
T12	112476	129	0	0
T13	0	33	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	222140	0	0
T1	13136	174	0	0
T2	246983	166	0	0
T3	151582	7	0	0
T4	34191	52	0	0
T7	36385	545	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	11	0	0
T11	265797	6	0	0
T12	112476	129	0	0
T13	0	33	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	3265872	0	0
T1	13136	166	0	0
T2	246983	58801	0	0
T3	151582	36	0	0
T4	34191	414	0	0
T7	36385	527	0	0
T8	547744	1	0	0
T9	527698	1	0	0
T10	2403	12	0	0
T11	265797	27	0	0
T12	112476	514	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	222140	0	0
T1	13136	174	0	0
T2	246983	166	0	0
T3	151582	7	0	0
T4	34191	52	0	0
T7	36385	545	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	11	0	0
T11	265797	6	0	0
T12	112476	129	0	0
T13	0	33	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	222140	0	0
T1	13136	174	0	0
T2	246983	166	0	0
T3	151582	7	0	0
T4	34191	52	0	0
T7	36385	545	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	11	0	0
T11	265797	6	0	0
T12	112476	129	0	0
T13	0	33	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	580407	0	0
T1	13136	183	0	0
T2	246983	1566	0	0
T3	151582	7	0	0
T4	34191	56	0	0
T7	36385	566	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	11	0	0
T11	265797	8	0	0
T12	112476	142	0	0
T13	0	35	0	0
T14	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	222140	0	0
T1	13136	174	0	0
T2	246983	166	0	0
T3	151582	7	0	0
T4	34191	52	0	0
T7	36385	545	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	11	0	0
T11	265797	6	0	0
T12	112476	129	0	0
T13	0	33	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	221924	0	0
GntImpliesValid_A	422224717	221924	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	221924	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	3266353	0	0
ReadyAndValidImplyGrant_A	422224717	221924	0	0
ReqAndReadyImplyGrant_A	422224717	221924	0	0
ReqImpliesValid_A	422224717	587494	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	221924	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	221924	0	0
T1	13136	171	0	0
T2	246983	170	0	0
T3	151582	6	0	0
T4	34191	69	0	0
T7	36385	520	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	9	0	0
T11	265797	6	0	0
T12	112476	111	0	0
T13	0	30	0	0
T14	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	221924	0	0
T1	13136	171	0	0
T2	246983	170	0	0
T3	151582	6	0	0
T4	34191	69	0	0
T7	36385	520	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	9	0	0
T11	265797	6	0	0
T12	112476	111	0	0
T13	0	30	0	0
T14	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	221924	0	0
T1	13136	171	0	0
T2	246983	170	0	0
T3	151582	6	0	0
T4	34191	69	0	0
T7	36385	520	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	9	0	0
T11	265797	6	0	0
T12	112476	111	0	0
T13	0	30	0	0
T14	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	3266353	0	0
T1	13136	164	0	0
T2	246983	59643	0	0
T3	151582	35	0	0
T4	34191	542	0	0
T7	36385	512	0	0
T8	547744	1	0	0
T9	527698	1	0	0
T10	2403	10	0	0
T11	265797	22	0	0
T12	112476	443	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	221924	0	0
T1	13136	171	0	0
T2	246983	170	0	0
T3	151582	6	0	0
T4	34191	69	0	0
T7	36385	520	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	9	0	0
T11	265797	6	0	0
T12	112476	111	0	0
T13	0	30	0	0
T14	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	221924	0	0
T1	13136	171	0	0
T2	246983	170	0	0
T3	151582	6	0	0
T4	34191	69	0	0
T7	36385	520	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	9	0	0
T11	265797	6	0	0
T12	112476	111	0	0
T13	0	30	0	0
T14	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	587494	0	0
T1	13136	179	0	0
T2	246983	2937	0	0
T3	151582	6	0	0
T4	34191	76	0	0
T7	36385	531	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	9	0	0
T11	265797	9	0	0
T12	112476	134	0	0
T13	0	32	0	0
T14	0	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	221924	0	0
T1	13136	171	0	0
T2	246983	170	0	0
T3	151582	6	0	0
T4	34191	69	0	0
T7	36385	520	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	9	0	0
T11	265797	6	0	0
T12	112476	111	0	0
T13	0	30	0	0
T14	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	222751	0	0
GntImpliesValid_A	422224717	222751	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	222751	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	5290317	0	0
ReadyAndValidImplyGrant_A	422224717	222751	0	0
ReqAndReadyImplyGrant_A	422224717	222751	0	0
ReqImpliesValid_A	422224717	1136033	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	222751	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	222751	0	0
T1	13136	165	0	0
T2	246983	174	0	0
T3	151582	11	0	0
T4	34191	49	0	0
T7	36385	540	0	0
T8	547744	0	0	0
T9	527698	549	0	0
T10	2403	13	0	0
T11	265797	8	0	0
T12	112476	121	0	0
T13	0	23	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	222751	0	0
T1	13136	165	0	0
T2	246983	174	0	0
T3	151582	11	0	0
T4	34191	49	0	0
T7	36385	540	0	0
T8	547744	0	0	0
T9	527698	549	0	0
T10	2403	13	0	0
T11	265797	8	0	0
T12	112476	121	0	0
T13	0	23	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	222751	0	0
T1	13136	165	0	0
T2	246983	174	0	0
T3	151582	11	0	0
T4	34191	49	0	0
T7	36385	540	0	0
T8	547744	0	0	0
T9	527698	549	0	0
T10	2403	13	0	0
T11	265797	8	0	0
T12	112476	121	0	0
T13	0	23	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	5290317	0	0
T1	13136	1913	0	0
T2	246983	168385	0	0
T3	151582	64	0	0
T4	34191	1748	0	0
T7	36385	2822	0	0
T8	547744	0	0	0
T9	527698	10650	0	0
T10	2403	74	0	0
T11	265797	120	0	0
T12	112476	1065	0	0
T13	0	78	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	222751	0	0
T1	13136	165	0	0
T2	246983	174	0	0
T3	151582	11	0	0
T4	34191	49	0	0
T7	36385	540	0	0
T8	547744	0	0	0
T9	527698	549	0	0
T10	2403	13	0	0
T11	265797	8	0	0
T12	112476	121	0	0
T13	0	23	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	222751	0	0
T1	13136	165	0	0
T2	246983	174	0	0
T3	151582	11	0	0
T4	34191	49	0	0
T7	36385	540	0	0
T8	547744	0	0	0
T9	527698	549	0	0
T10	2403	13	0	0
T11	265797	8	0	0
T12	112476	121	0	0
T13	0	23	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	1136033	0	0
T1	13136	401	0	0
T2	246983	12531	0	0
T3	151582	11	0	0
T4	34191	83	0	0
T7	36385	744	0	0
T8	547744	0	0	0
T9	527698	3807	0	0
T10	2403	18	0	0
T11	265797	8	0	0
T12	112476	182	0	0
T13	0	29	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	222751	0	0
T1	13136	165	0	0
T2	246983	174	0	0
T3	151582	11	0	0
T4	34191	49	0	0
T7	36385	540	0	0
T8	547744	0	0	0
T9	527698	549	0	0
T10	2403	13	0	0
T11	265797	8	0	0
T12	112476	121	0	0
T13	0	23	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	212617	0	0
GntImpliesValid_A	422224717	212617	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	212617	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	5836454	0	0
ReadyAndValidImplyGrant_A	422224717	212617	0	0
ReqAndReadyImplyGrant_A	422224717	212617	0	0
ReqImpliesValid_A	422224717	1105919	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	212617	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	212617	0	0
T1	13136	177	0	0
T2	246983	191	0	0
T3	151582	10	0	0
T4	34191	62	0	0
T7	36385	563	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	9	0	0
T11	265797	8	0	0
T12	112476	93	0	0
T13	0	24	0	0
T14	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	212617	0	0
T1	13136	177	0	0
T2	246983	191	0	0
T3	151582	10	0	0
T4	34191	62	0	0
T7	36385	563	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	9	0	0
T11	265797	8	0	0
T12	112476	93	0	0
T13	0	24	0	0
T14	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	212617	0	0
T1	13136	177	0	0
T2	246983	191	0	0
T3	151582	10	0	0
T4	34191	62	0	0
T7	36385	563	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	9	0	0
T11	265797	8	0	0
T12	112476	93	0	0
T13	0	24	0	0
T14	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	5836454	0	0
T1	13136	979	0	0
T2	246983	51959	0	0
T3	151582	43	0	0
T4	34191	779	0	0
T7	36385	2840	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	175	0	0
T11	265797	87	0	0
T12	112476	896	0	0
T13	0	72	0	0
T14	0	106	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	212617	0	0
T1	13136	177	0	0
T2	246983	191	0	0
T3	151582	10	0	0
T4	34191	62	0	0
T7	36385	563	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	9	0	0
T11	265797	8	0	0
T12	112476	93	0	0
T13	0	24	0	0
T14	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	212617	0	0
T1	13136	177	0	0
T2	246983	191	0	0
T3	151582	10	0	0
T4	34191	62	0	0
T7	36385	563	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	9	0	0
T11	265797	8	0	0
T12	112476	93	0	0
T13	0	24	0	0
T14	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	1105919	0	0
T1	13136	321	0	0
T2	246983	4801	0	0
T3	151582	10	0	0
T4	34191	100	0	0
T7	36385	785	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	9	0	0
T11	265797	8	0	0
T12	112476	107	0	0
T13	0	41	0	0
T14	0	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	212617	0	0
T1	13136	177	0	0
T2	246983	191	0	0
T3	151582	10	0	0
T4	34191	62	0	0
T7	36385	563	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	9	0	0
T11	265797	8	0	0
T12	112476	93	0	0
T13	0	24	0	0
T14	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	215878	0	0
GntImpliesValid_A	422224717	215878	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	215878	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	5111493	0	0
ReadyAndValidImplyGrant_A	422224717	215878	0	0
ReqAndReadyImplyGrant_A	422224717	215878	0	0
ReqImpliesValid_A	422224717	1164107	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	215878	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	215878	0	0
T1	13136	176	0	0
T2	246983	169	0	0
T3	151582	7	0	0
T4	34191	64	0	0
T7	36385	609	0	0
T8	547744	1503	0	0
T9	527698	0	0	0
T10	2403	14	0	0
T11	265797	8	0	0
T12	112476	99	0	0
T13	0	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	215878	0	0
T1	13136	176	0	0
T2	246983	169	0	0
T3	151582	7	0	0
T4	34191	64	0	0
T7	36385	609	0	0
T8	547744	1503	0	0
T9	527698	0	0	0
T10	2403	14	0	0
T11	265797	8	0	0
T12	112476	99	0	0
T13	0	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	215878	0	0
T1	13136	176	0	0
T2	246983	169	0	0
T3	151582	7	0	0
T4	34191	64	0	0
T7	36385	609	0	0
T8	547744	1503	0	0
T9	527698	0	0	0
T10	2403	14	0	0
T11	265797	8	0	0
T12	112476	99	0	0
T13	0	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	5111493	0	0
T1	13136	1845	0	0
T2	246983	126248	0	0
T3	151582	41	0	0
T4	34191	860	0	0
T7	36385	3727	0	0
T8	547744	8505	0	0
T9	527698	0	0	0
T10	2403	54	0	0
T11	265797	75	0	0
T12	112476	3679	0	0
T13	0	66	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	215878	0	0
T1	13136	176	0	0
T2	246983	169	0	0
T3	151582	7	0	0
T4	34191	64	0	0
T7	36385	609	0	0
T8	547744	1503	0	0
T9	527698	0	0	0
T10	2403	14	0	0
T11	265797	8	0	0
T12	112476	99	0	0
T13	0	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	215878	0	0
T1	13136	176	0	0
T2	246983	169	0	0
T3	151582	7	0	0
T4	34191	64	0	0
T7	36385	609	0	0
T8	547744	1503	0	0
T9	527698	0	0	0
T10	2403	14	0	0
T11	265797	8	0	0
T12	112476	99	0	0
T13	0	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	1164107	0	0
T1	13136	445	0	0
T2	246983	11174	0	0
T3	151582	7	0	0
T4	34191	85	0	0
T7	36385	874	0	0
T8	547744	4372	0	0
T9	527698	0	0	0
T10	2403	22	0	0
T11	265797	8	0	0
T12	112476	422	0	0
T13	0	26	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	215878	0	0
T1	13136	176	0	0
T2	246983	169	0	0
T3	151582	7	0	0
T4	34191	64	0	0
T7	36385	609	0	0
T8	547744	1503	0	0
T9	527698	0	0	0
T10	2403	14	0	0
T11	265797	8	0	0
T12	112476	99	0	0
T13	0	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	223671	0	0
GntImpliesValid_A	422224717	223671	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	223671	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	5062771	0	0
ReadyAndValidImplyGrant_A	422224717	223671	0	0
ReqAndReadyImplyGrant_A	422224717	223671	0	0
ReqImpliesValid_A	422224717	1175348	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	223671	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	223671	0	0
T1	13136	154	0	0
T2	246983	169	0	0
T3	151582	11	0	0
T4	34191	62	0	0
T7	36385	549	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	16	0	0
T11	265797	6	0	0
T12	112476	100	0	0
T13	0	24	0	0
T14	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	223671	0	0
T1	13136	154	0	0
T2	246983	169	0	0
T3	151582	11	0	0
T4	34191	62	0	0
T7	36385	549	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	16	0	0
T11	265797	6	0	0
T12	112476	100	0	0
T13	0	24	0	0
T14	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	223671	0	0
T1	13136	154	0	0
T2	246983	169	0	0
T3	151582	11	0	0
T4	34191	62	0	0
T7	36385	549	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	16	0	0
T11	265797	6	0	0
T12	112476	100	0	0
T13	0	24	0	0
T14	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	5062771	0	0
T1	13136	1449	0	0
T2	246983	26904	0	0
T3	151582	48	0	0
T4	34191	1945	0	0
T7	36385	3745	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	132	0	0
T11	265797	62	0	0
T12	112476	2916	0	0
T13	0	101	0	0
T14	0	65	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	223671	0	0
T1	13136	154	0	0
T2	246983	169	0	0
T3	151582	11	0	0
T4	34191	62	0	0
T7	36385	549	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	16	0	0
T11	265797	6	0	0
T12	112476	100	0	0
T13	0	24	0	0
T14	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	223671	0	0
T1	13136	154	0	0
T2	246983	169	0	0
T3	151582	11	0	0
T4	34191	62	0	0
T7	36385	549	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	16	0	0
T11	265797	6	0	0
T12	112476	100	0	0
T13	0	24	0	0
T14	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	1175348	0	0
T1	13136	390	0	0
T2	246983	704	0	0
T3	151582	11	0	0
T4	34191	155	0	0
T7	36385	890	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	23	0	0
T11	265797	19	0	0
T12	112476	397	0	0
T13	0	31	0	0
T14	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	223671	0	0
T1	13136	154	0	0
T2	246983	169	0	0
T3	151582	11	0	0
T4	34191	62	0	0
T7	36385	549	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	16	0	0
T11	265797	6	0	0
T12	112476	100	0	0
T13	0	24	0	0
T14	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	223740	0	0
GntImpliesValid_A	422224717	223740	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	223740	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	3289589	0	0
ReadyAndValidImplyGrant_A	422224717	223740	0	0
ReqAndReadyImplyGrant_A	422224717	223740	0	0
ReqImpliesValid_A	422224717	575193	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	223740	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	223740	0	0
T1	13136	178	0	0
T2	246983	182	0	0
T3	151582	10	0	0
T4	34191	67	0	0
T7	36385	488	0	0
T8	547744	0	0	0
T9	527698	544	0	0
T10	2403	18	0	0
T11	265797	7	0	0
T12	112476	78	0	0
T13	0	22	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	223740	0	0
T1	13136	178	0	0
T2	246983	182	0	0
T3	151582	10	0	0
T4	34191	67	0	0
T7	36385	488	0	0
T8	547744	0	0	0
T9	527698	544	0	0
T10	2403	18	0	0
T11	265797	7	0	0
T12	112476	78	0	0
T13	0	22	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	223740	0	0
T1	13136	178	0	0
T2	246983	182	0	0
T3	151582	10	0	0
T4	34191	67	0	0
T7	36385	488	0	0
T8	547744	0	0	0
T9	527698	544	0	0
T10	2403	18	0	0
T11	265797	7	0	0
T12	112476	78	0	0
T13	0	22	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	3289589	0	0
T1	13136	174	0	0
T2	246983	60563	0	0
T3	151582	42	0	0
T4	34191	515	0	0
T7	36385	477	0	0
T8	547744	1	0	0
T9	527698	1876	0	0
T10	2403	17	0	0
T11	265797	30	0	0
T12	112476	336	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	223740	0	0
T1	13136	178	0	0
T2	246983	182	0	0
T3	151582	10	0	0
T4	34191	67	0	0
T7	36385	488	0	0
T8	547744	0	0	0
T9	527698	544	0	0
T10	2403	18	0	0
T11	265797	7	0	0
T12	112476	78	0	0
T13	0	22	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	223740	0	0
T1	13136	178	0	0
T2	246983	182	0	0
T3	151582	10	0	0
T4	34191	67	0	0
T7	36385	488	0	0
T8	547744	0	0	0
T9	527698	544	0	0
T10	2403	18	0	0
T11	265797	7	0	0
T12	112476	78	0	0
T13	0	22	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	575193	0	0
T1	13136	183	0	0
T2	246983	4407	0	0
T3	151582	13	0	0
T4	34191	104	0	0
T7	36385	502	0	0
T8	547744	0	0	0
T9	527698	1147	0	0
T10	2403	20	0	0
T11	265797	7	0	0
T12	112476	92	0	0
T13	0	22	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	223740	0	0
T1	13136	178	0	0
T2	246983	182	0	0
T3	151582	10	0	0
T4	34191	67	0	0
T7	36385	488	0	0
T8	547744	0	0	0
T9	527698	544	0	0
T10	2403	18	0	0
T11	265797	7	0	0
T12	112476	78	0	0
T13	0	22	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	231732	0	0
GntImpliesValid_A	422224717	231732	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	231732	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	3226321	0	0
ReadyAndValidImplyGrant_A	422224717	231732	0	0
ReqAndReadyImplyGrant_A	422224717	231732	0	0
ReqImpliesValid_A	422224717	628034	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	231732	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	231732	0	0
T1	13136	157	0	0
T2	246983	203	0	0
T3	151582	11	0	0
T4	34191	55	0	0
T7	36385	535	0	0
T8	547744	1026	0	0
T9	527698	0	0	0
T10	2403	26	0	0
T11	265797	8	0	0
T12	112476	117	0	0
T13	0	26	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	231732	0	0
T1	13136	157	0	0
T2	246983	203	0	0
T3	151582	11	0	0
T4	34191	55	0	0
T7	36385	535	0	0
T8	547744	1026	0	0
T9	527698	0	0	0
T10	2403	26	0	0
T11	265797	8	0	0
T12	112476	117	0	0
T13	0	26	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	231732	0	0
T1	13136	157	0	0
T2	246983	203	0	0
T3	151582	11	0	0
T4	34191	55	0	0
T7	36385	535	0	0
T8	547744	1026	0	0
T9	527698	0	0	0
T10	2403	26	0	0
T11	265797	8	0	0
T12	112476	117	0	0
T13	0	26	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	3226321	0	0
T1	13136	150	0	0
T2	246983	58452	0	0
T3	151582	67	0	0
T4	34191	402	0	0
T7	36385	521	0	0
T8	547744	3344	0	0
T9	527698	1	0	0
T10	2403	24	0	0
T11	265797	28	0	0
T12	112476	547	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	231732	0	0
T1	13136	157	0	0
T2	246983	203	0	0
T3	151582	11	0	0
T4	34191	55	0	0
T7	36385	535	0	0
T8	547744	1026	0	0
T9	527698	0	0	0
T10	2403	26	0	0
T11	265797	8	0	0
T12	112476	117	0	0
T13	0	26	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	231732	0	0
T1	13136	157	0	0
T2	246983	203	0	0
T3	151582	11	0	0
T4	34191	55	0	0
T7	36385	535	0	0
T8	547744	1026	0	0
T9	527698	0	0	0
T10	2403	26	0	0
T11	265797	8	0	0
T12	112476	117	0	0
T13	0	26	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	628034	0	0
T1	13136	165	0	0
T2	246983	2409	0	0
T3	151582	20	0	0
T4	34191	72	0	0
T7	36385	552	0	0
T8	547744	2424	0	0
T9	527698	0	0	0
T10	2403	29	0	0
T11	265797	8	0	0
T12	112476	134	0	0
T13	0	26	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	231732	0	0
T1	13136	157	0	0
T2	246983	203	0	0
T3	151582	11	0	0
T4	34191	55	0	0
T7	36385	535	0	0
T8	547744	1026	0	0
T9	527698	0	0	0
T10	2403	26	0	0
T11	265797	8	0	0
T12	112476	117	0	0
T13	0	26	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	226885	0	0
GntImpliesValid_A	422224717	226885	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	226885	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	3190613	0	0
ReadyAndValidImplyGrant_A	422224717	226885	0	0
ReqAndReadyImplyGrant_A	422224717	226885	0	0
ReqImpliesValid_A	422224717	615139	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	226885	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	226885	0	0
T1	13136	169	0	0
T2	246983	188	0	0
T3	151582	4	0	0
T4	34191	52	0	0
T7	36385	589	0	0
T8	547744	551	0	0
T9	527698	523	0	0
T10	2403	9	0	0
T11	265797	11	0	0
T12	112476	106	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	226885	0	0
T1	13136	169	0	0
T2	246983	188	0	0
T3	151582	4	0	0
T4	34191	52	0	0
T7	36385	589	0	0
T8	547744	551	0	0
T9	527698	523	0	0
T10	2403	9	0	0
T11	265797	11	0	0
T12	112476	106	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	226885	0	0
T1	13136	169	0	0
T2	246983	188	0	0
T3	151582	4	0	0
T4	34191	52	0	0
T7	36385	589	0	0
T8	547744	551	0	0
T9	527698	523	0	0
T10	2403	9	0	0
T11	265797	11	0	0
T12	112476	106	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	3190613	0	0
T1	13136	161	0	0
T2	246983	60349	0	0
T3	151582	17	0	0
T4	34191	395	0	0
T7	36385	579	0	0
T8	547744	1938	0	0
T9	527698	1773	0	0
T10	2403	10	0	0
T11	265797	54	0	0
T12	112476	468	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	226885	0	0
T1	13136	169	0	0
T2	246983	188	0	0
T3	151582	4	0	0
T4	34191	52	0	0
T7	36385	589	0	0
T8	547744	551	0	0
T9	527698	523	0	0
T10	2403	9	0	0
T11	265797	11	0	0
T12	112476	106	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	226885	0	0
T1	13136	169	0	0
T2	246983	188	0	0
T3	151582	4	0	0
T4	34191	52	0	0
T7	36385	589	0	0
T8	547744	551	0	0
T9	527698	523	0	0
T10	2403	9	0	0
T11	265797	11	0	0
T12	112476	106	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	615139	0	0
T1	13136	178	0	0
T2	246983	2587	0	0
T3	151582	4	0	0
T4	34191	52	0	0
T7	36385	602	0	0
T8	547744	1205	0	0
T9	527698	1143	0	0
T10	2403	9	0	0
T11	265797	20	0	0
T12	112476	120	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	226885	0	0
T1	13136	169	0	0
T2	246983	188	0	0
T3	151582	4	0	0
T4	34191	52	0	0
T7	36385	589	0	0
T8	547744	551	0	0
T9	527698	523	0	0
T10	2403	9	0	0
T11	265797	11	0	0
T12	112476	106	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	220768	0	0
GntImpliesValid_A	422224717	220768	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	220768	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	3263010	0	0
ReadyAndValidImplyGrant_A	422224717	220768	0	0
ReqAndReadyImplyGrant_A	422224717	220768	0	0
ReqImpliesValid_A	422224717	580491	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	220768	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	220768	0	0
T1	13136	197	0	0
T2	246983	173	0	0
T3	151582	15	0	0
T4	34191	51	0	0
T7	36385	534	0	0
T8	547744	0	0	0
T9	527698	543	0	0
T10	2403	12	0	0
T11	265797	8	0	0
T12	112476	100	0	0
T13	0	28	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	220768	0	0
T1	13136	197	0	0
T2	246983	173	0	0
T3	151582	15	0	0
T4	34191	51	0	0
T7	36385	534	0	0
T8	547744	0	0	0
T9	527698	543	0	0
T10	2403	12	0	0
T11	265797	8	0	0
T12	112476	100	0	0
T13	0	28	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	220768	0	0
T1	13136	197	0	0
T2	246983	173	0	0
T3	151582	15	0	0
T4	34191	51	0	0
T7	36385	534	0	0
T8	547744	0	0	0
T9	527698	543	0	0
T10	2403	12	0	0
T11	265797	8	0	0
T12	112476	100	0	0
T13	0	28	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	3263010	0	0
T1	13136	185	0	0
T2	246983	50073	0	0
T3	151582	79	0	0
T4	34191	371	0	0
T7	36385	515	0	0
T8	547744	1	0	0
T9	527698	1828	0	0
T10	2403	13	0	0
T11	265797	27	0	0
T12	112476	418	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	220768	0	0
T1	13136	197	0	0
T2	246983	173	0	0
T3	151582	15	0	0
T4	34191	51	0	0
T7	36385	534	0	0
T8	547744	0	0	0
T9	527698	543	0	0
T10	2403	12	0	0
T11	265797	8	0	0
T12	112476	100	0	0
T13	0	28	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	220768	0	0
T1	13136	197	0	0
T2	246983	173	0	0
T3	151582	15	0	0
T4	34191	51	0	0
T7	36385	534	0	0
T8	547744	0	0	0
T9	527698	543	0	0
T10	2403	12	0	0
T11	265797	8	0	0
T12	112476	100	0	0
T13	0	28	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	580491	0	0
T1	13136	210	0	0
T2	246983	4815	0	0
T3	151582	15	0	0
T4	34191	51	0	0
T7	36385	556	0	0
T8	547744	0	0	0
T9	527698	1200	0	0
T10	2403	12	0	0
T11	265797	8	0	0
T12	112476	137	0	0
T13	0	30	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	220768	0	0
T1	13136	197	0	0
T2	246983	173	0	0
T3	151582	15	0	0
T4	34191	51	0	0
T7	36385	534	0	0
T8	547744	0	0	0
T9	527698	543	0	0
T10	2403	12	0	0
T11	265797	8	0	0
T12	112476	100	0	0
T13	0	28	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	216708	0	0
GntImpliesValid_A	422224717	216708	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	216708	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	3225978	0	0
ReadyAndValidImplyGrant_A	422224717	216708	0	0
ReqAndReadyImplyGrant_A	422224717	216708	0	0
ReqImpliesValid_A	422224717	597053	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	216708	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	216708	0	0
T1	13136	190	0	0
T2	246983	179	0	0
T3	151582	8	0	0
T4	34191	61	0	0
T7	36385	515	0	0
T8	547744	520	0	0
T9	527698	0	0	0
T10	2403	14	0	0
T11	265797	8	0	0
T12	112476	111	0	0
T13	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	216708	0	0
T1	13136	190	0	0
T2	246983	179	0	0
T3	151582	8	0	0
T4	34191	61	0	0
T7	36385	515	0	0
T8	547744	520	0	0
T9	527698	0	0	0
T10	2403	14	0	0
T11	265797	8	0	0
T12	112476	111	0	0
T13	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	216708	0	0
T1	13136	190	0	0
T2	246983	179	0	0
T3	151582	8	0	0
T4	34191	61	0	0
T7	36385	515	0	0
T8	547744	520	0	0
T9	527698	0	0	0
T10	2403	14	0	0
T11	265797	8	0	0
T12	112476	111	0	0
T13	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	3225978	0	0
T1	13136	180	0	0
T2	246983	58939	0	0
T3	151582	40	0	0
T4	34191	468	0	0
T7	36385	509	0	0
T8	547744	1712	0	0
T9	527698	1	0	0
T10	2403	15	0	0
T11	265797	31	0	0
T12	112476	465	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	216708	0	0
T1	13136	190	0	0
T2	246983	179	0	0
T3	151582	8	0	0
T4	34191	61	0	0
T7	36385	515	0	0
T8	547744	520	0	0
T9	527698	0	0	0
T10	2403	14	0	0
T11	265797	8	0	0
T12	112476	111	0	0
T13	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	216708	0	0
T1	13136	190	0	0
T2	246983	179	0	0
T3	151582	8	0	0
T4	34191	61	0	0
T7	36385	515	0	0
T8	547744	520	0	0
T9	527698	0	0	0
T10	2403	14	0	0
T11	265797	8	0	0
T12	112476	111	0	0
T13	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	597053	0	0
T1	13136	201	0	0
T2	246983	1637	0	0
T3	151582	8	0	0
T4	34191	61	0	0
T7	36385	524	0	0
T8	547744	1196	0	0
T9	527698	0	0	0
T10	2403	14	0	0
T11	265797	8	0	0
T12	112476	132	0	0
T13	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	216708	0	0
T1	13136	190	0	0
T2	246983	179	0	0
T3	151582	8	0	0
T4	34191	61	0	0
T7	36385	515	0	0
T8	547744	520	0	0
T9	527698	0	0	0
T10	2403	14	0	0
T11	265797	8	0	0
T12	112476	111	0	0
T13	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	234042	0	0
GntImpliesValid_A	422224717	234042	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	234042	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	3153404	0	0
ReadyAndValidImplyGrant_A	422224717	234042	0	0
ReqAndReadyImplyGrant_A	422224717	234042	0	0
ReqImpliesValid_A	422224717	634600	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	234042	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	234042	0	0
T1	13136	170	0	0
T2	246983	182	0	0
T3	151582	10	0	0
T4	34191	60	0	0
T7	36385	556	0	0
T8	547744	0	0	0
T9	527698	511	0	0
T10	2403	16	0	0
T11	265797	14	0	0
T12	112476	105	0	0
T13	0	24	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	234042	0	0
T1	13136	170	0	0
T2	246983	182	0	0
T3	151582	10	0	0
T4	34191	60	0	0
T7	36385	556	0	0
T8	547744	0	0	0
T9	527698	511	0	0
T10	2403	16	0	0
T11	265797	14	0	0
T12	112476	105	0	0
T13	0	24	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	234042	0	0
T1	13136	170	0	0
T2	246983	182	0	0
T3	151582	10	0	0
T4	34191	60	0	0
T7	36385	556	0	0
T8	547744	0	0	0
T9	527698	511	0	0
T10	2403	16	0	0
T11	265797	14	0	0
T12	112476	105	0	0
T13	0	24	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	3153404	0	0
T1	13136	160	0	0
T2	246983	60162	0	0
T3	151582	29	0	0
T4	34191	443	0	0
T7	36385	543	0	0
T8	547744	1	0	0
T9	527698	1649	0	0
T10	2403	16	0	0
T11	265797	72	0	0
T12	112476	482	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	234042	0	0
T1	13136	170	0	0
T2	246983	182	0	0
T3	151582	10	0	0
T4	34191	60	0	0
T7	36385	556	0	0
T8	547744	0	0	0
T9	527698	511	0	0
T10	2403	16	0	0
T11	265797	14	0	0
T12	112476	105	0	0
T13	0	24	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	234042	0	0
T1	13136	170	0	0
T2	246983	182	0	0
T3	151582	10	0	0
T4	34191	60	0	0
T7	36385	556	0	0
T8	547744	0	0	0
T9	527698	511	0	0
T10	2403	16	0	0
T11	265797	14	0	0
T12	112476	105	0	0
T13	0	24	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	634600	0	0
T1	13136	181	0	0
T2	246983	4480	0	0
T3	151582	23	0	0
T4	34191	62	0	0
T7	36385	572	0	0
T8	547744	0	0	0
T9	527698	1185	0	0
T10	2403	17	0	0
T11	265797	17	0	0
T12	112476	120	0	0
T13	0	24	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	234042	0	0
T1	13136	170	0	0
T2	246983	182	0	0
T3	151582	10	0	0
T4	34191	60	0	0
T7	36385	556	0	0
T8	547744	0	0	0
T9	527698	511	0	0
T10	2403	16	0	0
T11	265797	14	0	0
T12	112476	105	0	0
T13	0	24	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	221248	0	0
GntImpliesValid_A	422224717	221248	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	221248	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	3271561	0	0
ReadyAndValidImplyGrant_A	422224717	221248	0	0
ReqAndReadyImplyGrant_A	422224717	221248	0	0
ReqImpliesValid_A	422224717	641897	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	221248	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	221248	0	0
T1	13136	169	0	0
T2	246983	167	0	0
T3	151582	10	0	0
T4	34191	63	0	0
T7	36385	554	0	0
T8	547744	490	0	0
T9	527698	1482	0	0
T10	2403	13	0	0
T11	265797	12	0	0
T12	112476	112	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	221248	0	0
T1	13136	169	0	0
T2	246983	167	0	0
T3	151582	10	0	0
T4	34191	63	0	0
T7	36385	554	0	0
T8	547744	490	0	0
T9	527698	1482	0	0
T10	2403	13	0	0
T11	265797	12	0	0
T12	112476	112	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	221248	0	0
T1	13136	169	0	0
T2	246983	167	0	0
T3	151582	10	0	0
T4	34191	63	0	0
T7	36385	554	0	0
T8	547744	490	0	0
T9	527698	1482	0	0
T10	2403	13	0	0
T11	265797	12	0	0
T12	112476	112	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	3271561	0	0
T1	13136	160	0	0
T2	246983	55077	0	0
T3	151582	43	0	0
T4	34191	542	0	0
T7	36385	535	0	0
T8	547744	1569	0	0
T9	527698	4827	0	0
T10	2403	14	0	0
T11	265797	49	0	0
T12	112476	486	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	221248	0	0
T1	13136	169	0	0
T2	246983	167	0	0
T3	151582	10	0	0
T4	34191	63	0	0
T7	36385	554	0	0
T8	547744	490	0	0
T9	527698	1482	0	0
T10	2403	13	0	0
T11	265797	12	0	0
T12	112476	112	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	221248	0	0
T1	13136	169	0	0
T2	246983	167	0	0
T3	151582	10	0	0
T4	34191	63	0	0
T7	36385	554	0	0
T8	547744	490	0	0
T9	527698	1482	0	0
T10	2403	13	0	0
T11	265797	12	0	0
T12	112476	112	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	641897	0	0
T1	13136	179	0	0
T2	246983	2282	0	0
T3	151582	10	0	0
T4	34191	90	0	0
T7	36385	576	0	0
T8	547744	1213	0	0
T9	527698	3468	0	0
T10	2403	13	0	0
T11	265797	12	0	0
T12	112476	131	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	221248	0	0
T1	13136	169	0	0
T2	246983	167	0	0
T3	151582	10	0	0
T4	34191	63	0	0
T7	36385	554	0	0
T8	547744	490	0	0
T9	527698	1482	0	0
T10	2403	13	0	0
T11	265797	12	0	0
T12	112476	112	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	216845	0	0
GntImpliesValid_A	422224717	216845	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	216845	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	3259919	0	0
ReadyAndValidImplyGrant_A	422224717	216845	0	0
ReqAndReadyImplyGrant_A	422224717	216845	0	0
ReqImpliesValid_A	422224717	603608	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	216845	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	216845	0	0
T1	13136	170	0	0
T2	246983	187	0	0
T3	151582	2	0	0
T4	34191	62	0	0
T7	36385	565	0	0
T8	547744	0	0	0
T9	527698	566	0	0
T10	2403	11	0	0
T11	265797	11	0	0
T12	112476	99	0	0
T13	0	25	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	216845	0	0
T1	13136	170	0	0
T2	246983	187	0	0
T3	151582	2	0	0
T4	34191	62	0	0
T7	36385	565	0	0
T8	547744	0	0	0
T9	527698	566	0	0
T10	2403	11	0	0
T11	265797	11	0	0
T12	112476	99	0	0
T13	0	25	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	216845	0	0
T1	13136	170	0	0
T2	246983	187	0	0
T3	151582	2	0	0
T4	34191	62	0	0
T7	36385	565	0	0
T8	547744	0	0	0
T9	527698	566	0	0
T10	2403	11	0	0
T11	265797	11	0	0
T12	112476	99	0	0
T13	0	25	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	3259919	0	0
T1	13136	159	0	0
T2	246983	57462	0	0
T3	151582	4	0	0
T4	34191	532	0	0
T7	36385	547	0	0
T8	547744	1	0	0
T9	527698	1924	0	0
T10	2403	12	0	0
T11	265797	44	0	0
T12	112476	443	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	216845	0	0
T1	13136	170	0	0
T2	246983	187	0	0
T3	151582	2	0	0
T4	34191	62	0	0
T7	36385	565	0	0
T8	547744	0	0	0
T9	527698	566	0	0
T10	2403	11	0	0
T11	265797	11	0	0
T12	112476	99	0	0
T13	0	25	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	216845	0	0
T1	13136	170	0	0
T2	246983	187	0	0
T3	151582	2	0	0
T4	34191	62	0	0
T7	36385	565	0	0
T8	547744	0	0	0
T9	527698	566	0	0
T10	2403	11	0	0
T11	265797	11	0	0
T12	112476	99	0	0
T13	0	25	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	603608	0	0
T1	13136	182	0	0
T2	246983	3151	0	0
T3	151582	2	0	0
T4	34191	86	0	0
T7	36385	586	0	0
T8	547744	0	0	0
T9	527698	1282	0	0
T10	2403	11	0	0
T11	265797	11	0	0
T12	112476	114	0	0
T13	0	26	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	216845	0	0
T1	13136	170	0	0
T2	246983	187	0	0
T3	151582	2	0	0
T4	34191	62	0	0
T7	36385	565	0	0
T8	547744	0	0	0
T9	527698	566	0	0
T10	2403	11	0	0
T11	265797	11	0	0
T12	112476	99	0	0
T13	0	25	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	237886	0	0
GntImpliesValid_A	422224717	237886	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	237886	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	3330599	0	0
ReadyAndValidImplyGrant_A	422224717	237886	0	0
ReqAndReadyImplyGrant_A	422224717	237886	0	0
ReqImpliesValid_A	422224717	627071	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	237886	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	237886	0	0
T1	13136	169	0	0
T2	246983	184	0	0
T3	151582	13	0	0
T4	34191	97	0	0
T7	36385	646	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	12	0	0
T11	265797	19	0	0
T12	112476	116	0	0
T13	0	24	0	0
T14	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	237886	0	0
T1	13136	169	0	0
T2	246983	184	0	0
T3	151582	13	0	0
T4	34191	97	0	0
T7	36385	646	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	12	0	0
T11	265797	19	0	0
T12	112476	116	0	0
T13	0	24	0	0
T14	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	237886	0	0
T1	13136	169	0	0
T2	246983	184	0	0
T3	151582	13	0	0
T4	34191	97	0	0
T7	36385	646	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	12	0	0
T11	265797	19	0	0
T12	112476	116	0	0
T13	0	24	0	0
T14	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	3330599	0	0
T1	13136	162	0	0
T2	246983	56703	0	0
T3	151582	36	0	0
T4	34191	711	0	0
T7	36385	628	0	0
T8	547744	1	0	0
T9	527698	1	0	0
T10	2403	12	0	0
T11	265797	67	0	0
T12	112476	478	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	237886	0	0
T1	13136	169	0	0
T2	246983	184	0	0
T3	151582	13	0	0
T4	34191	97	0	0
T7	36385	646	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	12	0	0
T11	265797	19	0	0
T12	112476	116	0	0
T13	0	24	0	0
T14	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	237886	0	0
T1	13136	169	0	0
T2	246983	184	0	0
T3	151582	13	0	0
T4	34191	97	0	0
T7	36385	646	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	12	0	0
T11	265797	19	0	0
T12	112476	116	0	0
T13	0	24	0	0
T14	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	627071	0	0
T1	13136	177	0	0
T2	246983	4496	0	0
T3	151582	30	0	0
T4	34191	142	0	0
T7	36385	667	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	13	0	0
T11	265797	20	0	0
T12	112476	140	0	0
T13	0	24	0	0
T14	0	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	237886	0	0
T1	13136	169	0	0
T2	246983	184	0	0
T3	151582	13	0	0
T4	34191	97	0	0
T7	36385	646	0	0
T8	547744	0	0	0
T9	527698	0	0	0
T10	2403	12	0	0
T11	265797	19	0	0
T12	112476	116	0	0
T13	0	24	0	0
T14	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	213756	0	0
GntImpliesValid_A	422224717	213756	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	213756	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	3215911	0	0
ReadyAndValidImplyGrant_A	422224717	213756	0	0
ReqAndReadyImplyGrant_A	422224717	213756	0	0
ReqImpliesValid_A	422224717	564406	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	213756	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	213756	0	0
T1	13136	165	0	0
T2	246983	184	0	0
T3	151582	7	0	0
T4	34191	47	0	0
T7	36385	545	0	0
T8	547744	512	0	0
T9	527698	0	0	0
T10	2403	15	0	0
T11	265797	13	0	0
T12	112476	120	0	0
T13	0	23	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	213756	0	0
T1	13136	165	0	0
T2	246983	184	0	0
T3	151582	7	0	0
T4	34191	47	0	0
T7	36385	545	0	0
T8	547744	512	0	0
T9	527698	0	0	0
T10	2403	15	0	0
T11	265797	13	0	0
T12	112476	120	0	0
T13	0	23	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	213756	0	0
T1	13136	165	0	0
T2	246983	184	0	0
T3	151582	7	0	0
T4	34191	47	0	0
T7	36385	545	0	0
T8	547744	512	0	0
T9	527698	0	0	0
T10	2403	15	0	0
T11	265797	13	0	0
T12	112476	120	0	0
T13	0	23	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	3215911	0	0
T1	13136	154	0	0
T2	246983	56066	0	0
T3	151582	38	0	0
T4	34191	417	0	0
T7	36385	527	0	0
T8	547744	1746	0	0
T9	527698	1	0	0
T10	2403	15	0	0
T11	265797	54	0	0
T12	112476	485	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	213756	0	0
T1	13136	165	0	0
T2	246983	184	0	0
T3	151582	7	0	0
T4	34191	47	0	0
T7	36385	545	0	0
T8	547744	512	0	0
T9	527698	0	0	0
T10	2403	15	0	0
T11	265797	13	0	0
T12	112476	120	0	0
T13	0	23	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	213756	0	0
T1	13136	165	0	0
T2	246983	184	0	0
T3	151582	7	0	0
T4	34191	47	0	0
T7	36385	545	0	0
T8	547744	512	0	0
T9	527698	0	0	0
T10	2403	15	0	0
T11	265797	13	0	0
T12	112476	120	0	0
T13	0	23	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	564406	0	0
T1	13136	177	0	0
T2	246983	3463	0	0
T3	151582	7	0	0
T4	34191	66	0	0
T7	36385	566	0	0
T8	547744	1187	0	0
T9	527698	0	0	0
T10	2403	16	0	0
T11	265797	19	0	0
T12	112476	154	0	0
T13	0	25	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	213756	0	0
T1	13136	165	0	0
T2	246983	184	0	0
T3	151582	7	0	0
T4	34191	47	0	0
T7	36385	545	0	0
T8	547744	512	0	0
T9	527698	0	0	0
T10	2403	15	0	0
T11	265797	13	0	0
T12	112476	120	0	0
T13	0	23	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	215833	0	0
GntImpliesValid_A	422224717	215833	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	215833	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	3262027	0	0
ReadyAndValidImplyGrant_A	422224717	215833	0	0
ReqAndReadyImplyGrant_A	422224717	215833	0	0
ReqImpliesValid_A	422224717	585794	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	215833	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	215833	0	0
T1	13136	167	0	0
T2	246983	218	0	0
T3	151582	9	0	0
T4	34191	58	0	0
T7	36385	529	0	0
T8	547744	529	0	0
T9	527698	585	0	0
T10	2403	16	0	0
T11	265797	16	0	0
T12	112476	121	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	215833	0	0
T1	13136	167	0	0
T2	246983	218	0	0
T3	151582	9	0	0
T4	34191	58	0	0
T7	36385	529	0	0
T8	547744	529	0	0
T9	527698	585	0	0
T10	2403	16	0	0
T11	265797	16	0	0
T12	112476	121	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	215833	0	0
T1	13136	167	0	0
T2	246983	218	0	0
T3	151582	9	0	0
T4	34191	58	0	0
T7	36385	529	0	0
T8	547744	529	0	0
T9	527698	585	0	0
T10	2403	16	0	0
T11	265797	16	0	0
T12	112476	121	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	3262027	0	0
T1	13136	160	0	0
T2	246983	76596	0	0
T3	151582	40	0	0
T4	34191	416	0	0
T7	36385	520	0	0
T8	547744	1780	0	0
T9	527698	1923	0	0
T10	2403	17	0	0
T11	265797	71	0	0
T12	112476	479	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	215833	0	0
T1	13136	167	0	0
T2	246983	218	0	0
T3	151582	9	0	0
T4	34191	58	0	0
T7	36385	529	0	0
T8	547744	529	0	0
T9	527698	585	0	0
T10	2403	16	0	0
T11	265797	16	0	0
T12	112476	121	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	215833	0	0
T1	13136	167	0	0
T2	246983	218	0	0
T3	151582	9	0	0
T4	34191	58	0	0
T7	36385	529	0	0
T8	547744	529	0	0
T9	527698	585	0	0
T10	2403	16	0	0
T11	265797	16	0	0
T12	112476	121	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	585794	0	0
T1	13136	175	0	0
T2	246983	3190	0	0
T3	151582	9	0	0
T4	34191	124	0	0
T7	36385	541	0	0
T8	547744	1104	0	0
T9	527698	1254	0	0
T10	2403	16	0	0
T11	265797	16	0	0
T12	112476	159	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	215833	0	0
T1	13136	167	0	0
T2	246983	218	0	0
T3	151582	9	0	0
T4	34191	58	0	0
T7	36385	529	0	0
T8	547744	529	0	0
T9	527698	585	0	0
T10	2403	16	0	0
T11	265797	16	0	0
T12	112476	121	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	212392	0	0
GntImpliesValid_A	422224717	212392	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	212392	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	3166513	0	0
ReadyAndValidImplyGrant_A	422224717	212392	0	0
ReqAndReadyImplyGrant_A	422224717	212392	0	0
ReqImpliesValid_A	422224717	594155	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	212392	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	212392	0	0
T1	13136	172	0	0
T2	246983	180	0	0
T3	151582	5	0	0
T4	34191	60	0	0
T7	36385	538	0	0
T8	547744	0	0	0
T9	527698	467	0	0
T10	2403	9	0	0
T11	265797	14	0	0
T12	112476	139	0	0
T13	0	21	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	212392	0	0
T1	13136	172	0	0
T2	246983	180	0	0
T3	151582	5	0	0
T4	34191	60	0	0
T7	36385	538	0	0
T8	547744	0	0	0
T9	527698	467	0	0
T10	2403	9	0	0
T11	265797	14	0	0
T12	112476	139	0	0
T13	0	21	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	212392	0	0
T1	13136	172	0	0
T2	246983	180	0	0
T3	151582	5	0	0
T4	34191	60	0	0
T7	36385	538	0	0
T8	547744	0	0	0
T9	527698	467	0	0
T10	2403	9	0	0
T11	265797	14	0	0
T12	112476	139	0	0
T13	0	21	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	3166513	0	0
T1	13136	169	0	0
T2	246983	56160	0	0
T3	151582	15	0	0
T4	34191	484	0	0
T7	36385	528	0	0
T8	547744	1	0	0
T9	527698	1574	0	0
T10	2403	10	0	0
T11	265797	65	0	0
T12	112476	586	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	212392	0	0
T1	13136	172	0	0
T2	246983	180	0	0
T3	151582	5	0	0
T4	34191	60	0	0
T7	36385	538	0	0
T8	547744	0	0	0
T9	527698	467	0	0
T10	2403	9	0	0
T11	265797	14	0	0
T12	112476	139	0	0
T13	0	21	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	212392	0	0
T1	13136	172	0	0
T2	246983	180	0	0
T3	151582	5	0	0
T4	34191	60	0	0
T7	36385	538	0	0
T8	547744	0	0	0
T9	527698	467	0	0
T10	2403	9	0	0
T11	265797	14	0	0
T12	112476	139	0	0
T13	0	21	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	594155	0	0
T1	13136	176	0	0
T2	246983	4215	0	0
T3	151582	11	0	0
T4	34191	79	0	0
T7	36385	551	0	0
T8	547744	0	0	0
T9	527698	1126	0	0
T10	2403	9	0	0
T11	265797	14	0	0
T12	112476	172	0	0
T13	0	22	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	212392	0	0
T1	13136	172	0	0
T2	246983	180	0	0
T3	151582	5	0	0
T4	34191	60	0	0
T7	36385	538	0	0
T8	547744	0	0	0
T9	527698	467	0	0
T10	2403	9	0	0
T11	265797	14	0	0
T12	112476	139	0	0
T13	0	21	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	224278	0	0
GntImpliesValid_A	422224717	224278	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	224278	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	3297660	0	0
ReadyAndValidImplyGrant_A	422224717	224278	0	0
ReqAndReadyImplyGrant_A	422224717	224278	0	0
ReqImpliesValid_A	422224717	624826	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	224278	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	224278	0	0
T1	13136	179	0	0
T2	246983	185	0	0
T3	151582	6	0	0
T4	34191	36	0	0
T7	36385	537	0	0
T8	547744	0	0	0
T9	527698	511	0	0
T10	2403	14	0	0
T11	265797	13	0	0
T12	112476	95	0	0
T13	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	224278	0	0
T1	13136	179	0	0
T2	246983	185	0	0
T3	151582	6	0	0
T4	34191	36	0	0
T7	36385	537	0	0
T8	547744	0	0	0
T9	527698	511	0	0
T10	2403	14	0	0
T11	265797	13	0	0
T12	112476	95	0	0
T13	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	224278	0	0
T1	13136	179	0	0
T2	246983	185	0	0
T3	151582	6	0	0
T4	34191	36	0	0
T7	36385	537	0	0
T8	547744	0	0	0
T9	527698	511	0	0
T10	2403	14	0	0
T11	265797	13	0	0
T12	112476	95	0	0
T13	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	3297660	0	0
T1	13136	168	0	0
T2	246983	56926	0	0
T3	151582	36	0	0
T4	34191	234	0	0
T7	36385	516	0	0
T8	547744	1	0	0
T9	527698	1675	0	0
T10	2403	15	0	0
T11	265797	47	0	0
T12	112476	390	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	224278	0	0
T1	13136	179	0	0
T2	246983	185	0	0
T3	151582	6	0	0
T4	34191	36	0	0
T7	36385	537	0	0
T8	547744	0	0	0
T9	527698	511	0	0
T10	2403	14	0	0
T11	265797	13	0	0
T12	112476	95	0	0
T13	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	224278	0	0
T1	13136	179	0	0
T2	246983	185	0	0
T3	151582	6	0	0
T4	34191	36	0	0
T7	36385	537	0	0
T8	547744	0	0	0
T9	527698	511	0	0
T10	2403	14	0	0
T11	265797	13	0	0
T12	112476	95	0	0
T13	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	624826	0	0
T1	13136	191	0	0
T2	246983	5487	0	0
T3	151582	6	0	0
T4	34191	38	0	0
T7	36385	561	0	0
T8	547744	0	0	0
T9	527698	1226	0	0
T10	2403	14	0	0
T11	265797	15	0	0
T12	112476	124	0	0
T13	0	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	224278	0	0
T1	13136	179	0	0
T2	246983	185	0	0
T3	151582	6	0	0
T4	34191	36	0	0
T7	36385	537	0	0
T8	547744	0	0	0
T9	527698	511	0	0
T10	2403	14	0	0
T11	265797	13	0	0
T12	112476	95	0	0
T13	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	223349	0	0
GntImpliesValid_A	422224717	223349	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	223349	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	3256305	0	0
ReadyAndValidImplyGrant_A	422224717	223349	0	0
ReqAndReadyImplyGrant_A	422224717	223349	0	0
ReqImpliesValid_A	422224717	617680	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	0	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	223349	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	223349	0	0
T1	13136	168	0	0
T2	246983	148	0	0
T3	151582	3	0	0
T4	34191	57	0	0
T7	36385	514	0	0
T8	547744	0	0	0
T9	527698	513	0	0
T10	2403	5	0	0
T11	265797	13	0	0
T12	112476	96	0	0
T13	0	30	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	223349	0	0
T1	13136	168	0	0
T2	246983	148	0	0
T3	151582	3	0	0
T4	34191	57	0	0
T7	36385	514	0	0
T8	547744	0	0	0
T9	527698	513	0	0
T10	2403	5	0	0
T11	265797	13	0	0
T12	112476	96	0	0
T13	0	30	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	223349	0	0
T1	13136	168	0	0
T2	246983	148	0	0
T3	151582	3	0	0
T4	34191	57	0	0
T7	36385	514	0	0
T8	547744	0	0	0
T9	527698	513	0	0
T10	2403	5	0	0
T11	265797	13	0	0
T12	112476	96	0	0
T13	0	30	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	3256305	0	0
T1	13136	163	0	0
T2	246983	44925	0	0
T3	151582	15	0	0
T4	34191	381	0	0
T7	36385	502	0	0
T8	547744	1	0	0
T9	527698	1697	0	0
T10	2403	6	0	0
T11	265797	43	0	0
T12	112476	387	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	223349	0	0
T1	13136	168	0	0
T2	246983	148	0	0
T3	151582	3	0	0
T4	34191	57	0	0
T7	36385	514	0	0
T8	547744	0	0	0
T9	527698	513	0	0
T10	2403	5	0	0
T11	265797	13	0	0
T12	112476	96	0	0
T13	0	30	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	223349	0	0
T1	13136	168	0	0
T2	246983	148	0	0
T3	151582	3	0	0
T4	34191	57	0	0
T7	36385	514	0	0
T8	547744	0	0	0
T9	527698	513	0	0
T10	2403	5	0	0
T11	265797	13	0	0
T12	112476	96	0	0
T13	0	30	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	617680	0	0
T1	13136	174	0	0
T2	246983	2791	0	0
T3	151582	3	0	0
T4	34191	57	0	0
T7	36385	529	0	0
T8	547744	0	0	0
T9	527698	1149	0	0
T10	2403	5	0	0
T11	265797	21	0	0
T12	112476	108	0	0
T13	0	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	223349	0	0
T1	13136	168	0	0
T2	246983	148	0	0
T3	151582	3	0	0
T4	34191	57	0	0
T7	36385	514	0	0
T8	547744	0	0	0
T9	527698	513	0	0
T10	2403	5	0	0
T11	265797	13	0	0
T12	112476	96	0	0
T13	0	30	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	899898	0	0
GntImpliesValid_A	422224717	899898	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	899898	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	12205907	0	0
ReadyAndValidImplyGrant_A	422224717	899898	0	0
ReqAndReadyImplyGrant_A	422224717	899898	0	0
ReqImpliesValid_A	422224717	2395668	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	18469	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	899898	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	899898	0	0
T1	13136	667	0	0
T2	246983	749	0	0
T3	151582	35	0	0
T4	34191	203	0	0
T7	36385	2111	0	0
T8	547744	551	0	0
T9	527698	773	0	0
T10	2403	58	0	0
T11	265797	36	0	0
T12	112476	429	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	899898	0	0
T1	13136	667	0	0
T2	246983	749	0	0
T3	151582	35	0	0
T4	34191	203	0	0
T7	36385	2111	0	0
T8	547744	551	0	0
T9	527698	773	0	0
T10	2403	58	0	0
T11	265797	36	0	0
T12	112476	429	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	899898	0	0
T1	13136	667	0	0
T2	246983	749	0	0
T3	151582	35	0	0
T4	34191	203	0	0
T7	36385	2111	0	0
T8	547744	551	0	0
T9	527698	773	0	0
T10	2403	58	0	0
T11	265797	36	0	0
T12	112476	429	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	12205907	0	0
T1	13136	1	0	0
T2	246983	223155	0	0
T3	151582	97	0	0
T4	34191	1208	0	0
T7	36385	3	0	0
T8	547744	1756	0	0
T9	527698	2555	0	0
T10	2403	1	0	0
T11	265797	87	0	0
T12	112476	1267	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	899898	0	0
T1	13136	667	0	0
T2	246983	749	0	0
T3	151582	35	0	0
T4	34191	203	0	0
T7	36385	2111	0	0
T8	547744	551	0	0
T9	527698	773	0	0
T10	2403	58	0	0
T11	265797	36	0	0
T12	112476	429	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	899898	0	0
T1	13136	667	0	0
T2	246983	749	0	0
T3	151582	35	0	0
T4	34191	203	0	0
T7	36385	2111	0	0
T8	547744	551	0	0
T9	527698	773	0	0
T10	2403	58	0	0
T11	265797	36	0	0
T12	112476	429	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	2395668	0	0
T1	13136	667	0	0
T2	246983	22646	0	0
T3	151582	48	0	0
T4	34191	287	0	0
T7	36385	2111	0	0
T8	547744	745	0	0
T9	527698	1009	0	0
T10	2403	58	0	0
T11	265797	36	0	0
T12	112476	582	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	18469	0	900
T1	13136	7	0	1
T2	246983	0	0	1
T3	151582	0	0	1
T4	34191	0	0	1
T7	36385	40	0	1
T8	547744	0	0	1
T9	527698	0	0	1
T10	2403	0	0	1
T11	265797	0	0	1
T12	112476	0	0	1
T13	0	4	0	0
T16	0	5	0	0
T17	0	10	0	0
T19	0	17	0	0
T20	0	3	0	0
T21	0	6	0	0
T22	0	4	0	0
T23	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	899898	0	0
T1	13136	667	0	0
T2	246983	749	0	0
T3	151582	35	0	0
T4	34191	203	0	0
T7	36385	2111	0	0
T8	547744	551	0	0
T9	527698	773	0	0
T10	2403	58	0	0
T11	265797	36	0	0
T12	112476	429	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422224717	422094791	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422224717	879395	0	0
GntImpliesValid_A	422224717	879395	0	0
GrantKnown_A	422224717	422094791	0	0
IdxKnown_A	422224717	422094791	0	0
IndexIsCorrect_A	422224717	879395	0	0
LockArbDecision_A	422224717	0	0	0
NoReadyValidNoGrant_A	422224717	354909478	0	0
ReadyAndValidImplyGrant_A	422224717	879395	0	0
ReqAndReadyImplyGrant_A	422224717	879395	0	0
ReqImpliesValid_A	422224717	14386611	0	0
ReqStaysHighUntilGranted0_M	422224717	0	0	0
RoundRobin_A	422224717	23258	0	900
ValidKnown_A	422224717	422094791	0	0
gen_data_port_assertion.DataFlow_A	422224717	879395	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	879395	0	0
T1	13136	677	0	0
T2	246983	698	0	0
T3	151582	32	0	0
T4	34191	207	0	0
T7	36385	2169	0	0
T8	547744	2884	0	0
T9	527698	1461	0	0
T10	2403	46	0	0
T11	265797	54	0	0
T12	112476	421	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	879395	0	0
T1	13136	677	0	0
T2	246983	698	0	0
T3	151582	32	0	0
T4	34191	207	0	0
T7	36385	2169	0	0
T8	547744	2884	0	0
T9	527698	1461	0	0
T10	2403	46	0	0
T11	265797	54	0	0
T12	112476	421	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	879395	0	0
T1	13136	677	0	0
T2	246983	698	0	0
T3	151582	32	0	0
T4	34191	207	0	0
T7	36385	2169	0	0
T8	547744	2884	0	0
T9	527698	1461	0	0
T10	2403	46	0	0
T11	265797	54	0	0
T12	112476	421	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	354909478	0	0
T1	13136	1	0	0
T2	246983	221078	0	0
T3	151582	126140	0	0
T4	34191	29553	0	0
T7	36385	1	0	0
T8	547744	455035	0	0
T9	527698	439253	0	0
T10	2403	1	0	0
T11	265797	221293	0	0
T12	112476	936274	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	879395	0	0
T1	13136	677	0	0
T2	246983	698	0	0
T3	151582	32	0	0
T4	34191	207	0	0
T7	36385	2169	0	0
T8	547744	2884	0	0
T9	527698	1461	0	0
T10	2403	46	0	0
T11	265797	54	0	0
T12	112476	421	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	879395	0	0
T1	13136	677	0	0
T2	246983	698	0	0
T3	151582	32	0	0
T4	34191	207	0	0
T7	36385	2169	0	0
T8	547744	2884	0	0
T9	527698	1461	0	0
T10	2403	46	0	0
T11	265797	54	0	0
T12	112476	421	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	14386611	0	0
T1	13136	677	0	0
T2	246983	254733	0	0
T3	151582	119	0	0
T4	34191	1696	0	0
T7	36385	2169	0	0
T8	547744	13140	0	0
T9	527698	6682	0	0
T10	2403	46	0	0
T11	265797	234	0	0
T12	112476	1962	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	23258	0	900
T1	13136	12	0	1
T2	246983	0	0	1
T3	151582	0	0	1
T4	34191	0	0	1
T7	36385	47	0	1
T8	547744	34	0	1
T9	527698	9	0	1
T10	2403	0	0	1
T11	265797	0	0	1
T12	112476	0	0	1
T13	0	1	0	0
T15	0	428	0	0
T16	0	405	0	0
T17	0	13	0	0
T18	0	2	0	0
T19	0	16	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	422094791	0	0
T1	13136	13085	0	0
T2	246983	246980	0	0
T3	151582	151571	0	0
T4	34191	34148	0	0
T7	36385	36200	0	0
T8	547744	547740	0	0
T9	527698	527694	0	0
T10	2403	2341	0	0
T11	265797	265717	0	0
T12	112476	112471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422224717	879395	0	0
T1	13136	677	0	0
T2	246983	698	0	0
T3	151582	32	0	0
T4	34191	207	0	0
T7	36385	2169	0	0
T8	547744	2884	0	0
T9	527698	1461	0	0
T10	2403	46	0	0
T11	265797	54	0	0
T12	112476	421	0	0