Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1583419	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

251315

1

T1

441

T2

31

T3

158

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	624072	1			T1	991		T2	56		T3	360
values[0x0]	588302	1			T1	1064		T2	68		T3	334
values[0x1]	622360	1			T1	1014		T2	71		T3	391

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1222834	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

611900

1

T1

1013

T2

67

T3

358

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28831	1			T1	61		T3	2		T4	241
valid_sources[0x01]	28390	1			T1	53		T3	15		T4	301
valid_sources[0x02]	28093	1			T1	43		T3	45		T4	198
valid_sources[0x03]	28287	1			T1	47		T3	33		T4	212
valid_sources[0x04]	29176	1			T1	47		T3	16		T4	211
valid_sources[0x05]	29271	1			T1	45		T2	6		T3	10
valid_sources[0x06]	29448	1			T1	43		T3	13		T4	207
valid_sources[0x07]	28934	1			T1	54		T3	15		T4	219
valid_sources[0x08]	28861	1			T1	55		T3	22		T4	151
valid_sources[0x09]	28032	1			T1	55		T3	24		T4	206
valid_sources[0x0a]	29025	1			T1	41		T3	17		T4	223
valid_sources[0x0b]	29266	1			T1	53		T3	12		T4	183
valid_sources[0x0c]	27219	1			T1	47		T3	15		T4	231
valid_sources[0x0d]	29107	1			T1	59		T3	19		T4	216
valid_sources[0x0e]	28485	1			T1	51		T3	6		T4	213
valid_sources[0x0f]	28012	1			T1	55		T3	10		T4	192
valid_sources[0x10]	28595	1			T1	43		T3	10		T4	183
valid_sources[0x11]	29475	1			T1	46		T3	18		T4	176
valid_sources[0x12]	27619	1			T1	51		T3	14		T4	214
valid_sources[0x13]	28043	1			T1	41		T3	21		T4	192
valid_sources[0x14]	28369	1			T1	43		T2	9		T3	8
valid_sources[0x15]	28306	1			T1	49		T3	32		T4	211
valid_sources[0x16]	28508	1			T1	56		T3	8		T4	148
valid_sources[0x17]	28195	1			T1	53		T3	29		T4	228
valid_sources[0x18]	28065	1			T1	36		T3	19		T4	316
valid_sources[0x19]	28461	1			T1	48		T3	10		T4	181
valid_sources[0x1a]	29747	1			T1	47		T2	15		T3	5
valid_sources[0x1b]	28809	1			T1	55		T2	9		T3	10
valid_sources[0x1c]	27850	1			T1	41		T3	26		T4	173
valid_sources[0x1d]	28463	1			T1	47		T3	15		T4	230
valid_sources[0x1e]	28473	1			T1	37		T3	16		T4	162
valid_sources[0x1f]	28281	1			T1	56		T3	17		T4	203
valid_sources[0x20]	29199	1			T1	44		T3	8		T4	255

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26439

1

T1

45

T2

4

T3

13

values[0x0]

all_enables

biggest_size

198579

1

T1

349

T2

25

T3

123

values[0x1]

all_enables

biggest_size

26297

1

T1

47

T2

2

T3

22

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1594104	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

259804

1

T1

392

T2

21

T3

250

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	635235	1			T1	959		T2	62		T3	596
values[0x0]	585123	1			T1	949		T2	54		T3	539
values[0x1]	633550	1			T1	963		T2	58		T3	603

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1224037	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

629871

1

T1

954

T2

52

T3

589

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29252	1			T1	55		T3	37		T4	232
valid_sources[0x01]	29450	1			T1	50		T2	1		T3	31
valid_sources[0x02]	29017	1			T1	46		T2	3		T3	57
valid_sources[0x03]	28967	1			T1	41		T2	10		T3	43
valid_sources[0x04]	28745	1			T1	56		T2	5		T3	23
valid_sources[0x05]	29340	1			T1	41		T3	30		T4	203
valid_sources[0x06]	29299	1			T1	27		T3	28		T4	158
valid_sources[0x07]	29286	1			T1	50		T3	25		T4	227
valid_sources[0x08]	28998	1			T1	42		T2	3		T3	17
valid_sources[0x09]	29235	1			T1	49		T3	35		T4	194
valid_sources[0x0a]	28608	1			T1	34		T2	1		T3	24
valid_sources[0x0b]	29739	1			T1	42		T3	22		T4	242
valid_sources[0x0c]	29425	1			T1	42		T2	7		T3	27
valid_sources[0x0d]	28780	1			T1	32		T2	1		T3	14
valid_sources[0x0e]	27937	1			T1	38		T3	14		T4	187
valid_sources[0x0f]	28515	1			T1	38		T2	2		T3	15
valid_sources[0x10]	29491	1			T1	32		T2	4		T3	23
valid_sources[0x11]	29023	1			T1	47		T2	9		T3	29
valid_sources[0x12]	27943	1			T1	49		T2	4		T3	30
valid_sources[0x13]	28865	1			T1	60		T3	23		T4	140
valid_sources[0x14]	29607	1			T1	32		T2	1		T3	25
valid_sources[0x15]	28576	1			T1	46		T2	1		T3	51
valid_sources[0x16]	28634	1			T1	50		T3	22		T4	180
valid_sources[0x17]	28470	1			T1	42		T2	3		T3	18
valid_sources[0x18]	29085	1			T1	42		T3	31		T4	293
valid_sources[0x19]	28718	1			T1	40		T3	24		T4	241
valid_sources[0x1a]	28747	1			T1	46		T3	31		T4	181
valid_sources[0x1b]	28568	1			T1	53		T2	5		T3	28
valid_sources[0x1c]	28573	1			T1	50		T3	35		T4	128
valid_sources[0x1d]	29088	1			T1	47		T2	15		T3	20
valid_sources[0x1e]	29406	1			T1	48		T3	17		T4	199
valid_sources[0x1f]	29520	1			T1	37		T3	29		T4	267
valid_sources[0x20]	29402	1			T1	40		T2	3		T3	34

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27268

1

T1

43

T2

4

T3

28

values[0x0]

all_enables

biggest_size

205045

1

T1

313

T2

14

T3

193

values[0x1]

all_enables

biggest_size

27491

1

T1

36

T2

3

T3

29

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1596650	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

253974

1

T1

408

T2

18

T3

212

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	628257	1			T1	971		T2	33		T3	522
values[0x0]	594067	1			T1	1032		T2	43		T3	530
values[0x1]	628300	1			T1	1037		T2	40		T3	508

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1234554	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

616070

1

T1

976

T2

35

T3

535

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28538	1			T1	41		T3	25		T4	198
valid_sources[0x01]	28227	1			T1	44		T3	22		T4	253
valid_sources[0x02]	28375	1			T1	50		T2	2		T3	28
valid_sources[0x03]	29228	1			T1	46		T3	27		T4	177
valid_sources[0x04]	28967	1			T1	45		T3	18		T4	255
valid_sources[0x05]	28625	1			T1	46		T3	36		T4	228
valid_sources[0x06]	29001	1			T1	61		T3	15		T4	191
valid_sources[0x07]	29659	1			T1	49		T3	21		T4	226
valid_sources[0x08]	28819	1			T1	47		T2	30		T3	15
valid_sources[0x09]	28105	1			T1	48		T3	32		T4	194
valid_sources[0x0a]	28552	1			T1	48		T3	26		T4	239
valid_sources[0x0b]	29039	1			T1	37		T3	16		T4	174
valid_sources[0x0c]	28855	1			T1	41		T3	16		T4	174
valid_sources[0x0d]	28731	1			T1	46		T2	1		T3	26
valid_sources[0x0e]	29383	1			T1	45		T3	29		T4	200
valid_sources[0x0f]	29081	1			T1	42		T3	19		T4	204
valid_sources[0x10]	28864	1			T1	49		T3	22		T4	179
valid_sources[0x11]	28795	1			T1	53		T3	34		T4	193
valid_sources[0x12]	28699	1			T1	37		T3	21		T4	187
valid_sources[0x13]	27921	1			T1	49		T3	12		T4	159
valid_sources[0x14]	28743	1			T1	37		T3	23		T4	271
valid_sources[0x15]	28851	1			T1	47		T3	39		T4	181
valid_sources[0x16]	29496	1			T1	42		T3	23		T4	195
valid_sources[0x17]	28801	1			T1	51		T3	30		T4	260
valid_sources[0x18]	28675	1			T1	55		T3	18		T4	296
valid_sources[0x19]	29878	1			T1	43		T2	2		T3	19
valid_sources[0x1a]	29309	1			T1	45		T3	25		T4	180
valid_sources[0x1b]	28441	1			T1	57		T3	30		T4	213
valid_sources[0x1c]	28864	1			T1	44		T2	2		T3	28
valid_sources[0x1d]	29104	1			T1	50		T3	34		T4	240
valid_sources[0x1e]	28400	1			T1	48		T3	21		T4	163
valid_sources[0x1f]	28912	1			T1	45		T3	24		T4	253
valid_sources[0x20]	28866	1			T1	39		T3	19		T4	248

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26721

1

T1

40

T3

19

T4

168

values[0x0]

all_enables

biggest_size

200535

1

T1

325

T2

16

T3

178

values[0x1]

all_enables

biggest_size

26718

1

T1

43

T2

2

T3

15