Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8222973	0	0
GntImpliesValid_A	2147483647	8222973	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8222973	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	439857615	0	0
ReadyAndValidImplyGrant_A	2147483647	8222973	0	0
ReqAndReadyImplyGrant_A	2147483647	8222973	0	0
ReqImpliesValid_A	2147483647	32822417	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	55142	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8222973	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10994376	10994304	0	0
T2	11991888	11990616	0	0
T3	960672	925248	0	0
T4	1816992	1814352	0	0
T7	1582128	1581720	0	0
T8	362688	362112	0	0
T9	54120	53568	0	0
T10	144192	143064	0	0
T11	5548056	5547816	0	0
T12	12924360	12922344	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8222973	0	0
T1	4122891	8979	0	0
T2	11991888	485	0	0
T3	960672	3989	0	0
T4	1816992	36756	0	0
T7	1582128	7382	0	0
T8	362688	7977	0	0
T9	54120	525	0	0
T10	144192	3031	0	0
T11	5548056	422	0	0
T12	12924360	449	0	0
T13	4590405	12578	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8222973	0	0
T1	4122891	8979	0	0
T2	11991888	485	0	0
T3	960672	3989	0	0
T4	1816992	36756	0	0
T7	1582128	7382	0	0
T8	362688	7977	0	0
T9	54120	525	0	0
T10	144192	3031	0	0
T11	5548056	422	0	0
T12	12924360	449	0	0
T13	4590405	12578	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10994376	10994304	0	0
T2	11991888	11990616	0	0
T3	960672	925248	0	0
T4	1816992	1814352	0	0
T7	1582128	1581720	0	0
T8	362688	362112	0	0
T9	54120	53568	0	0
T10	144192	143064	0	0
T11	5548056	5547816	0	0
T12	12924360	12922344	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10994376	10994304	0	0
T2	11991888	11990616	0	0
T3	960672	925248	0	0
T4	1816992	1814352	0	0
T7	1582128	1581720	0	0
T8	362688	362112	0	0
T9	54120	53568	0	0
T10	144192	143064	0	0
T11	5548056	5547816	0	0
T12	12924360	12922344	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8222973	0	0
T1	4122891	8979	0	0
T2	11991888	485	0	0
T3	960672	3989	0	0
T4	1816992	36756	0	0
T7	1582128	7382	0	0
T8	362688	7977	0	0
T9	54120	525	0	0
T10	144192	3031	0	0
T11	5548056	422	0	0
T12	12924360	449	0	0
T13	4590405	12578	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	439857615	0	0
T1	10078178	410642	0	0
T2	11991888	658751	0	0
T3	960672	56579	0	0
T4	1816992	43749	0	0
T7	1582128	96978	0	0
T8	362688	10903	0	0
T9	54120	654	0	0
T10	144192	4075	0	0
T11	5548056	194172	0	0
T12	12924360	667340	0	0
T13	612054	11567	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8222973	0	0
T1	4122891	8979	0	0
T2	11991888	485	0	0
T3	960672	3989	0	0
T4	1816992	36756	0	0
T7	1582128	7382	0	0
T8	362688	7977	0	0
T9	54120	525	0	0
T10	144192	3031	0	0
T11	5548056	422	0	0
T12	12924360	449	0	0
T13	4590405	12578	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8222973	0	0
T1	4122891	8979	0	0
T2	11991888	485	0	0
T3	960672	3989	0	0
T4	1816992	36756	0	0
T7	1582128	7382	0	0
T8	362688	7977	0	0
T9	54120	525	0	0
T10	144192	3031	0	0
T11	5548056	422	0	0
T12	12924360	449	0	0
T13	4590405	12578	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32822417	0	0
T1	4122891	27716	0	0
T2	11991888	23964	0	0
T3	960672	15592	0	0
T4	1816992	54809	0	0
T7	1582128	16860	0	0
T8	362688	9545	0	0
T9	54120	579	0	0
T10	144192	3712	0	0
T11	5548056	717	0	0
T12	12924360	28439	0	0
T13	4590405	44493	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	55142	0	21600
T1	916198	27	0	2
T2	999324	0	0	2
T3	80056	0	0	2
T4	151416	51	0	2
T5	0	24	0	0
T7	131844	2	0	2
T8	30224	19	0	2
T9	4510	0	0	2
T10	12016	12	0	2
T11	462338	0	0	2
T12	1077030	0	0	2
T13	0	9	0	0
T14	0	3	0	0
T15	0	3	0	0
T16	0	5	0	0
T17	0	12	0	0
T18	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10994376	10994304	0	0
T2	11991888	11990616	0	0
T3	960672	925248	0	0
T4	1816992	1814352	0	0
T7	1582128	1581720	0	0
T8	362688	362112	0	0
T9	54120	53568	0	0
T10	144192	143064	0	0
T11	5548056	5547816	0	0
T12	12924360	12922344	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8222973	0	0
T1	4122891	8979	0	0
T2	11991888	485	0	0
T3	960672	3989	0	0
T4	1816992	36756	0	0
T7	1582128	7382	0	0
T8	362688	7977	0	0
T9	54120	525	0	0
T10	144192	3031	0	0
T11	5548056	422	0	0
T12	12924360	449	0	0
T13	4590405	12578	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	912226	0	0
GntImpliesValid_A	408724497	912226	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	912226	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	11204177	0	0
ReadyAndValidImplyGrant_A	408724497	912226	0	0
ReqAndReadyImplyGrant_A	408724497	912226	0	0
ReqImpliesValid_A	408724497	2437150	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	912226	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	912226	0	0
T1	458099	1193	0	0
T2	499662	62	0	0
T3	40028	444	0	0
T4	75708	4945	0	0
T7	65922	828	0	0
T8	15112	863	0	0
T9	2255	53	0	0
T10	6008	331	0	0
T11	231169	42	0	0
T12	538515	49	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	912226	0	0
T1	458099	1193	0	0
T2	499662	62	0	0
T3	40028	444	0	0
T4	75708	4945	0	0
T7	65922	828	0	0
T8	15112	863	0	0
T9	2255	53	0	0
T10	6008	331	0	0
T11	231169	42	0	0
T12	538515	49	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	912226	0	0
T1	458099	1193	0	0
T2	499662	62	0	0
T3	40028	444	0	0
T4	75708	4945	0	0
T7	65922	828	0	0
T8	15112	863	0	0
T9	2255	53	0	0
T10	6008	331	0	0
T11	231169	42	0	0
T12	538515	49	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	11204177	0	0
T1	458099	4135	0	0
T2	499662	19346	0	0
T3	40028	3419	0	0
T4	75708	2869	0	0
T7	65922	5384	0	0
T8	15112	635	0	0
T9	2255	43	0	0
T10	6008	254	0	0
T11	231169	219	0	0
T12	538515	15712	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	912226	0	0
T1	458099	1193	0	0
T2	499662	62	0	0
T3	40028	444	0	0
T4	75708	4945	0	0
T7	65922	828	0	0
T8	15112	863	0	0
T9	2255	53	0	0
T10	6008	331	0	0
T11	231169	42	0	0
T12	538515	49	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	912226	0	0
T1	458099	1193	0	0
T2	499662	62	0	0
T3	40028	444	0	0
T4	75708	4945	0	0
T7	65922	828	0	0
T8	15112	863	0	0
T9	2255	53	0	0
T10	6008	331	0	0
T11	231169	42	0	0
T12	538515	49	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	2437150	0	0
T1	458099	2479	0	0
T2	499662	2939	0	0
T3	40028	642	0	0
T4	75708	7023	0	0
T7	65922	1611	0	0
T8	15112	1092	0	0
T9	2255	64	0	0
T10	6008	409	0	0
T11	231169	66	0	0
T12	538515	435	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	912226	0	0
T1	458099	1193	0	0
T2	499662	62	0	0
T3	40028	444	0	0
T4	75708	4945	0	0
T7	65922	828	0	0
T8	15112	863	0	0
T9	2255	53	0	0
T10	6008	331	0	0
T11	231169	42	0	0
T12	538515	49	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	920428	0	0
GntImpliesValid_A	408724497	920428	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	920428	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	11129713	0	0
ReadyAndValidImplyGrant_A	408724497	920428	0	0
ReqAndReadyImplyGrant_A	408724497	920428	0	0
ReqImpliesValid_A	408724497	2390081	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	920428	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	920428	0	0
T1	458099	1078	0	0
T2	499662	56	0	0
T3	40028	429	0	0
T4	75708	3487	0	0
T7	65922	872	0	0
T8	15112	904	0	0
T9	2255	62	0	0
T10	6008	342	0	0
T11	231169	48	0	0
T12	538515	57	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	920428	0	0
T1	458099	1078	0	0
T2	499662	56	0	0
T3	40028	429	0	0
T4	75708	3487	0	0
T7	65922	872	0	0
T8	15112	904	0	0
T9	2255	62	0	0
T10	6008	342	0	0
T11	231169	48	0	0
T12	538515	57	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	920428	0	0
T1	458099	1078	0	0
T2	499662	56	0	0
T3	40028	429	0	0
T4	75708	3487	0	0
T7	65922	872	0	0
T8	15112	904	0	0
T9	2255	62	0	0
T10	6008	342	0	0
T11	231169	48	0	0
T12	538515	57	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	11129713	0	0
T1	458099	3769	0	0
T2	499662	21953	0	0
T3	40028	3185	0	0
T4	75708	2772	0	0
T7	65922	5730	0	0
T8	15112	644	0	0
T9	2255	50	0	0
T10	6008	252	0	0
T11	231169	183	0	0
T12	538515	23640	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	920428	0	0
T1	458099	1078	0	0
T2	499662	56	0	0
T3	40028	429	0	0
T4	75708	3487	0	0
T7	65922	872	0	0
T8	15112	904	0	0
T9	2255	62	0	0
T10	6008	342	0	0
T11	231169	48	0	0
T12	538515	57	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	920428	0	0
T1	458099	1078	0	0
T2	499662	56	0	0
T3	40028	429	0	0
T4	75708	3487	0	0
T7	65922	872	0	0
T8	15112	904	0	0
T9	2255	62	0	0
T10	6008	342	0	0
T11	231169	48	0	0
T12	538515	57	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	2390081	0	0
T1	458099	2318	0	0
T2	499662	715	0	0
T3	40028	604	0	0
T4	75708	4204	0	0
T7	65922	1653	0	0
T8	15112	1165	0	0
T9	2255	75	0	0
T10	6008	433	0	0
T11	231169	67	0	0
T12	538515	2668	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	920428	0	0
T1	458099	1078	0	0
T2	499662	56	0	0
T3	40028	429	0	0
T4	75708	3487	0	0
T7	65922	872	0	0
T8	15112	904	0	0
T9	2255	62	0	0
T10	6008	342	0	0
T11	231169	48	0	0
T12	538515	57	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	228480	0	0
GntImpliesValid_A	408724497	228480	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	228480	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	2803948	0	0
ReadyAndValidImplyGrant_A	408724497	228480	0	0
ReqAndReadyImplyGrant_A	408724497	228480	0	0
ReqImpliesValid_A	408724497	593501	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	228480	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228480	0	0
T2	499662	9	0	0
T3	40028	309	0	0
T4	75708	1490	0	0
T7	65922	199	0	0
T8	15112	221	0	0
T9	2255	15	0	0
T10	6008	79	0	0
T11	231169	10	0	0
T12	538515	15	0	0
T13	306027	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228480	0	0
T2	499662	9	0	0
T3	40028	309	0	0
T4	75708	1490	0	0
T7	65922	199	0	0
T8	15112	221	0	0
T9	2255	15	0	0
T10	6008	79	0	0
T11	231169	10	0	0
T12	538515	15	0	0
T13	306027	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228480	0	0
T2	499662	9	0	0
T3	40028	309	0	0
T4	75708	1490	0	0
T7	65922	199	0	0
T8	15112	221	0	0
T9	2255	15	0	0
T10	6008	79	0	0
T11	231169	10	0	0
T12	538515	15	0	0
T13	306027	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	2803948	0	0
T1	458099	1	0	0
T2	499662	3347	0	0
T3	40028	688	0	0
T4	75708	923	0	0
T7	65922	1485	0	0
T8	15112	210	0	0
T9	2255	16	0	0
T10	6008	73	0	0
T11	231169	47	0	0
T12	538515	3902	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228480	0	0
T2	499662	9	0	0
T3	40028	309	0	0
T4	75708	1490	0	0
T7	65922	199	0	0
T8	15112	221	0	0
T9	2255	15	0	0
T10	6008	79	0	0
T11	231169	10	0	0
T12	538515	15	0	0
T13	306027	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228480	0	0
T2	499662	9	0	0
T3	40028	309	0	0
T4	75708	1490	0	0
T7	65922	199	0	0
T8	15112	221	0	0
T9	2255	15	0	0
T10	6008	79	0	0
T11	231169	10	0	0
T12	538515	15	0	0
T13	306027	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	593501	0	0
T2	499662	9	0	0
T3	40028	2820	0	0
T4	75708	2059	0	0
T7	65922	262	0	0
T8	15112	233	0	0
T9	2255	15	0	0
T10	6008	86	0	0
T11	231169	20	0	0
T12	538515	756	0	0
T13	306027	5375	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228480	0	0
T2	499662	9	0	0
T3	40028	309	0	0
T4	75708	1490	0	0
T7	65922	199	0	0
T8	15112	221	0	0
T9	2255	15	0	0
T10	6008	79	0	0
T11	231169	10	0	0
T12	538515	15	0	0
T13	306027	832	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	213815	0	0
GntImpliesValid_A	408724497	213815	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	213815	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	2770343	0	0
ReadyAndValidImplyGrant_A	408724497	213815	0	0
ReqAndReadyImplyGrant_A	408724497	213815	0	0
ReqImpliesValid_A	408724497	502684	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	213815	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	213815	0	0
T2	499662	11	0	0
T3	40028	63	0	0
T4	75708	1486	0	0
T7	65922	197	0	0
T8	15112	209	0	0
T9	2255	20	0	0
T10	6008	76	0	0
T11	231169	13	0	0
T12	538515	10	0	0
T13	306027	2206	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	213815	0	0
T2	499662	11	0	0
T3	40028	63	0	0
T4	75708	1486	0	0
T7	65922	197	0	0
T8	15112	209	0	0
T9	2255	20	0	0
T10	6008	76	0	0
T11	231169	13	0	0
T12	538515	10	0	0
T13	306027	2206	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	213815	0	0
T2	499662	11	0	0
T3	40028	63	0	0
T4	75708	1486	0	0
T7	65922	197	0	0
T8	15112	209	0	0
T9	2255	20	0	0
T10	6008	76	0	0
T11	231169	13	0	0
T12	538515	10	0	0
T13	306027	2206	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	2770343	0	0
T1	458099	1	0	0
T2	499662	3229	0	0
T3	40028	462	0	0
T4	75708	1277	0	0
T7	65922	1411	0	0
T8	15112	197	0	0
T9	2255	20	0	0
T10	6008	74	0	0
T11	231169	64	0	0
T12	538515	2769	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	213815	0	0
T2	499662	11	0	0
T3	40028	63	0	0
T4	75708	1486	0	0
T7	65922	197	0	0
T8	15112	209	0	0
T9	2255	20	0	0
T10	6008	76	0	0
T11	231169	13	0	0
T12	538515	10	0	0
T13	306027	2206	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	213815	0	0
T2	499662	11	0	0
T3	40028	63	0	0
T4	75708	1486	0	0
T7	65922	197	0	0
T8	15112	209	0	0
T9	2255	20	0	0
T10	6008	76	0	0
T11	231169	13	0	0
T12	538515	10	0	0
T13	306027	2206	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	502684	0	0
T2	499662	11	0	0
T3	40028	64	0	0
T4	75708	1697	0	0
T7	65922	267	0	0
T8	15112	222	0	0
T9	2255	21	0	0
T10	6008	79	0	0
T11	231169	13	0	0
T12	538515	10	0	0
T13	306027	7621	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	213815	0	0
T2	499662	11	0	0
T3	40028	63	0	0
T4	75708	1486	0	0
T7	65922	197	0	0
T8	15112	209	0	0
T9	2255	20	0	0
T10	6008	76	0	0
T11	231169	13	0	0
T12	538515	10	0	0
T13	306027	2206	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	227507	0	0
GntImpliesValid_A	408724497	227507	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	227507	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	5375901	0	0
ReadyAndValidImplyGrant_A	408724497	227507	0	0
ReqAndReadyImplyGrant_A	408724497	227507	0	0
ReqImpliesValid_A	408724497	1269641	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	227507	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	227507	0	0
T1	458099	1025	0	0
T2	499662	15	0	0
T3	40028	67	0	0
T4	75708	1033	0	0
T7	65922	187	0	0
T8	15112	228	0	0
T9	2255	12	0	0
T10	6008	88	0	0
T11	231169	8	0	0
T12	538515	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	227507	0	0
T1	458099	1025	0	0
T2	499662	15	0	0
T3	40028	67	0	0
T4	75708	1033	0	0
T7	65922	187	0	0
T8	15112	228	0	0
T9	2255	12	0	0
T10	6008	88	0	0
T11	231169	8	0	0
T12	538515	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	227507	0	0
T1	458099	1025	0	0
T2	499662	15	0	0
T3	40028	67	0	0
T4	75708	1033	0	0
T7	65922	187	0	0
T8	15112	228	0	0
T9	2255	12	0	0
T10	6008	88	0	0
T11	231169	8	0	0
T12	538515	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	5375901	0	0
T1	458099	5795	0	0
T2	499662	39292	0	0
T3	40028	569	0	0
T4	75708	6046	0	0
T7	65922	847	0	0
T8	15112	1831	0	0
T9	2255	58	0	0
T10	6008	1152	0	0
T11	231169	92	0	0
T12	538515	8420	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	227507	0	0
T1	458099	1025	0	0
T2	499662	15	0	0
T3	40028	67	0	0
T4	75708	1033	0	0
T7	65922	187	0	0
T8	15112	228	0	0
T9	2255	12	0	0
T10	6008	88	0	0
T11	231169	8	0	0
T12	538515	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	227507	0	0
T1	458099	1025	0	0
T2	499662	15	0	0
T3	40028	67	0	0
T4	75708	1033	0	0
T7	65922	187	0	0
T8	15112	228	0	0
T9	2255	12	0	0
T10	6008	88	0	0
T11	231169	8	0	0
T12	538515	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	1269641	0	0
T1	458099	3208	0	0
T2	499662	15	0	0
T3	40028	78	0	0
T4	75708	3022	0	0
T7	65922	247	0	0
T8	15112	434	0	0
T9	2255	18	0	0
T10	6008	406	0	0
T11	231169	19	0	0
T12	538515	472	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	227507	0	0
T1	458099	1025	0	0
T2	499662	15	0	0
T3	40028	67	0	0
T4	75708	1033	0	0
T7	65922	187	0	0
T8	15112	228	0	0
T9	2255	12	0	0
T10	6008	88	0	0
T11	231169	8	0	0
T12	538515	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	223735	0	0
GntImpliesValid_A	408724497	223735	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	223735	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	4903408	0	0
ReadyAndValidImplyGrant_A	408724497	223735	0	0
ReqAndReadyImplyGrant_A	408724497	223735	0	0
ReqImpliesValid_A	408724497	1095574	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	223735	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	223735	0	0
T2	499662	16	0	0
T3	40028	65	0	0
T4	75708	1382	0	0
T7	65922	241	0	0
T8	15112	202	0	0
T9	2255	13	0	0
T10	6008	81	0	0
T11	231169	21	0	0
T12	538515	19	0	0
T13	306027	806	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	223735	0	0
T2	499662	16	0	0
T3	40028	65	0	0
T4	75708	1382	0	0
T7	65922	241	0	0
T8	15112	202	0	0
T9	2255	13	0	0
T10	6008	81	0	0
T11	231169	21	0	0
T12	538515	19	0	0
T13	306027	806	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	223735	0	0
T2	499662	16	0	0
T3	40028	65	0	0
T4	75708	1382	0	0
T7	65922	241	0	0
T8	15112	202	0	0
T9	2255	13	0	0
T10	6008	81	0	0
T11	231169	21	0	0
T12	538515	19	0	0
T13	306027	806	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	4903408	0	0
T2	499662	3708	0	0
T3	40028	724	0	0
T4	75708	8129	0	0
T7	65922	2672	0	0
T8	15112	926	0	0
T9	2255	153	0	0
T10	6008	345	0	0
T11	231169	164	0	0
T12	538515	14625	0	0
T13	306027	4641	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	223735	0	0
T2	499662	16	0	0
T3	40028	65	0	0
T4	75708	1382	0	0
T7	65922	241	0	0
T8	15112	202	0	0
T9	2255	13	0	0
T10	6008	81	0	0
T11	231169	21	0	0
T12	538515	19	0	0
T13	306027	806	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	223735	0	0
T2	499662	16	0	0
T3	40028	65	0	0
T4	75708	1382	0	0
T7	65922	241	0	0
T8	15112	202	0	0
T9	2255	13	0	0
T10	6008	81	0	0
T11	231169	21	0	0
T12	538515	19	0	0
T13	306027	806	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	1095574	0	0
T2	499662	16	0	0
T3	40028	80	0	0
T4	75708	4346	0	0
T7	65922	506	0	0
T8	15112	315	0	0
T9	2255	13	0	0
T10	6008	130	0	0
T11	231169	21	0	0
T12	538515	2758	0	0
T13	306027	5452	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	223735	0	0
T2	499662	16	0	0
T3	40028	65	0	0
T4	75708	1382	0	0
T7	65922	241	0	0
T8	15112	202	0	0
T9	2255	13	0	0
T10	6008	81	0	0
T11	231169	21	0	0
T12	538515	19	0	0
T13	306027	806	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	227083	0	0
GntImpliesValid_A	408724497	227083	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	227083	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	5276187	0	0
ReadyAndValidImplyGrant_A	408724497	227083	0	0
ReqAndReadyImplyGrant_A	408724497	227083	0	0
ReqImpliesValid_A	408724497	1311054	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	227083	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	227083	0	0
T1	458099	467	0	0
T2	499662	9	0	0
T3	40028	55	0	0
T4	75708	971	0	0
T7	65922	198	0	0
T8	15112	254	0	0
T9	2255	11	0	0
T10	6008	81	0	0
T11	231169	14	0	0
T12	538515	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	227083	0	0
T1	458099	467	0	0
T2	499662	9	0	0
T3	40028	55	0	0
T4	75708	971	0	0
T7	65922	198	0	0
T8	15112	254	0	0
T9	2255	11	0	0
T10	6008	81	0	0
T11	231169	14	0	0
T12	538515	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	227083	0	0
T1	458099	467	0	0
T2	499662	9	0	0
T3	40028	55	0	0
T4	75708	971	0	0
T7	65922	198	0	0
T8	15112	254	0	0
T9	2255	11	0	0
T10	6008	81	0	0
T11	231169	14	0	0
T12	538515	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	5276187	0	0
T1	458099	6152	0	0
T2	499662	2618	0	0
T3	40028	2082	0	0
T4	75708	6018	0	0
T7	65922	1097	0	0
T8	15112	1109	0	0
T9	2255	50	0	0
T10	6008	404	0	0
T11	231169	70	0	0
T12	538515	3849	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	227083	0	0
T1	458099	467	0	0
T2	499662	9	0	0
T3	40028	55	0	0
T4	75708	971	0	0
T7	65922	198	0	0
T8	15112	254	0	0
T9	2255	11	0	0
T10	6008	81	0	0
T11	231169	14	0	0
T12	538515	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	227083	0	0
T1	458099	467	0	0
T2	499662	9	0	0
T3	40028	55	0	0
T4	75708	971	0	0
T7	65922	198	0	0
T8	15112	254	0	0
T9	2255	11	0	0
T10	6008	81	0	0
T11	231169	14	0	0
T12	538515	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	1311054	0	0
T1	458099	3219	0	0
T2	499662	9	0	0
T3	40028	241	0	0
T4	75708	2174	0	0
T7	65922	255	0	0
T8	15112	410	0	0
T9	2255	28	0	0
T10	6008	93	0	0
T11	231169	23	0	0
T12	538515	5	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	227083	0	0
T1	458099	467	0	0
T2	499662	9	0	0
T3	40028	55	0	0
T4	75708	971	0	0
T7	65922	198	0	0
T8	15112	254	0	0
T9	2255	11	0	0
T10	6008	81	0	0
T11	231169	14	0	0
T12	538515	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	217231	0	0
GntImpliesValid_A	408724497	217231	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	217231	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	5323508	0	0
ReadyAndValidImplyGrant_A	408724497	217231	0	0
ReqAndReadyImplyGrant_A	408724497	217231	0	0
ReqImpliesValid_A	408724497	1232358	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	217231	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	217231	0	0
T2	499662	13	0	0
T3	40028	185	0	0
T4	75708	1105	0	0
T7	65922	182	0	0
T8	15112	215	0	0
T9	2255	14	0	0
T10	6008	90	0	0
T11	231169	13	0	0
T12	538515	13	0	0
T13	306027	841	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	217231	0	0
T2	499662	13	0	0
T3	40028	185	0	0
T4	75708	1105	0	0
T7	65922	182	0	0
T8	15112	215	0	0
T9	2255	14	0	0
T10	6008	90	0	0
T11	231169	13	0	0
T12	538515	13	0	0
T13	306027	841	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	217231	0	0
T2	499662	13	0	0
T3	40028	185	0	0
T4	75708	1105	0	0
T7	65922	182	0	0
T8	15112	215	0	0
T9	2255	14	0	0
T10	6008	90	0	0
T11	231169	13	0	0
T12	538515	13	0	0
T13	306027	841	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	5323508	0	0
T2	499662	7674	0	0
T3	40028	1255	0	0
T4	75708	4608	0	0
T7	65922	883	0	0
T8	15112	2322	0	0
T9	2255	59	0	0
T10	6008	375	0	0
T11	231169	52	0	0
T12	538515	5280	0	0
T13	306027	6926	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	217231	0	0
T2	499662	13	0	0
T3	40028	185	0	0
T4	75708	1105	0	0
T7	65922	182	0	0
T8	15112	215	0	0
T9	2255	14	0	0
T10	6008	90	0	0
T11	231169	13	0	0
T12	538515	13	0	0
T13	306027	841	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	217231	0	0
T2	499662	13	0	0
T3	40028	185	0	0
T4	75708	1105	0	0
T7	65922	182	0	0
T8	15112	215	0	0
T9	2255	14	0	0
T10	6008	90	0	0
T11	231169	13	0	0
T12	538515	13	0	0
T13	306027	841	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	1232358	0	0
T2	499662	13	0	0
T3	40028	4164	0	0
T4	75708	6372	0	0
T7	65922	199	0	0
T8	15112	612	0	0
T9	2255	14	0	0
T10	6008	155	0	0
T11	231169	17	0	0
T12	538515	107	0	0
T13	306027	4498	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	217231	0	0
T2	499662	13	0	0
T3	40028	185	0	0
T4	75708	1105	0	0
T7	65922	182	0	0
T8	15112	215	0	0
T9	2255	14	0	0
T10	6008	90	0	0
T11	231169	13	0	0
T12	538515	13	0	0
T13	306027	841	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	231207	0	0
GntImpliesValid_A	408724497	231207	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	231207	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	2773131	0	0
ReadyAndValidImplyGrant_A	408724497	231207	0	0
ReqAndReadyImplyGrant_A	408724497	231207	0	0
ReqImpliesValid_A	408724497	556988	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	231207	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	231207	0	0
T2	499662	11	0	0
T3	40028	166	0	0
T4	75708	940	0	0
T7	65922	205	0	0
T8	15112	220	0	0
T9	2255	13	0	0
T10	6008	71	0	0
T11	231169	15	0	0
T12	538515	10	0	0
T13	306027	846	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	231207	0	0
T2	499662	11	0	0
T3	40028	166	0	0
T4	75708	940	0	0
T7	65922	205	0	0
T8	15112	220	0	0
T9	2255	13	0	0
T10	6008	71	0	0
T11	231169	15	0	0
T12	538515	10	0	0
T13	306027	846	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	231207	0	0
T2	499662	11	0	0
T3	40028	166	0	0
T4	75708	940	0	0
T7	65922	205	0	0
T8	15112	220	0	0
T9	2255	13	0	0
T10	6008	71	0	0
T11	231169	15	0	0
T12	538515	10	0	0
T13	306027	846	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	2773131	0	0
T1	458099	1	0	0
T2	499662	1913	0	0
T3	40028	1141	0	0
T4	75708	738	0	0
T7	65922	1704	0	0
T8	15112	211	0	0
T9	2255	12	0	0
T10	6008	71	0	0
T11	231169	46	0	0
T12	538515	3209	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	231207	0	0
T2	499662	11	0	0
T3	40028	166	0	0
T4	75708	940	0	0
T7	65922	205	0	0
T8	15112	220	0	0
T9	2255	13	0	0
T10	6008	71	0	0
T11	231169	15	0	0
T12	538515	10	0	0
T13	306027	846	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	231207	0	0
T2	499662	11	0	0
T3	40028	166	0	0
T4	75708	940	0	0
T7	65922	205	0	0
T8	15112	220	0	0
T9	2255	13	0	0
T10	6008	71	0	0
T11	231169	15	0	0
T12	538515	10	0	0
T13	306027	846	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	556988	0	0
T2	499662	11	0	0
T3	40028	256	0	0
T4	75708	1144	0	0
T7	65922	265	0	0
T8	15112	230	0	0
T9	2255	15	0	0
T10	6008	72	0	0
T11	231169	27	0	0
T12	538515	10	0	0
T13	306027	2669	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	231207	0	0
T2	499662	11	0	0
T3	40028	166	0	0
T4	75708	940	0	0
T7	65922	205	0	0
T8	15112	220	0	0
T9	2255	13	0	0
T10	6008	71	0	0
T11	231169	15	0	0
T12	538515	10	0	0
T13	306027	846	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	232724	0	0
GntImpliesValid_A	408724497	232724	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	232724	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	2744120	0	0
ReadyAndValidImplyGrant_A	408724497	232724	0	0
ReqAndReadyImplyGrant_A	408724497	232724	0	0
ReqImpliesValid_A	408724497	584310	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	232724	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	232724	0	0
T1	458099	513	0	0
T2	499662	11	0	0
T3	40028	65	0	0
T4	75708	1593	0	0
T7	65922	204	0	0
T8	15112	229	0	0
T9	2255	18	0	0
T10	6008	94	0	0
T11	231169	13	0	0
T12	538515	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	232724	0	0
T1	458099	513	0	0
T2	499662	11	0	0
T3	40028	65	0	0
T4	75708	1593	0	0
T7	65922	204	0	0
T8	15112	229	0	0
T9	2255	18	0	0
T10	6008	94	0	0
T11	231169	13	0	0
T12	538515	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	232724	0	0
T1	458099	513	0	0
T2	499662	11	0	0
T3	40028	65	0	0
T4	75708	1593	0	0
T7	65922	204	0	0
T8	15112	229	0	0
T9	2255	18	0	0
T10	6008	94	0	0
T11	231169	13	0	0
T12	538515	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	2744120	0	0
T1	458099	1581	0	0
T2	499662	3607	0	0
T3	40028	512	0	0
T4	75708	995	0	0
T7	65922	1499	0	0
T8	15112	222	0	0
T9	2255	19	0	0
T10	6008	90	0	0
T11	231169	61	0	0
T12	538515	2221	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	232724	0	0
T1	458099	513	0	0
T2	499662	11	0	0
T3	40028	65	0	0
T4	75708	1593	0	0
T7	65922	204	0	0
T8	15112	229	0	0
T9	2255	18	0	0
T10	6008	94	0	0
T11	231169	13	0	0
T12	538515	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	232724	0	0
T1	458099	513	0	0
T2	499662	11	0	0
T3	40028	65	0	0
T4	75708	1593	0	0
T7	65922	204	0	0
T8	15112	229	0	0
T9	2255	18	0	0
T10	6008	94	0	0
T11	231169	13	0	0
T12	538515	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	584310	0	0
T1	458099	1197	0	0
T2	499662	310	0	0
T3	40028	77	0	0
T4	75708	2193	0	0
T7	65922	348	0	0
T8	15112	237	0	0
T9	2255	18	0	0
T10	6008	99	0	0
T11	231169	15	0	0
T12	538515	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	232724	0	0
T1	458099	513	0	0
T2	499662	11	0	0
T3	40028	65	0	0
T4	75708	1593	0	0
T7	65922	204	0	0
T8	15112	229	0	0
T9	2255	18	0	0
T10	6008	94	0	0
T11	231169	13	0	0
T12	538515	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	227479	0	0
GntImpliesValid_A	408724497	227479	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	227479	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	2776996	0	0
ReadyAndValidImplyGrant_A	408724497	227479	0	0
ReqAndReadyImplyGrant_A	408724497	227479	0	0
ReqImpliesValid_A	408724497	540061	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	227479	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	227479	0	0
T2	499662	20	0	0
T3	40028	179	0	0
T4	75708	1002	0	0
T7	65922	214	0	0
T8	15112	231	0	0
T9	2255	11	0	0
T10	6008	82	0	0
T11	231169	20	0	0
T12	538515	12	0	0
T13	306027	712	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	227479	0	0
T2	499662	20	0	0
T3	40028	179	0	0
T4	75708	1002	0	0
T7	65922	214	0	0
T8	15112	231	0	0
T9	2255	11	0	0
T10	6008	82	0	0
T11	231169	20	0	0
T12	538515	12	0	0
T13	306027	712	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	227479	0	0
T2	499662	20	0	0
T3	40028	179	0	0
T4	75708	1002	0	0
T7	65922	214	0	0
T8	15112	231	0	0
T9	2255	11	0	0
T10	6008	82	0	0
T11	231169	20	0	0
T12	538515	12	0	0
T13	306027	712	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	2776996	0	0
T1	458099	1	0	0
T2	499662	7148	0	0
T3	40028	1297	0	0
T4	75708	595	0	0
T7	65922	1482	0	0
T8	15112	219	0	0
T9	2255	12	0	0
T10	6008	80	0	0
T11	231169	99	0	0
T12	538515	4543	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	227479	0	0
T2	499662	20	0	0
T3	40028	179	0	0
T4	75708	1002	0	0
T7	65922	214	0	0
T8	15112	231	0	0
T9	2255	11	0	0
T10	6008	82	0	0
T11	231169	20	0	0
T12	538515	12	0	0
T13	306027	712	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	227479	0	0
T2	499662	20	0	0
T3	40028	179	0	0
T4	75708	1002	0	0
T7	65922	214	0	0
T8	15112	231	0	0
T9	2255	11	0	0
T10	6008	82	0	0
T11	231169	20	0	0
T12	538515	12	0	0
T13	306027	712	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	540061	0	0
T2	499662	666	0	0
T3	40028	384	0	0
T4	75708	1411	0	0
T7	65922	283	0	0
T8	15112	244	0	0
T9	2255	11	0	0
T10	6008	85	0	0
T11	231169	20	0	0
T12	538515	12	0	0
T13	306027	2715	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	227479	0	0
T2	499662	20	0	0
T3	40028	179	0	0
T4	75708	1002	0	0
T7	65922	214	0	0
T8	15112	231	0	0
T9	2255	11	0	0
T10	6008	82	0	0
T11	231169	20	0	0
T12	538515	12	0	0
T13	306027	712	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	228401	0	0
GntImpliesValid_A	408724497	228401	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	228401	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	2827346	0	0
ReadyAndValidImplyGrant_A	408724497	228401	0	0
ReqAndReadyImplyGrant_A	408724497	228401	0	0
ReqImpliesValid_A	408724497	561243	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	228401	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228401	0	0
T2	499662	20	0	0
T3	40028	124	0	0
T4	75708	1032	0	0
T7	65922	220	0	0
T8	15112	229	0	0
T9	2255	14	0	0
T10	6008	73	0	0
T11	231169	15	0	0
T12	538515	18	0	0
T13	306027	789	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228401	0	0
T2	499662	20	0	0
T3	40028	124	0	0
T4	75708	1032	0	0
T7	65922	220	0	0
T8	15112	229	0	0
T9	2255	14	0	0
T10	6008	73	0	0
T11	231169	15	0	0
T12	538515	18	0	0
T13	306027	789	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228401	0	0
T2	499662	20	0	0
T3	40028	124	0	0
T4	75708	1032	0	0
T7	65922	220	0	0
T8	15112	229	0	0
T9	2255	14	0	0
T10	6008	73	0	0
T11	231169	15	0	0
T12	538515	18	0	0
T13	306027	789	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	2827346	0	0
T1	458099	1	0	0
T2	499662	7137	0	0
T3	40028	912	0	0
T4	75708	939	0	0
T7	65922	1684	0	0
T8	15112	218	0	0
T9	2255	15	0	0
T10	6008	72	0	0
T11	231169	57	0	0
T12	538515	5516	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228401	0	0
T2	499662	20	0	0
T3	40028	124	0	0
T4	75708	1032	0	0
T7	65922	220	0	0
T8	15112	229	0	0
T9	2255	14	0	0
T10	6008	73	0	0
T11	231169	15	0	0
T12	538515	18	0	0
T13	306027	789	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228401	0	0
T2	499662	20	0	0
T3	40028	124	0	0
T4	75708	1032	0	0
T7	65922	220	0	0
T8	15112	229	0	0
T9	2255	14	0	0
T10	6008	73	0	0
T11	231169	15	0	0
T12	538515	18	0	0
T13	306027	789	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	561243	0	0
T2	499662	703	0	0
T3	40028	223	0	0
T4	75708	1127	0	0
T7	65922	298	0	0
T8	15112	241	0	0
T9	2255	14	0	0
T10	6008	75	0	0
T11	231169	34	0	0
T12	538515	18	0	0
T13	306027	2854	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228401	0	0
T2	499662	20	0	0
T3	40028	124	0	0
T4	75708	1032	0	0
T7	65922	220	0	0
T8	15112	229	0	0
T9	2255	14	0	0
T10	6008	73	0	0
T11	231169	15	0	0
T12	538515	18	0	0
T13	306027	789	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T8
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T4,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	228171	0	0
GntImpliesValid_A	408724497	228171	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	228171	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	2871208	0	0
ReadyAndValidImplyGrant_A	408724497	228171	0	0
ReqAndReadyImplyGrant_A	408724497	228171	0	0
ReqImpliesValid_A	408724497	561914	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	228171	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228171	0	0
T2	499662	11	0	0
T3	40028	65	0	0
T4	75708	533	0	0
T7	65922	202	0	0
T8	15112	210	0	0
T9	2255	12	0	0
T10	6008	104	0	0
T11	231169	10	0	0
T12	538515	13	0	0
T13	306027	854	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228171	0	0
T2	499662	11	0	0
T3	40028	65	0	0
T4	75708	533	0	0
T7	65922	202	0	0
T8	15112	210	0	0
T9	2255	12	0	0
T10	6008	104	0	0
T11	231169	10	0	0
T12	538515	13	0	0
T13	306027	854	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228171	0	0
T2	499662	11	0	0
T3	40028	65	0	0
T4	75708	533	0	0
T7	65922	202	0	0
T8	15112	210	0	0
T9	2255	12	0	0
T10	6008	104	0	0
T11	231169	10	0	0
T12	538515	13	0	0
T13	306027	854	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	2871208	0	0
T1	458099	1	0	0
T2	499662	3130	0	0
T3	40028	544	0	0
T4	75708	533	0	0
T7	65922	1504	0	0
T8	15112	195	0	0
T9	2255	12	0	0
T10	6008	99	0	0
T11	231169	46	0	0
T12	538515	4691	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228171	0	0
T2	499662	11	0	0
T3	40028	65	0	0
T4	75708	533	0	0
T7	65922	202	0	0
T8	15112	210	0	0
T9	2255	12	0	0
T10	6008	104	0	0
T11	231169	10	0	0
T12	538515	13	0	0
T13	306027	854	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228171	0	0
T2	499662	11	0	0
T3	40028	65	0	0
T4	75708	533	0	0
T7	65922	202	0	0
T8	15112	210	0	0
T9	2255	12	0	0
T10	6008	104	0	0
T11	231169	10	0	0
T12	538515	13	0	0
T13	306027	854	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	561914	0	0
T2	499662	11	0	0
T3	40028	65	0	0
T4	75708	535	0	0
T7	65922	335	0	0
T8	15112	226	0	0
T9	2255	13	0	0
T10	6008	110	0	0
T11	231169	10	0	0
T12	538515	13	0	0
T13	306027	1457	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228171	0	0
T2	499662	11	0	0
T3	40028	65	0	0
T4	75708	533	0	0
T7	65922	202	0	0
T8	15112	210	0	0
T9	2255	12	0	0
T10	6008	104	0	0
T11	231169	10	0	0
T12	538515	13	0	0
T13	306027	854	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	223079	0	0
GntImpliesValid_A	408724497	223079	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	223079	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	2774675	0	0
ReadyAndValidImplyGrant_A	408724497	223079	0	0
ReqAndReadyImplyGrant_A	408724497	223079	0	0
ReqImpliesValid_A	408724497	553699	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	223079	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	223079	0	0
T2	499662	8	0	0
T3	40028	49	0	0
T4	75708	493	0	0
T7	65922	182	0	0
T8	15112	204	0	0
T9	2255	8	0	0
T10	6008	83	0	0
T11	231169	10	0	0
T12	538515	11	0	0
T13	306027	328	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	223079	0	0
T2	499662	8	0	0
T3	40028	49	0	0
T4	75708	493	0	0
T7	65922	182	0	0
T8	15112	204	0	0
T9	2255	8	0	0
T10	6008	83	0	0
T11	231169	10	0	0
T12	538515	11	0	0
T13	306027	328	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	223079	0	0
T2	499662	8	0	0
T3	40028	49	0	0
T4	75708	493	0	0
T7	65922	182	0	0
T8	15112	204	0	0
T9	2255	8	0	0
T10	6008	83	0	0
T11	231169	10	0	0
T12	538515	11	0	0
T13	306027	328	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	2774675	0	0
T1	458099	1	0	0
T2	499662	3116	0	0
T3	40028	386	0	0
T4	75708	486	0	0
T7	65922	1365	0	0
T8	15112	193	0	0
T9	2255	9	0	0
T10	6008	79	0	0
T11	231169	46	0	0
T12	538515	3640	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	223079	0	0
T2	499662	8	0	0
T3	40028	49	0	0
T4	75708	493	0	0
T7	65922	182	0	0
T8	15112	204	0	0
T9	2255	8	0	0
T10	6008	83	0	0
T11	231169	10	0	0
T12	538515	11	0	0
T13	306027	328	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	223079	0	0
T2	499662	8	0	0
T3	40028	49	0	0
T4	75708	493	0	0
T7	65922	182	0	0
T8	15112	204	0	0
T9	2255	8	0	0
T10	6008	83	0	0
T11	231169	10	0	0
T12	538515	11	0	0
T13	306027	328	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	553699	0	0
T2	499662	8	0	0
T3	40028	68	0	0
T4	75708	502	0	0
T7	65922	239	0	0
T8	15112	216	0	0
T9	2255	8	0	0
T10	6008	88	0	0
T11	231169	13	0	0
T12	538515	11	0	0
T13	306027	345	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	223079	0	0
T2	499662	8	0	0
T3	40028	49	0	0
T4	75708	493	0	0
T7	65922	182	0	0
T8	15112	204	0	0
T9	2255	8	0	0
T10	6008	83	0	0
T11	231169	10	0	0
T12	538515	11	0	0
T13	306027	328	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T8
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T4,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	230949	0	0
GntImpliesValid_A	408724497	230949	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	230949	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	2783210	0	0
ReadyAndValidImplyGrant_A	408724497	230949	0	0
ReqAndReadyImplyGrant_A	408724497	230949	0	0
ReqImpliesValid_A	408724497	551530	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	230949	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	230949	0	0
T2	499662	10	0	0
T3	40028	61	0	0
T4	75708	514	0	0
T7	65922	192	0	0
T8	15112	251	0	0
T9	2255	9	0	0
T10	6008	97	0	0
T11	231169	10	0	0
T12	538515	17	0	0
T13	306027	798	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	230949	0	0
T2	499662	10	0	0
T3	40028	61	0	0
T4	75708	514	0	0
T7	65922	192	0	0
T8	15112	251	0	0
T9	2255	9	0	0
T10	6008	97	0	0
T11	231169	10	0	0
T12	538515	17	0	0
T13	306027	798	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	230949	0	0
T2	499662	10	0	0
T3	40028	61	0	0
T4	75708	514	0	0
T7	65922	192	0	0
T8	15112	251	0	0
T9	2255	9	0	0
T10	6008	97	0	0
T11	231169	10	0	0
T12	538515	17	0	0
T13	306027	798	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	2783210	0	0
T1	458099	1	0	0
T2	499662	4804	0	0
T3	40028	494	0	0
T4	75708	513	0	0
T7	65922	1537	0	0
T8	15112	241	0	0
T9	2255	10	0	0
T10	6008	96	0	0
T11	231169	36	0	0
T12	538515	6214	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	230949	0	0
T2	499662	10	0	0
T3	40028	61	0	0
T4	75708	514	0	0
T7	65922	192	0	0
T8	15112	251	0	0
T9	2255	9	0	0
T10	6008	97	0	0
T11	231169	10	0	0
T12	538515	17	0	0
T13	306027	798	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	230949	0	0
T2	499662	10	0	0
T3	40028	61	0	0
T4	75708	514	0	0
T7	65922	192	0	0
T8	15112	251	0	0
T9	2255	9	0	0
T10	6008	97	0	0
T11	231169	10	0	0
T12	538515	17	0	0
T13	306027	798	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	551530	0	0
T2	499662	10	0	0
T3	40028	61	0	0
T4	75708	517	0	0
T7	65922	250	0	0
T8	15112	262	0	0
T9	2255	9	0	0
T10	6008	99	0	0
T11	231169	10	0	0
T12	538515	1370	0	0
T13	306027	2104	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	230949	0	0
T2	499662	10	0	0
T3	40028	61	0	0
T4	75708	514	0	0
T7	65922	192	0	0
T8	15112	251	0	0
T9	2255	9	0	0
T10	6008	97	0	0
T11	231169	10	0	0
T12	538515	17	0	0
T13	306027	798	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T8
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T4,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	236150	0	0
GntImpliesValid_A	408724497	236150	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	236150	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	2737082	0	0
ReadyAndValidImplyGrant_A	408724497	236150	0	0
ReqAndReadyImplyGrant_A	408724497	236150	0	0
ReqImpliesValid_A	408724497	549828	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	236150	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	236150	0	0
T2	499662	11	0	0
T3	40028	46	0	0
T4	75708	1021	0	0
T7	65922	187	0	0
T8	15112	238	0	0
T9	2255	9	0	0
T10	6008	81	0	0
T11	231169	4	0	0
T12	538515	10	0	0
T13	306027	320	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	236150	0	0
T2	499662	11	0	0
T3	40028	46	0	0
T4	75708	1021	0	0
T7	65922	187	0	0
T8	15112	238	0	0
T9	2255	9	0	0
T10	6008	81	0	0
T11	231169	4	0	0
T12	538515	10	0	0
T13	306027	320	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	236150	0	0
T2	499662	11	0	0
T3	40028	46	0	0
T4	75708	1021	0	0
T7	65922	187	0	0
T8	15112	238	0	0
T9	2255	9	0	0
T10	6008	81	0	0
T11	231169	4	0	0
T12	538515	10	0	0
T13	306027	320	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	2737082	0	0
T1	458099	1	0	0
T2	499662	4375	0	0
T3	40028	402	0	0
T4	75708	928	0	0
T7	65922	1488	0	0
T8	15112	230	0	0
T9	2255	10	0	0
T10	6008	79	0	0
T11	231169	15	0	0
T12	538515	2709	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	236150	0	0
T2	499662	11	0	0
T3	40028	46	0	0
T4	75708	1021	0	0
T7	65922	187	0	0
T8	15112	238	0	0
T9	2255	9	0	0
T10	6008	81	0	0
T11	231169	4	0	0
T12	538515	10	0	0
T13	306027	320	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	236150	0	0
T2	499662	11	0	0
T3	40028	46	0	0
T4	75708	1021	0	0
T7	65922	187	0	0
T8	15112	238	0	0
T9	2255	9	0	0
T10	6008	81	0	0
T11	231169	4	0	0
T12	538515	10	0	0
T13	306027	320	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	549828	0	0
T2	499662	11	0	0
T3	40028	46	0	0
T4	75708	1116	0	0
T7	65922	207	0	0
T8	15112	247	0	0
T9	2255	9	0	0
T10	6008	84	0	0
T11	231169	4	0	0
T12	538515	113	0	0
T13	306027	332	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	236150	0	0
T2	499662	11	0	0
T3	40028	46	0	0
T4	75708	1021	0	0
T7	65922	187	0	0
T8	15112	238	0	0
T9	2255	9	0	0
T10	6008	81	0	0
T11	231169	4	0	0
T12	538515	10	0	0
T13	306027	320	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	248896	0	0
GntImpliesValid_A	408724497	248896	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	248896	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	2801907	0	0
ReadyAndValidImplyGrant_A	408724497	248896	0	0
ReqAndReadyImplyGrant_A	408724497	248896	0	0
ReqImpliesValid_A	408724497	569856	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	248896	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	248896	0	0
T2	499662	15	0	0
T3	40028	64	0	0
T4	75708	1093	0	0
T7	65922	198	0	0
T8	15112	240	0	0
T9	2255	21	0	0
T10	6008	87	0	0
T11	231169	15	0	0
T12	538515	10	0	0
T13	306027	858	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	248896	0	0
T2	499662	15	0	0
T3	40028	64	0	0
T4	75708	1093	0	0
T7	65922	198	0	0
T8	15112	240	0	0
T9	2255	21	0	0
T10	6008	87	0	0
T11	231169	15	0	0
T12	538515	10	0	0
T13	306027	858	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	248896	0	0
T2	499662	15	0	0
T3	40028	64	0	0
T4	75708	1093	0	0
T7	65922	198	0	0
T8	15112	240	0	0
T9	2255	21	0	0
T10	6008	87	0	0
T11	231169	15	0	0
T12	538515	10	0	0
T13	306027	858	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	2801907	0	0
T1	458099	1	0	0
T2	499662	4764	0	0
T3	40028	478	0	0
T4	75708	828	0	0
T7	65922	1361	0	0
T8	15112	222	0	0
T9	2255	22	0	0
T10	6008	82	0	0
T11	231169	68	0	0
T12	538515	4055	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	248896	0	0
T2	499662	15	0	0
T3	40028	64	0	0
T4	75708	1093	0	0
T7	65922	198	0	0
T8	15112	240	0	0
T9	2255	21	0	0
T10	6008	87	0	0
T11	231169	15	0	0
T12	538515	10	0	0
T13	306027	858	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	248896	0	0
T2	499662	15	0	0
T3	40028	64	0	0
T4	75708	1093	0	0
T7	65922	198	0	0
T8	15112	240	0	0
T9	2255	21	0	0
T10	6008	87	0	0
T11	231169	15	0	0
T12	538515	10	0	0
T13	306027	858	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	569856	0	0
T2	499662	15	0	0
T3	40028	76	0	0
T4	75708	1360	0	0
T7	65922	318	0	0
T8	15112	259	0	0
T9	2255	21	0	0
T10	6008	93	0	0
T11	231169	15	0	0
T12	538515	52	0	0
T13	306027	2896	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	248896	0	0
T2	499662	15	0	0
T3	40028	64	0	0
T4	75708	1093	0	0
T7	65922	198	0	0
T8	15112	240	0	0
T9	2255	21	0	0
T10	6008	87	0	0
T11	231169	15	0	0
T12	538515	10	0	0
T13	306027	858	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	224645	0	0
GntImpliesValid_A	408724497	224645	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	224645	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	2800541	0	0
ReadyAndValidImplyGrant_A	408724497	224645	0	0
ReqAndReadyImplyGrant_A	408724497	224645	0	0
ReqImpliesValid_A	408724497	521573	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	224645	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	224645	0	0
T2	499662	12	0	0
T3	40028	62	0	0
T4	75708	1478	0	0
T7	65922	202	0	0
T8	15112	214	0	0
T9	2255	15	0	0
T10	6008	82	0	0
T11	231169	8	0	0
T12	538515	13	0	0
T13	306027	822	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	224645	0	0
T2	499662	12	0	0
T3	40028	62	0	0
T4	75708	1478	0	0
T7	65922	202	0	0
T8	15112	214	0	0
T9	2255	15	0	0
T10	6008	82	0	0
T11	231169	8	0	0
T12	538515	13	0	0
T13	306027	822	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	224645	0	0
T2	499662	12	0	0
T3	40028	62	0	0
T4	75708	1478	0	0
T7	65922	202	0	0
T8	15112	214	0	0
T9	2255	15	0	0
T10	6008	82	0	0
T11	231169	8	0	0
T12	538515	13	0	0
T13	306027	822	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	2800541	0	0
T1	458099	1	0	0
T2	499662	2657	0	0
T3	40028	535	0	0
T4	75708	1089	0	0
T7	65922	1536	0	0
T8	15112	200	0	0
T9	2255	16	0	0
T10	6008	78	0	0
T11	231169	35	0	0
T12	538515	3621	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	224645	0	0
T2	499662	12	0	0
T3	40028	62	0	0
T4	75708	1478	0	0
T7	65922	202	0	0
T8	15112	214	0	0
T9	2255	15	0	0
T10	6008	82	0	0
T11	231169	8	0	0
T12	538515	13	0	0
T13	306027	822	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	224645	0	0
T2	499662	12	0	0
T3	40028	62	0	0
T4	75708	1478	0	0
T7	65922	202	0	0
T8	15112	214	0	0
T9	2255	15	0	0
T10	6008	82	0	0
T11	231169	8	0	0
T12	538515	13	0	0
T13	306027	822	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	521573	0	0
T2	499662	12	0	0
T3	40028	70	0	0
T4	75708	1869	0	0
T7	65922	264	0	0
T8	15112	229	0	0
T9	2255	15	0	0
T10	6008	87	0	0
T11	231169	8	0	0
T12	538515	13	0	0
T13	306027	1747	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	224645	0	0
T2	499662	12	0	0
T3	40028	62	0	0
T4	75708	1478	0	0
T7	65922	202	0	0
T8	15112	214	0	0
T9	2255	15	0	0
T10	6008	82	0	0
T11	231169	8	0	0
T12	538515	13	0	0
T13	306027	822	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	236665	0	0
GntImpliesValid_A	408724497	236665	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	236665	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	2832662	0	0
ReadyAndValidImplyGrant_A	408724497	236665	0	0
ReqAndReadyImplyGrant_A	408724497	236665	0	0
ReqImpliesValid_A	408724497	570829	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	236665	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	236665	0	0
T2	499662	17	0	0
T3	40028	51	0	0
T4	75708	986	0	0
T7	65922	196	0	0
T8	15112	256	0	0
T9	2255	10	0	0
T10	6008	76	0	0
T11	231169	9	0	0
T12	538515	11	0	0
T13	306027	748	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	236665	0	0
T2	499662	17	0	0
T3	40028	51	0	0
T4	75708	986	0	0
T7	65922	196	0	0
T8	15112	256	0	0
T9	2255	10	0	0
T10	6008	76	0	0
T11	231169	9	0	0
T12	538515	11	0	0
T13	306027	748	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	236665	0	0
T2	499662	17	0	0
T3	40028	51	0	0
T4	75708	986	0	0
T7	65922	196	0	0
T8	15112	256	0	0
T9	2255	10	0	0
T10	6008	76	0	0
T11	231169	9	0	0
T12	538515	11	0	0
T13	306027	748	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	2832662	0	0
T1	458099	1	0	0
T2	499662	7176	0	0
T3	40028	363	0	0
T4	75708	762	0	0
T7	65922	1496	0	0
T8	15112	243	0	0
T9	2255	10	0	0
T10	6008	71	0	0
T11	231169	44	0	0
T12	538515	2717	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	236665	0	0
T2	499662	17	0	0
T3	40028	51	0	0
T4	75708	986	0	0
T7	65922	196	0	0
T8	15112	256	0	0
T9	2255	10	0	0
T10	6008	76	0	0
T11	231169	9	0	0
T12	538515	11	0	0
T13	306027	748	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	236665	0	0
T2	499662	17	0	0
T3	40028	51	0	0
T4	75708	986	0	0
T7	65922	196	0	0
T8	15112	256	0	0
T9	2255	10	0	0
T10	6008	76	0	0
T11	231169	9	0	0
T12	538515	11	0	0
T13	306027	748	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	570829	0	0
T2	499662	426	0	0
T3	40028	59	0	0
T4	75708	1212	0	0
T7	65922	312	0	0
T8	15112	270	0	0
T9	2255	11	0	0
T10	6008	82	0	0
T11	231169	9	0	0
T12	538515	350	0	0
T13	306027	2654	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	236665	0	0
T2	499662	17	0	0
T3	40028	51	0	0
T4	75708	986	0	0
T7	65922	196	0	0
T8	15112	256	0	0
T9	2255	10	0	0
T10	6008	76	0	0
T11	231169	9	0	0
T12	538515	11	0	0
T13	306027	748	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	231793	0	0
GntImpliesValid_A	408724497	231793	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	231793	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	2797054	0	0
ReadyAndValidImplyGrant_A	408724497	231793	0	0
ReqAndReadyImplyGrant_A	408724497	231793	0	0
ReqImpliesValid_A	408724497	574438	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	231793	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	231793	0	0
T1	458099	543	0	0
T2	499662	16	0	0
T3	40028	124	0	0
T4	75708	1497	0	0
T7	65922	190	0	0
T8	15112	221	0	0
T9	2255	21	0	0
T10	6008	91	0	0
T11	231169	13	0	0
T12	538515	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	231793	0	0
T1	458099	543	0	0
T2	499662	16	0	0
T3	40028	124	0	0
T4	75708	1497	0	0
T7	65922	190	0	0
T8	15112	221	0	0
T9	2255	21	0	0
T10	6008	91	0	0
T11	231169	13	0	0
T12	538515	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	231793	0	0
T1	458099	543	0	0
T2	499662	16	0	0
T3	40028	124	0	0
T4	75708	1497	0	0
T7	65922	190	0	0
T8	15112	221	0	0
T9	2255	21	0	0
T10	6008	91	0	0
T11	231169	13	0	0
T12	538515	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	2797054	0	0
T1	458099	1705	0	0
T2	499662	5719	0	0
T3	40028	896	0	0
T4	75708	1029	0	0
T7	65922	1396	0	0
T8	15112	205	0	0
T9	2255	22	0	0
T10	6008	87	0	0
T11	231169	59	0	0
T12	538515	5626	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	231793	0	0
T1	458099	543	0	0
T2	499662	16	0	0
T3	40028	124	0	0
T4	75708	1497	0	0
T7	65922	190	0	0
T8	15112	221	0	0
T9	2255	21	0	0
T10	6008	91	0	0
T11	231169	13	0	0
T12	538515	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	231793	0	0
T1	458099	543	0	0
T2	499662	16	0	0
T3	40028	124	0	0
T4	75708	1497	0	0
T7	65922	190	0	0
T8	15112	221	0	0
T9	2255	21	0	0
T10	6008	91	0	0
T11	231169	13	0	0
T12	538515	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	574438	0	0
T1	458099	1239	0	0
T2	499662	102	0	0
T3	40028	348	0	0
T4	75708	1967	0	0
T7	65922	284	0	0
T8	15112	238	0	0
T9	2255	21	0	0
T10	6008	96	0	0
T11	231169	18	0	0
T12	538515	90	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	231793	0	0
T1	458099	543	0	0
T2	499662	16	0	0
T3	40028	124	0	0
T4	75708	1497	0	0
T7	65922	190	0	0
T8	15112	221	0	0
T9	2255	21	0	0
T10	6008	91	0	0
T11	231169	13	0	0
T12	538515	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	215839	0	0
GntImpliesValid_A	408724497	215839	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	215839	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	2742922	0	0
ReadyAndValidImplyGrant_A	408724497	215839	0	0
ReqAndReadyImplyGrant_A	408724497	215839	0	0
ReqImpliesValid_A	408724497	496751	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	215839	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	215839	0	0
T2	499662	14	0	0
T3	40028	62	0	0
T4	75708	1003	0	0
T7	65922	206	0	0
T8	15112	222	0	0
T9	2255	17	0	0
T10	6008	78	0	0
T11	231169	19	0	0
T12	538515	4	0	0
T13	306027	818	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	215839	0	0
T2	499662	14	0	0
T3	40028	62	0	0
T4	75708	1003	0	0
T7	65922	206	0	0
T8	15112	222	0	0
T9	2255	17	0	0
T10	6008	78	0	0
T11	231169	19	0	0
T12	538515	4	0	0
T13	306027	818	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	215839	0	0
T2	499662	14	0	0
T3	40028	62	0	0
T4	75708	1003	0	0
T7	65922	206	0	0
T8	15112	222	0	0
T9	2255	17	0	0
T10	6008	78	0	0
T11	231169	19	0	0
T12	538515	4	0	0
T13	306027	818	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	2742922	0	0
T1	458099	1	0	0
T2	499662	4498	0	0
T3	40028	592	0	0
T4	75708	802	0	0
T7	65922	1417	0	0
T8	15112	213	0	0
T9	2255	17	0	0
T10	6008	74	0	0
T11	231169	76	0	0
T12	538515	1149	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	215839	0	0
T2	499662	14	0	0
T3	40028	62	0	0
T4	75708	1003	0	0
T7	65922	206	0	0
T8	15112	222	0	0
T9	2255	17	0	0
T10	6008	78	0	0
T11	231169	19	0	0
T12	538515	4	0	0
T13	306027	818	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	215839	0	0
T2	499662	14	0	0
T3	40028	62	0	0
T4	75708	1003	0	0
T7	65922	206	0	0
T8	15112	222	0	0
T9	2255	17	0	0
T10	6008	78	0	0
T11	231169	19	0	0
T12	538515	4	0	0
T13	306027	818	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	496751	0	0
T2	499662	173	0	0
T3	40028	69	0	0
T4	75708	1206	0	0
T7	65922	291	0	0
T8	15112	232	0	0
T9	2255	18	0	0
T10	6008	83	0	0
T11	231169	33	0	0
T12	538515	4	0	0
T13	306027	1774	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	215839	0	0
T2	499662	14	0	0
T3	40028	62	0	0
T4	75708	1003	0	0
T7	65922	206	0	0
T8	15112	222	0	0
T9	2255	17	0	0
T10	6008	78	0	0
T11	231169	19	0	0
T12	538515	4	0	0
T13	306027	818	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	228637	0	0
GntImpliesValid_A	408724497	228637	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	228637	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	2733235	0	0
ReadyAndValidImplyGrant_A	408724497	228637	0	0
ReqAndReadyImplyGrant_A	408724497	228637	0	0
ReqImpliesValid_A	408724497	538916	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	0	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	228637	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228637	0	0
T1	458099	952	0	0
T2	499662	9	0	0
T3	40028	182	0	0
T4	75708	946	0	0
T7	65922	196	0	0
T8	15112	229	0	0
T9	2255	17	0	0
T10	6008	89	0	0
T11	231169	5	0	0
T12	538515	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228637	0	0
T1	458099	952	0	0
T2	499662	9	0	0
T3	40028	182	0	0
T4	75708	946	0	0
T7	65922	196	0	0
T8	15112	229	0	0
T9	2255	17	0	0
T10	6008	89	0	0
T11	231169	5	0	0
T12	538515	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228637	0	0
T1	458099	952	0	0
T2	499662	9	0	0
T3	40028	182	0	0
T4	75708	946	0	0
T7	65922	196	0	0
T8	15112	229	0	0
T9	2255	17	0	0
T10	6008	89	0	0
T11	231169	5	0	0
T12	538515	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	2733235	0	0
T1	458099	3199	0	0
T2	499662	3947	0	0
T3	40028	1229	0	0
T4	75708	867	0	0
T7	65922	1404	0	0
T8	15112	215	0	0
T9	2255	17	0	0
T10	6008	86	0	0
T11	231169	29	0	0
T12	538515	3135	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228637	0	0
T1	458099	952	0	0
T2	499662	9	0	0
T3	40028	182	0	0
T4	75708	946	0	0
T7	65922	196	0	0
T8	15112	229	0	0
T9	2255	17	0	0
T10	6008	89	0	0
T11	231169	5	0	0
T12	538515	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228637	0	0
T1	458099	952	0	0
T2	499662	9	0	0
T3	40028	182	0	0
T4	75708	946	0	0
T7	65922	196	0	0
T8	15112	229	0	0
T9	2255	17	0	0
T10	6008	89	0	0
T11	231169	5	0	0
T12	538515	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	538916	0	0
T1	458099	2369	0	0
T2	499662	9	0	0
T3	40028	317	0	0
T4	75708	1027	0	0
T7	65922	279	0	0
T8	15112	244	0	0
T9	2255	18	0	0
T10	6008	93	0	0
T11	231169	9	0	0
T12	538515	159	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	228637	0	0
T1	458099	952	0	0
T2	499662	9	0	0
T3	40028	182	0	0
T4	75708	946	0	0
T7	65922	196	0	0
T8	15112	229	0	0
T9	2255	17	0	0
T10	6008	89	0	0
T11	231169	5	0	0
T12	538515	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	919062	0	0
GntImpliesValid_A	408724497	919062	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	919062	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	10439608	0	0
ReadyAndValidImplyGrant_A	408724497	919062	0	0
ReqAndReadyImplyGrant_A	408724497	919062	0	0
ReqImpliesValid_A	408724497	2159217	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	22446	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	919062	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	919062	0	0
T1	458099	1175	0	0
T2	499662	69	0	0
T3	40028	605	0	0
T4	75708	3339	0	0
T7	65922	839	0	0
T8	15112	833	0	0
T9	2255	79	0	0
T10	6008	335	0	0
T11	231169	42	0	0
T12	538515	51	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	919062	0	0
T1	458099	1175	0	0
T2	499662	69	0	0
T3	40028	605	0	0
T4	75708	3339	0	0
T7	65922	839	0	0
T8	15112	833	0	0
T9	2255	79	0	0
T10	6008	335	0	0
T11	231169	42	0	0
T12	538515	51	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	919062	0	0
T1	458099	1175	0	0
T2	499662	69	0	0
T3	40028	605	0	0
T4	75708	3339	0	0
T7	65922	839	0	0
T8	15112	833	0	0
T9	2255	79	0	0
T10	6008	335	0	0
T11	231169	42	0	0
T12	538515	51	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	10439608	0	0
T1	458099	3248	0	0
T2	499662	19063	0	0
T3	40028	3757	0	0
T4	75708	2	0	0
T7	65922	4795	0	0
T8	15112	1	0	0
T9	2255	1	0	0
T10	6008	1	0	0
T11	231169	145	0	0
T12	538515	17011	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	919062	0	0
T1	458099	1175	0	0
T2	499662	69	0	0
T3	40028	605	0	0
T4	75708	3339	0	0
T7	65922	839	0	0
T8	15112	833	0	0
T9	2255	79	0	0
T10	6008	335	0	0
T11	231169	42	0	0
T12	538515	51	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	919062	0	0
T1	458099	1175	0	0
T2	499662	69	0	0
T3	40028	605	0	0
T4	75708	3339	0	0
T7	65922	839	0	0
T8	15112	833	0	0
T9	2255	79	0	0
T10	6008	335	0	0
T11	231169	42	0	0
T12	538515	51	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	2159217	0	0
T1	458099	2309	0	0
T2	499662	1536	0	0
T3	40028	1216	0	0
T4	75708	3339	0	0
T7	65922	1617	0	0
T8	15112	833	0	0
T9	2255	79	0	0
T10	6008	335	0	0
T11	231169	50	0	0
T12	538515	659	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	22446	0	900
T1	458099	9	0	1
T2	499662	0	0	1
T3	40028	0	0	1
T4	75708	21	0	1
T5	0	11	0	0
T7	65922	0	0	1
T8	15112	10	0	1
T9	2255	0	0	1
T10	6008	4	0	1
T11	231169	0	0	1
T12	538515	0	0	1
T13	0	1	0	0
T15	0	1	0	0
T16	0	4	0	0
T17	0	12	0	0
T18	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	919062	0	0
T1	458099	1175	0	0
T2	499662	69	0	0
T3	40028	605	0	0
T4	75708	3339	0	0
T7	65922	839	0	0
T8	15112	833	0	0
T9	2255	79	0	0
T10	6008	335	0	0
T11	231169	42	0	0
T12	538515	51	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408724497	408589849	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408724497	908771	0	0
GntImpliesValid_A	408724497	908771	0	0
GrantKnown_A	408724497	408589849	0	0
IdxKnown_A	408724497	408589849	0	0
IndexIsCorrect_A	408724497	908771	0	0
LockArbDecision_A	408724497	0	0	0
NoReadyValidNoGrant_A	408724497	341634733	0	0
ReadyAndValidImplyGrant_A	408724497	908771	0	0
ReqAndReadyImplyGrant_A	408724497	908771	0	0
ReqImpliesValid_A	408724497	12099221	0	0
ReqStaysHighUntilGranted0_M	408724497	0	0	0
RoundRobin_A	408724497	32696	0	900
ValidKnown_A	408724497	408589849	0	0
gen_data_port_assertion.DataFlow_A	408724497	908771	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	908771	0	0
T1	458099	2033	0	0
T2	499662	40	0	0
T3	40028	467	0	0
T4	75708	3387	0	0
T7	65922	845	0	0
T8	15112	854	0	0
T9	2255	51	0	0
T10	6008	340	0	0
T11	231169	45	0	0
T12	538515	52	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	908771	0	0
T1	458099	2033	0	0
T2	499662	40	0	0
T3	40028	467	0	0
T4	75708	3387	0	0
T7	65922	845	0	0
T8	15112	854	0	0
T9	2255	51	0	0
T10	6008	340	0	0
T11	231169	45	0	0
T12	538515	52	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	908771	0	0
T1	458099	2033	0	0
T2	499662	40	0	0
T3	40028	467	0	0
T4	75708	3387	0	0
T7	65922	845	0	0
T8	15112	854	0	0
T9	2255	51	0	0
T10	6008	340	0	0
T11	231169	45	0	0
T12	538515	52	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	341634733	0	0
T1	458099	381045	0	0
T2	499662	474530	0	0
T3	40028	30657	0	0
T4	75708	1	0	0
T7	65922	51801	0	0
T8	15112	1	0	0
T9	2255	1	0	0
T10	6008	1	0	0
T11	231169	192419	0	0
T12	538515	519086	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	908771	0	0
T1	458099	2033	0	0
T2	499662	40	0	0
T3	40028	467	0	0
T4	75708	3387	0	0
T7	65922	845	0	0
T8	15112	854	0	0
T9	2255	51	0	0
T10	6008	340	0	0
T11	231169	45	0	0
T12	538515	52	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	908771	0	0
T1	458099	2033	0	0
T2	499662	40	0	0
T3	40028	467	0	0
T4	75708	3387	0	0
T7	65922	845	0	0
T8	15112	854	0	0
T9	2255	51	0	0
T10	6008	340	0	0
T11	231169	45	0	0
T12	538515	52	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	12099221	0	0
T1	458099	9378	0	0
T2	499662	16234	0	0
T3	40028	3564	0	0
T4	75708	3387	0	0
T7	65922	6270	0	0
T8	15112	854	0	0
T9	2255	51	0	0
T10	6008	340	0	0
T11	231169	196	0	0
T12	538515	18347	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	32696	0	900
T1	458099	18	0	1
T2	499662	0	0	1
T3	40028	0	0	1
T4	75708	30	0	1
T5	0	13	0	0
T7	65922	2	0	1
T8	15112	9	0	1
T9	2255	0	0	1
T10	6008	8	0	1
T11	231169	0	0	1
T12	538515	0	0	1
T13	0	8	0	0
T14	0	3	0	0
T15	0	2	0	0
T16	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	408589849	0	0
T1	458099	458096	0	0
T2	499662	499609	0	0
T3	40028	38552	0	0
T4	75708	75598	0	0
T7	65922	65905	0	0
T8	15112	15088	0	0
T9	2255	2232	0	0
T10	6008	5961	0	0
T11	231169	231159	0	0
T12	538515	538431	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408724497	908771	0	0
T1	458099	2033	0	0
T2	499662	40	0	0
T3	40028	467	0	0
T4	75708	3387	0	0
T7	65922	845	0	0
T8	15112	854	0	0
T9	2255	51	0	0
T10	6008	340	0	0
T11	231169	45	0	0
T12	538515	52	0	0