Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1514841	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

241051

1

T1

247

T2

17

T3

192

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	597062	1			T1	588		T2	60		T3	388
values[0x0]	562639	1			T1	541		T2	58		T3	420
values[0x1]	596191	1			T1	594		T2	60		T3	465

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1170944	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

584948

1

T1

591

T2

53

T3

453

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28241	1			T1	22		T2	6		T3	31
valid_sources[0x01]	27760	1			T1	38		T2	5		T3	18
valid_sources[0x02]	26537	1			T1	29		T2	5		T3	25
valid_sources[0x03]	27100	1			T1	31		T2	3		T3	20
valid_sources[0x04]	28228	1			T1	30		T2	2		T3	29
valid_sources[0x05]	27904	1			T1	22		T2	2		T3	20
valid_sources[0x06]	27350	1			T1	32		T2	1		T3	19
valid_sources[0x07]	27778	1			T1	21		T2	6		T3	21
valid_sources[0x08]	27896	1			T1	34		T2	5		T3	26
valid_sources[0x09]	27580	1			T1	15		T2	2		T3	14
valid_sources[0x0a]	27074	1			T1	22		T2	4		T3	25
valid_sources[0x0b]	28181	1			T1	24		T2	10		T3	13
valid_sources[0x0c]	26038	1			T1	30		T2	2		T3	14
valid_sources[0x0d]	27170	1			T1	22		T3	18		T7	3
valid_sources[0x0e]	27120	1			T1	30		T3	23		T8	2
valid_sources[0x0f]	26921	1			T1	22		T2	1		T3	13
valid_sources[0x10]	26790	1			T1	27		T2	1		T3	25
valid_sources[0x11]	27016	1			T1	28		T2	2		T3	14
valid_sources[0x12]	28361	1			T1	23		T2	1		T3	21
valid_sources[0x13]	27561	1			T1	31		T2	1		T3	21
valid_sources[0x14]	27175	1			T1	33		T2	1		T3	8
valid_sources[0x15]	28061	1			T1	33		T2	4		T3	25
valid_sources[0x16]	26479	1			T1	30		T2	4		T3	24
valid_sources[0x17]	27275	1			T1	28		T2	2		T3	16
valid_sources[0x18]	26648	1			T1	22		T3	11		T9	19
valid_sources[0x19]	27390	1			T1	24		T2	4		T3	19
valid_sources[0x1a]	27262	1			T1	35		T2	3		T3	31
valid_sources[0x1b]	27205	1			T1	18		T2	1		T3	22
valid_sources[0x1c]	27746	1			T1	23		T2	3		T3	20
valid_sources[0x1d]	27245	1			T1	30		T2	4		T3	23
valid_sources[0x1e]	26855	1			T1	24		T2	3		T3	21
valid_sources[0x1f]	27671	1			T1	32		T2	1		T3	14
valid_sources[0x20]	27303	1			T1	25		T2	1		T3	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25340

1

T1

25

T2

1

T3

14

values[0x0]

all_enables

biggest_size

189856

1

T1

195

T2

14

T3

154

values[0x1]

all_enables

biggest_size

25855

1

T1

27

T2

2

T3

24

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1521602	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

248557

1

T1

192

T2

19

T3

157

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	606050	1			T1	572		T2	47		T3	390
values[0x0]	558433	1			T1	557		T2	44		T3	371
values[0x1]	605676	1			T1	557		T2	40		T3	388

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1167011	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

603148

1

T1

537

T2

35

T3

386

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27411	1			T1	21		T2	1		T3	11
valid_sources[0x01]	27408	1			T1	16		T3	14		T9	2
valid_sources[0x02]	27005	1			T1	20		T2	1		T3	10
valid_sources[0x03]	27930	1			T1	24		T3	29		T9	3
valid_sources[0x04]	27689	1			T1	18		T3	11		T9	2
valid_sources[0x05]	28111	1			T1	17		T2	2		T3	24
valid_sources[0x06]	28343	1			T1	21		T2	7		T3	25
valid_sources[0x07]	27438	1			T1	22		T2	12		T3	11
valid_sources[0x08]	28667	1			T1	41		T2	3		T3	37
valid_sources[0x09]	27250	1			T1	30		T2	3		T3	11
valid_sources[0x0a]	27662	1			T1	31		T2	1		T3	15
valid_sources[0x0b]	27332	1			T1	9		T2	1		T3	6
valid_sources[0x0c]	26799	1			T1	9		T2	1		T3	26
valid_sources[0x0d]	27513	1			T1	33		T2	1		T3	15
valid_sources[0x0e]	27529	1			T1	24		T2	2		T3	25
valid_sources[0x0f]	27339	1			T1	22		T3	19		T9	5
valid_sources[0x10]	27186	1			T1	21		T2	10		T3	26
valid_sources[0x11]	27472	1			T1	15		T2	4		T3	17
valid_sources[0x12]	28316	1			T1	37		T3	10		T9	1
valid_sources[0x13]	27821	1			T1	37		T2	1		T3	17
valid_sources[0x14]	26956	1			T1	22		T2	1		T3	22
valid_sources[0x15]	27612	1			T1	48		T3	33		T9	1
valid_sources[0x16]	27746	1			T1	25		T3	1		T9	2
valid_sources[0x17]	27697	1			T1	22		T3	35		T9	4
valid_sources[0x18]	28196	1			T1	26		T2	2		T3	9
valid_sources[0x19]	27672	1			T1	35		T2	2		T3	14
valid_sources[0x1a]	27909	1			T1	44		T2	2		T3	30
valid_sources[0x1b]	28562	1			T1	36		T2	1		T3	29
valid_sources[0x1c]	27332	1			T1	16		T2	3		T3	13
valid_sources[0x1d]	27610	1			T1	21		T2	3		T3	13
valid_sources[0x1e]	27698	1			T1	19		T2	7		T3	26
valid_sources[0x1f]	28302	1			T1	9		T3	29		T9	3
valid_sources[0x20]	27203	1			T1	34		T3	5		T9	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26002

1

T1

13

T2

2

T3

11

values[0x0]

all_enables

biggest_size

196208

1

T1

164

T2

14

T3

135

values[0x1]

all_enables

biggest_size

26347

1

T1

15

T2

3

T3

11

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1524139	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

242359

1

T1

208

T2

23

T3

185

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	599713	1			T1	544		T2	57		T3	395
values[0x0]	566717	1			T1	513		T2	61		T3	391
values[0x1]	600068	1			T1	555		T2	71		T3	433

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1177998	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

588500

1

T1

523

T2

63

T3

431

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28311	1			T1	59		T3	19		T7	4
valid_sources[0x01]	27959	1			T1	21		T3	14		T8	5
valid_sources[0x02]	27474	1			T1	2		T2	4		T3	15
valid_sources[0x03]	27882	1			T1	33		T3	32		T9	41
valid_sources[0x04]	28031	1			T1	5		T3	27		T8	8
valid_sources[0x05]	27381	1			T1	21		T2	4		T3	15
valid_sources[0x06]	27907	1			T1	3		T3	14		T7	5
valid_sources[0x07]	27241	1			T1	11		T2	3		T3	22
valid_sources[0x08]	28018	1			T1	74		T3	8		T7	1
valid_sources[0x09]	27483	1			T1	3		T2	1		T3	22
valid_sources[0x0a]	27564	1			T1	14		T3	19		T8	5
valid_sources[0x0b]	27271	1			T1	47		T3	23		T7	1
valid_sources[0x0c]	26274	1			T1	21		T2	4		T3	10
valid_sources[0x0d]	26852	1			T1	68		T3	16		T8	7
valid_sources[0x0e]	27306	1			T1	49		T3	20		T8	14
valid_sources[0x0f]	27379	1			T1	2		T3	17		T7	1
valid_sources[0x10]	27481	1			T2	7		T3	14		T8	8
valid_sources[0x11]	26819	1			T1	28		T3	23		T7	1
valid_sources[0x12]	27055	1			T1	28		T3	18		T7	6
valid_sources[0x13]	28136	1			T1	4		T3	24		T7	2
valid_sources[0x14]	27725	1			T2	4		T3	24		T8	2
valid_sources[0x15]	26838	1			T1	42		T2	4		T3	22
valid_sources[0x16]	27785	1			T1	17		T3	26		T7	10
valid_sources[0x17]	27778	1			T1	44		T2	4		T3	15
valid_sources[0x18]	27967	1			T1	10		T3	21		T7	1
valid_sources[0x19]	28240	1			T3	28		T7	7		T8	7
valid_sources[0x1a]	28725	1			T1	32		T2	5		T3	17
valid_sources[0x1b]	27660	1			T1	66		T3	21		T8	6
valid_sources[0x1c]	27854	1			T2	2		T3	21		T8	7
valid_sources[0x1d]	27928	1			T1	12		T2	1		T3	16
valid_sources[0x1e]	27656	1			T1	6		T2	15		T3	27
valid_sources[0x1f]	28848	1			T1	5		T3	14		T7	3
valid_sources[0x20]	27289	1			T1	37		T2	12		T3	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25689

1

T1

24

T2

1

T3

17

values[0x0]

all_enables

biggest_size

191118

1

T1

160

T2

21

T3

138

values[0x1]

all_enables

biggest_size

25552

1

T1

24

T2

1

T3

30