Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8051426	0	0
GntImpliesValid_A	2147483647	8051426	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8051426	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	480400705	0	0
ReadyAndValidImplyGrant_A	2147483647	8051426	0	0
ReqAndReadyImplyGrant_A	2147483647	8051426	0	0
ReqImpliesValid_A	2147483647	35409839	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	59155	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8051426	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	212832	212160	0	0
T2	328632	328008	0	0
T3	106296	106080	0	0
T7	9346416	9345528	0	0
T8	8524032	8490480	0	0
T9	42504	42336	0	0
T10	10873872	10873416	0	0
T11	144072	143568	0	0
T12	2827896	2827800	0	0
T13	13910544	13910352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8051426	0	0
T1	212832	5019	0	0
T2	328632	498	0	0
T3	106296	1888	0	0
T7	9346416	390	0	0
T8	8524032	26616	0	0
T9	42504	470	0	0
T10	10873872	446	0	0
T11	144072	2229	0	0
T12	2827896	3843	0	0
T13	13910544	11080	0	0
T14	0	2077	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8051426	0	0
T1	212832	5019	0	0
T2	328632	498	0	0
T3	106296	1888	0	0
T7	9346416	390	0	0
T8	8524032	26616	0	0
T9	42504	470	0	0
T10	10873872	446	0	0
T11	144072	2229	0	0
T12	2827896	3843	0	0
T13	13910544	11080	0	0
T14	0	2077	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	212832	212160	0	0
T2	328632	328008	0	0
T3	106296	106080	0	0
T7	9346416	9345528	0	0
T8	8524032	8490480	0	0
T9	42504	42336	0	0
T10	10873872	10873416	0	0
T11	144072	143568	0	0
T12	2827896	2827800	0	0
T13	13910544	13910352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	212832	212160	0	0
T2	328632	328008	0	0
T3	106296	106080	0	0
T7	9346416	9345528	0	0
T8	8524032	8490480	0	0
T9	42504	42336	0	0
T10	10873872	10873416	0	0
T11	144072	143568	0	0
T12	2827896	2827800	0	0
T13	13910544	13910352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8051426	0	0
T1	212832	5019	0	0
T2	328632	498	0	0
T3	106296	1888	0	0
T7	9346416	390	0	0
T8	8524032	26616	0	0
T9	42504	470	0	0
T10	10873872	446	0	0
T11	144072	2229	0	0
T12	2827896	3843	0	0
T13	13910544	11080	0	0
T14	0	2077	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	480400705	0	0
T1	212832	6679	0	0
T2	328632	15904	0	0
T3	106296	2038	0	0
T7	9346416	482234	0	0
T8	8524032	526777	0	0
T9	42504	544	0	0
T10	10873872	558795	0	0
T11	144072	3184	0	0
T12	2827896	995617	0	0
T13	13910544	533829	0	0
T14	0	144	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8051426	0	0
T1	212832	5019	0	0
T2	328632	498	0	0
T3	106296	1888	0	0
T7	9346416	390	0	0
T8	8524032	26616	0	0
T9	42504	470	0	0
T10	10873872	446	0	0
T11	144072	2229	0	0
T12	2827896	3843	0	0
T13	13910544	11080	0	0
T14	0	2077	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8051426	0	0
T1	212832	5019	0	0
T2	328632	498	0	0
T3	106296	1888	0	0
T7	9346416	390	0	0
T8	8524032	26616	0	0
T9	42504	470	0	0
T10	10873872	446	0	0
T11	144072	2229	0	0
T12	2827896	3843	0	0
T13	13910544	11080	0	0
T14	0	2077	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35409839	0	0
T1	212832	5727	0	0
T2	328632	1080	0	0
T3	106296	2068	0	0
T7	9346416	21833	0	0
T8	8524032	54831	0	0
T9	42504	525	0	0
T10	10873872	18265	0	0
T11	144072	2551	0	0
T12	2827896	6383	0	0
T13	13910544	32129	0	0
T14	0	13073	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	59155	0	21600
T1	17736	19	0	2
T2	27386	0	0	2
T3	8858	3	0	2
T7	778868	0	0	2
T8	710336	2	0	2
T9	3542	0	0	2
T10	906156	0	0	2
T11	12006	5	0	2
T12	235658	0	0	2
T13	1159212	12	0	2
T15	0	273	0	0
T16	0	15	0	0
T17	0	22	0	0
T18	0	25	0	0
T19	0	671	0	0
T20	0	7	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	212832	212160	0	0
T2	328632	328008	0	0
T3	106296	106080	0	0
T7	9346416	9345528	0	0
T8	8524032	8490480	0	0
T9	42504	42336	0	0
T10	10873872	10873416	0	0
T11	144072	143568	0	0
T12	2827896	2827800	0	0
T13	13910544	13910352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8051426	0	0
T1	212832	5019	0	0
T2	328632	498	0	0
T3	106296	1888	0	0
T7	9346416	390	0	0
T8	8524032	26616	0	0
T9	42504	470	0	0
T10	10873872	446	0	0
T11	144072	2229	0	0
T12	2827896	3843	0	0
T13	13910544	11080	0	0
T14	0	2077	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	899622	0	0
GntImpliesValid_A	438663802	899622	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	899622	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	12648102	0	0
ReadyAndValidImplyGrant_A	438663802	899622	0	0
ReqAndReadyImplyGrant_A	438663802	899622	0	0
ReqImpliesValid_A	438663802	2558642	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	899622	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	899622	0	0
T1	8868	532	0	0
T2	13693	37	0	0
T3	4429	209	0	0
T7	389434	44	0	0
T8	355168	3027	0	0
T9	1771	44	0	0
T10	453078	51	0	0
T11	6003	252	0	0
T12	117829	448	0	0
T13	579606	1443	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	899622	0	0
T1	8868	532	0	0
T2	13693	37	0	0
T3	4429	209	0	0
T7	389434	44	0	0
T8	355168	3027	0	0
T9	1771	44	0	0
T10	453078	51	0	0
T11	6003	252	0	0
T12	117829	448	0	0
T13	579606	1443	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	899622	0	0
T1	8868	532	0	0
T2	13693	37	0	0
T3	4429	209	0	0
T7	389434	44	0	0
T8	355168	3027	0	0
T9	1771	44	0	0
T10	453078	51	0	0
T11	6003	252	0	0
T12	117829	448	0	0
T13	579606	1443	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	12648102	0	0
T1	8868	411	0	0
T2	13693	270	0	0
T3	4429	174	0	0
T7	389434	13888	0	0
T8	355168	22604	0	0
T9	1771	35	0	0
T10	453078	19097	0	0
T11	6003	211	0	0
T12	117829	1875	0	0
T13	579606	5273	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	899622	0	0
T1	8868	532	0	0
T2	13693	37	0	0
T3	4429	209	0	0
T7	389434	44	0	0
T8	355168	3027	0	0
T9	1771	44	0	0
T10	453078	51	0	0
T11	6003	252	0	0
T12	117829	448	0	0
T13	579606	1443	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	899622	0	0
T1	8868	532	0	0
T2	13693	37	0	0
T3	4429	209	0	0
T7	389434	44	0	0
T8	355168	3027	0	0
T9	1771	44	0	0
T10	453078	51	0	0
T11	6003	252	0	0
T12	117829	448	0	0
T13	579606	1443	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	2558642	0	0
T1	8868	654	0	0
T2	13693	49	0	0
T3	4429	245	0	0
T7	389434	44	0	0
T8	355168	4478	0	0
T9	1771	54	0	0
T10	453078	838	0	0
T11	6003	294	0	0
T12	117829	572	0	0
T13	579606	2799	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	899622	0	0
T1	8868	532	0	0
T2	13693	37	0	0
T3	4429	209	0	0
T7	389434	44	0	0
T8	355168	3027	0	0
T9	1771	44	0	0
T10	453078	51	0	0
T11	6003	252	0	0
T12	117829	448	0	0
T13	579606	1443	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	899116	0	0
GntImpliesValid_A	438663802	899116	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	899116	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	12532177	0	0
ReadyAndValidImplyGrant_A	438663802	899116	0	0
ReqAndReadyImplyGrant_A	438663802	899116	0	0
ReqImpliesValid_A	438663802	2512515	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	899116	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	899116	0	0
T1	8868	588	0	0
T2	13693	42	0	0
T3	4429	204	0	0
T7	389434	52	0	0
T8	355168	3040	0	0
T9	1771	58	0	0
T10	453078	56	0	0
T11	6003	257	0	0
T12	117829	453	0	0
T13	579606	1432	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	899116	0	0
T1	8868	588	0	0
T2	13693	42	0	0
T3	4429	204	0	0
T7	389434	52	0	0
T8	355168	3040	0	0
T9	1771	58	0	0
T10	453078	56	0	0
T11	6003	257	0	0
T12	117829	453	0	0
T13	579606	1432	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	899116	0	0
T1	8868	588	0	0
T2	13693	42	0	0
T3	4429	204	0	0
T7	389434	52	0	0
T8	355168	3040	0	0
T9	1771	58	0	0
T10	453078	56	0	0
T11	6003	257	0	0
T12	117829	453	0	0
T13	579606	1432	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	12532177	0	0
T1	8868	434	0	0
T2	13693	340	0	0
T3	4429	163	0	0
T7	389434	17220	0	0
T8	355168	22595	0	0
T9	1771	42	0	0
T10	453078	16368	0	0
T11	6003	215	0	0
T12	117829	1882	0	0
T13	579606	5258	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	899116	0	0
T1	8868	588	0	0
T2	13693	42	0	0
T3	4429	204	0	0
T7	389434	52	0	0
T8	355168	3040	0	0
T9	1771	58	0	0
T10	453078	56	0	0
T11	6003	257	0	0
T12	117829	453	0	0
T13	579606	1432	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	899116	0	0
T1	8868	588	0	0
T2	13693	42	0	0
T3	4429	204	0	0
T7	389434	52	0	0
T8	355168	3040	0	0
T9	1771	58	0	0
T10	453078	56	0	0
T11	6003	257	0	0
T12	117829	453	0	0
T13	579606	1432	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	2512515	0	0
T1	8868	743	0	0
T2	13693	64	0	0
T3	4429	246	0	0
T7	389434	578	0	0
T8	355168	4516	0	0
T9	1771	75	0	0
T10	453078	806	0	0
T11	6003	300	0	0
T12	117829	652	0	0
T13	579606	2793	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	899116	0	0
T1	8868	588	0	0
T2	13693	42	0	0
T3	4429	204	0	0
T7	389434	52	0	0
T8	355168	3040	0	0
T9	1771	58	0	0
T10	453078	56	0	0
T11	6003	257	0	0
T12	117829	453	0	0
T13	579606	1432	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	222446	0	0
GntImpliesValid_A	438663802	222446	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	222446	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	3248823	0	0
ReadyAndValidImplyGrant_A	438663802	222446	0	0
ReqAndReadyImplyGrant_A	438663802	222446	0	0
ReqImpliesValid_A	438663802	591595	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	222446	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	222446	0	0
T1	8868	137	0	0
T2	13693	21	0	0
T3	4429	54	0	0
T7	389434	3	0	0
T8	355168	929	0	0
T9	1771	14	0	0
T10	453078	13	0	0
T11	6003	59	0	0
T12	117829	96	0	0
T13	579606	0	0	0
T14	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	222446	0	0
T1	8868	137	0	0
T2	13693	21	0	0
T3	4429	54	0	0
T7	389434	3	0	0
T8	355168	929	0	0
T9	1771	14	0	0
T10	453078	13	0	0
T11	6003	59	0	0
T12	117829	96	0	0
T13	579606	0	0	0
T14	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	222446	0	0
T1	8868	137	0	0
T2	13693	21	0	0
T3	4429	54	0	0
T7	389434	3	0	0
T8	355168	929	0	0
T9	1771	14	0	0
T10	453078	13	0	0
T11	6003	59	0	0
T12	117829	96	0	0
T13	579606	0	0	0
T14	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	3248823	0	0
T1	8868	129	0	0
T2	13693	157	0	0
T3	4429	53	0	0
T7	389434	927	0	0
T8	355168	6664	0	0
T9	1771	15	0	0
T10	453078	4209	0	0
T11	6003	59	0	0
T12	117829	326	0	0
T13	579606	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	222446	0	0
T1	8868	137	0	0
T2	13693	21	0	0
T3	4429	54	0	0
T7	389434	3	0	0
T8	355168	929	0	0
T9	1771	14	0	0
T10	453078	13	0	0
T11	6003	59	0	0
T12	117829	96	0	0
T13	579606	0	0	0
T14	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	222446	0	0
T1	8868	137	0	0
T2	13693	21	0	0
T3	4429	54	0	0
T7	389434	3	0	0
T8	355168	929	0	0
T9	1771	14	0	0
T10	453078	13	0	0
T11	6003	59	0	0
T12	117829	96	0	0
T13	579606	0	0	0
T14	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	591595	0	0
T1	8868	146	0	0
T2	13693	28	0	0
T3	4429	56	0	0
T7	389434	3	0	0
T8	355168	1291	0	0
T9	1771	14	0	0
T10	453078	13	0	0
T11	6003	60	0	0
T12	117829	117	0	0
T13	579606	0	0	0
T14	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	222446	0	0
T1	8868	137	0	0
T2	13693	21	0	0
T3	4429	54	0	0
T7	389434	3	0	0
T8	355168	929	0	0
T9	1771	14	0	0
T10	453078	13	0	0
T11	6003	59	0	0
T12	117829	96	0	0
T13	579606	0	0	0
T14	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	229762	0	0
GntImpliesValid_A	438663802	229762	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	229762	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	3265869	0	0
ReadyAndValidImplyGrant_A	438663802	229762	0	0
ReqAndReadyImplyGrant_A	438663802	229762	0	0
ReqImpliesValid_A	438663802	629428	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	229762	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	229762	0	0
T1	8868	137	0	0
T2	13693	22	0	0
T3	4429	42	0	0
T7	389434	9	0	0
T8	355168	705	0	0
T9	1771	12	0	0
T10	453078	17	0	0
T11	6003	54	0	0
T12	117829	109	0	0
T13	579606	0	0	0
T14	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	229762	0	0
T1	8868	137	0	0
T2	13693	22	0	0
T3	4429	42	0	0
T7	389434	9	0	0
T8	355168	705	0	0
T9	1771	12	0	0
T10	453078	17	0	0
T11	6003	54	0	0
T12	117829	109	0	0
T13	579606	0	0	0
T14	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	229762	0	0
T1	8868	137	0	0
T2	13693	22	0	0
T3	4429	42	0	0
T7	389434	9	0	0
T8	355168	705	0	0
T9	1771	12	0	0
T10	453078	17	0	0
T11	6003	54	0	0
T12	117829	109	0	0
T13	579606	0	0	0
T14	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	3265869	0	0
T1	8868	129	0	0
T2	13693	215	0	0
T3	4429	42	0	0
T7	389434	4658	0	0
T8	355168	5342	0	0
T9	1771	13	0	0
T10	453078	4799	0	0
T11	6003	54	0	0
T12	117829	499	0	0
T13	579606	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	229762	0	0
T1	8868	137	0	0
T2	13693	22	0	0
T3	4429	42	0	0
T7	389434	9	0	0
T8	355168	705	0	0
T9	1771	12	0	0
T10	453078	17	0	0
T11	6003	54	0	0
T12	117829	109	0	0
T13	579606	0	0	0
T14	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	229762	0	0
T1	8868	137	0	0
T2	13693	22	0	0
T3	4429	42	0	0
T7	389434	9	0	0
T8	355168	705	0	0
T9	1771	12	0	0
T10	453078	17	0	0
T11	6003	54	0	0
T12	117829	109	0	0
T13	579606	0	0	0
T14	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	629428	0	0
T1	8868	146	0	0
T2	13693	44	0	0
T3	4429	43	0	0
T7	389434	9	0	0
T8	355168	831	0	0
T9	1771	12	0	0
T10	453078	247	0	0
T11	6003	55	0	0
T12	117829	127	0	0
T13	579606	0	0	0
T14	0	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	229762	0	0
T1	8868	137	0	0
T2	13693	22	0	0
T3	4429	42	0	0
T7	389434	9	0	0
T8	355168	705	0	0
T9	1771	12	0	0
T10	453078	17	0	0
T11	6003	54	0	0
T12	117829	109	0	0
T13	579606	0	0	0
T14	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	225563	0	0
GntImpliesValid_A	438663802	225563	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	225563	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	5642779	0	0
ReadyAndValidImplyGrant_A	438663802	225563	0	0
ReqAndReadyImplyGrant_A	438663802	225563	0	0
ReqImpliesValid_A	438663802	1328670	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	225563	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	225563	0	0
T1	8868	149	0	0
T2	13693	19	0	0
T3	4429	56	0	0
T7	389434	11	0	0
T8	355168	683	0	0
T9	1771	13	0	0
T10	453078	13	0	0
T11	6003	65	0	0
T12	117829	111	0	0
T13	579606	504	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	225563	0	0
T1	8868	149	0	0
T2	13693	19	0	0
T3	4429	56	0	0
T7	389434	11	0	0
T8	355168	683	0	0
T9	1771	13	0	0
T10	453078	13	0	0
T11	6003	65	0	0
T12	117829	111	0	0
T13	579606	504	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	225563	0	0
T1	8868	149	0	0
T2	13693	19	0	0
T3	4429	56	0	0
T7	389434	11	0	0
T8	355168	683	0	0
T9	1771	13	0	0
T10	453078	13	0	0
T11	6003	65	0	0
T12	117829	111	0	0
T13	579606	504	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	5642779	0	0
T1	8868	624	0	0
T2	13693	515	0	0
T3	4429	216	0	0
T7	389434	5023	0	0
T8	355168	29489	0	0
T9	1771	82	0	0
T10	453078	7675	0	0
T11	6003	265	0	0
T12	117829	969	0	0
T13	579606	6147	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	225563	0	0
T1	8868	149	0	0
T2	13693	19	0	0
T3	4429	56	0	0
T7	389434	11	0	0
T8	355168	683	0	0
T9	1771	13	0	0
T10	453078	13	0	0
T11	6003	65	0	0
T12	117829	111	0	0
T13	579606	504	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	225563	0	0
T1	8868	149	0	0
T2	13693	19	0	0
T3	4429	56	0	0
T7	389434	11	0	0
T8	355168	683	0	0
T9	1771	13	0	0
T10	453078	13	0	0
T11	6003	65	0	0
T12	117829	111	0	0
T13	579606	504	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	1328670	0	0
T1	8868	179	0	0
T2	13693	54	0	0
T3	4429	57	0	0
T7	389434	451	0	0
T8	355168	2255	0	0
T9	1771	13	0	0
T10	453078	149	0	0
T11	6003	87	0	0
T12	117829	172	0	0
T13	579606	3001	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	225563	0	0
T1	8868	149	0	0
T2	13693	19	0	0
T3	4429	56	0	0
T7	389434	11	0	0
T8	355168	683	0	0
T9	1771	13	0	0
T10	453078	13	0	0
T11	6003	65	0	0
T12	117829	111	0	0
T13	579606	504	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	219727	0	0
GntImpliesValid_A	438663802	219727	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	219727	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	6061978	0	0
ReadyAndValidImplyGrant_A	438663802	219727	0	0
ReqAndReadyImplyGrant_A	438663802	219727	0	0
ReqImpliesValid_A	438663802	1324237	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	219727	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	219727	0	0
T1	8868	141	0	0
T2	13693	17	0	0
T3	4429	72	0	0
T7	389434	18	0	0
T8	355168	745	0	0
T9	1771	15	0	0
T10	453078	14	0	0
T11	6003	62	0	0
T12	117829	107	0	0
T13	579606	511	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	219727	0	0
T1	8868	141	0	0
T2	13693	17	0	0
T3	4429	72	0	0
T7	389434	18	0	0
T8	355168	745	0	0
T9	1771	15	0	0
T10	453078	14	0	0
T11	6003	62	0	0
T12	117829	107	0	0
T13	579606	511	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	219727	0	0
T1	8868	141	0	0
T2	13693	17	0	0
T3	4429	72	0	0
T7	389434	18	0	0
T8	355168	745	0	0
T9	1771	15	0	0
T10	453078	14	0	0
T11	6003	62	0	0
T12	117829	107	0	0
T13	579606	511	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	6061978	0	0
T1	8868	556	0	0
T2	13693	261	0	0
T3	4429	260	0	0
T7	389434	4094	0	0
T8	355168	10857	0	0
T9	1771	53	0	0
T10	453078	3137	0	0
T11	6003	296	0	0
T12	117829	797	0	0
T13	579606	4145	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	219727	0	0
T1	8868	141	0	0
T2	13693	17	0	0
T3	4429	72	0	0
T7	389434	18	0	0
T8	355168	745	0	0
T9	1771	15	0	0
T10	453078	14	0	0
T11	6003	62	0	0
T12	117829	107	0	0
T13	579606	511	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	219727	0	0
T1	8868	141	0	0
T2	13693	17	0	0
T3	4429	72	0	0
T7	389434	18	0	0
T8	355168	745	0	0
T9	1771	15	0	0
T10	453078	14	0	0
T11	6003	62	0	0
T12	117829	107	0	0
T13	579606	511	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	1324237	0	0
T1	8868	177	0	0
T2	13693	34	0	0
T3	4429	93	0	0
T7	389434	292	0	0
T8	355168	1178	0	0
T9	1771	15	0	0
T10	453078	157	0	0
T11	6003	102	0	0
T12	117829	138	0	0
T13	579606	2135	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	219727	0	0
T1	8868	141	0	0
T2	13693	17	0	0
T3	4429	72	0	0
T7	389434	18	0	0
T8	355168	745	0	0
T9	1771	15	0	0
T10	453078	14	0	0
T11	6003	62	0	0
T12	117829	107	0	0
T13	579606	511	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	225821	0	0
GntImpliesValid_A	438663802	225821	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	225821	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	5829925	0	0
ReadyAndValidImplyGrant_A	438663802	225821	0	0
ReqAndReadyImplyGrant_A	438663802	225821	0	0
ReqImpliesValid_A	438663802	1303914	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	225821	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	225821	0	0
T1	8868	141	0	0
T2	13693	11	0	0
T3	4429	65	0	0
T7	389434	16	0	0
T8	355168	705	0	0
T9	1771	22	0	0
T10	453078	11	0	0
T11	6003	55	0	0
T12	117829	96	0	0
T13	579606	466	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	225821	0	0
T1	8868	141	0	0
T2	13693	11	0	0
T3	4429	65	0	0
T7	389434	16	0	0
T8	355168	705	0	0
T9	1771	22	0	0
T10	453078	11	0	0
T11	6003	55	0	0
T12	117829	96	0	0
T13	579606	466	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	225821	0	0
T1	8868	141	0	0
T2	13693	11	0	0
T3	4429	65	0	0
T7	389434	16	0	0
T8	355168	705	0	0
T9	1771	22	0	0
T10	453078	11	0	0
T11	6003	55	0	0
T12	117829	96	0	0
T13	579606	466	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	5829925	0	0
T1	8868	1125	0	0
T2	13693	103	0	0
T3	4429	192	0	0
T7	389434	3148	0	0
T8	355168	16154	0	0
T9	1771	66	0	0
T10	453078	5386	0	0
T11	6003	675	0	0
T12	117829	594	0	0
T13	579606	11069	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	225821	0	0
T1	8868	141	0	0
T2	13693	11	0	0
T3	4429	65	0	0
T7	389434	16	0	0
T8	355168	705	0	0
T9	1771	22	0	0
T10	453078	11	0	0
T11	6003	55	0	0
T12	117829	96	0	0
T13	579606	466	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	225821	0	0
T1	8868	141	0	0
T2	13693	11	0	0
T3	4429	65	0	0
T7	389434	16	0	0
T8	355168	705	0	0
T9	1771	22	0	0
T10	453078	11	0	0
T11	6003	55	0	0
T12	117829	96	0	0
T13	579606	466	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	1303914	0	0
T1	8868	206	0	0
T2	13693	11	0	0
T3	4429	93	0	0
T7	389434	798	0	0
T8	355168	1120	0	0
T9	1771	33	0	0
T10	453078	11	0	0
T11	6003	126	0	0
T12	117829	134	0	0
T13	579606	4979	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	225821	0	0
T1	8868	141	0	0
T2	13693	11	0	0
T3	4429	65	0	0
T7	389434	16	0	0
T8	355168	705	0	0
T9	1771	22	0	0
T10	453078	11	0	0
T11	6003	55	0	0
T12	117829	96	0	0
T13	579606	466	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	218827	0	0
GntImpliesValid_A	438663802	218827	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	218827	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	5431428	0	0
ReadyAndValidImplyGrant_A	438663802	218827	0	0
ReqAndReadyImplyGrant_A	438663802	218827	0	0
ReqImpliesValid_A	438663802	1105388	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	218827	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	218827	0	0
T1	8868	125	0	0
T2	13693	16	0	0
T3	4429	56	0	0
T7	389434	10	0	0
T8	355168	724	0	0
T9	1771	19	0	0
T10	453078	6	0	0
T11	6003	55	0	0
T12	117829	113	0	0
T13	579606	0	0	0
T14	0	26	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	218827	0	0
T1	8868	125	0	0
T2	13693	16	0	0
T3	4429	56	0	0
T7	389434	10	0	0
T8	355168	724	0	0
T9	1771	19	0	0
T10	453078	6	0	0
T11	6003	55	0	0
T12	117829	113	0	0
T13	579606	0	0	0
T14	0	26	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	218827	0	0
T1	8868	125	0	0
T2	13693	16	0	0
T3	4429	56	0	0
T7	389434	10	0	0
T8	355168	724	0	0
T9	1771	19	0	0
T10	453078	6	0	0
T11	6003	55	0	0
T12	117829	113	0	0
T13	579606	0	0	0
T14	0	26	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	5431428	0	0
T1	8868	1445	0	0
T2	13693	79	0	0
T3	4429	225	0	0
T7	389434	6192	0	0
T8	355168	12697	0	0
T9	1771	62	0	0
T10	453078	675	0	0
T11	6003	552	0	0
T12	117829	800	0	0
T13	579606	0	0	0
T14	0	144	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	218827	0	0
T1	8868	125	0	0
T2	13693	16	0	0
T3	4429	56	0	0
T7	389434	10	0	0
T8	355168	724	0	0
T9	1771	19	0	0
T10	453078	6	0	0
T11	6003	55	0	0
T12	117829	113	0	0
T13	579606	0	0	0
T14	0	26	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	218827	0	0
T1	8868	125	0	0
T2	13693	16	0	0
T3	4429	56	0	0
T7	389434	10	0	0
T8	355168	724	0	0
T9	1771	19	0	0
T10	453078	6	0	0
T11	6003	55	0	0
T12	117829	113	0	0
T13	579606	0	0	0
T14	0	26	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	1105388	0	0
T1	8868	317	0	0
T2	13693	20	0	0
T3	4429	79	0	0
T7	389434	986	0	0
T8	355168	1083	0	0
T9	1771	23	0	0
T10	453078	6	0	0
T11	6003	117	0	0
T12	117829	179	0	0
T13	579606	0	0	0
T14	0	33	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	218827	0	0
T1	8868	125	0	0
T2	13693	16	0	0
T3	4429	56	0	0
T7	389434	10	0	0
T8	355168	724	0	0
T9	1771	19	0	0
T10	453078	6	0	0
T11	6003	55	0	0
T12	117829	113	0	0
T13	579606	0	0	0
T14	0	26	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	226934	0	0
GntImpliesValid_A	438663802	226934	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	226934	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	3167740	0	0
ReadyAndValidImplyGrant_A	438663802	226934	0	0
ReqAndReadyImplyGrant_A	438663802	226934	0	0
ReqImpliesValid_A	438663802	539269	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	226934	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	226934	0	0
T1	8868	142	0	0
T2	13693	13	0	0
T3	4429	42	0	0
T7	389434	8	0	0
T8	355168	765	0	0
T9	1771	4	0	0
T10	453078	9	0	0
T11	6003	50	0	0
T12	117829	92	0	0
T13	579606	493	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	226934	0	0
T1	8868	142	0	0
T2	13693	13	0	0
T3	4429	42	0	0
T7	389434	8	0	0
T8	355168	765	0	0
T9	1771	4	0	0
T10	453078	9	0	0
T11	6003	50	0	0
T12	117829	92	0	0
T13	579606	493	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	226934	0	0
T1	8868	142	0	0
T2	13693	13	0	0
T3	4429	42	0	0
T7	389434	8	0	0
T8	355168	765	0	0
T9	1771	4	0	0
T10	453078	9	0	0
T11	6003	50	0	0
T12	117829	92	0	0
T13	579606	493	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	3167740	0	0
T1	8868	133	0	0
T2	13693	90	0	0
T3	4429	43	0	0
T7	389434	2473	0	0
T8	355168	5666	0	0
T9	1771	5	0	0
T10	453078	2468	0	0
T11	6003	49	0	0
T12	117829	405	0	0
T13	579606	1562	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	226934	0	0
T1	8868	142	0	0
T2	13693	13	0	0
T3	4429	42	0	0
T7	389434	8	0	0
T8	355168	765	0	0
T9	1771	4	0	0
T10	453078	9	0	0
T11	6003	50	0	0
T12	117829	92	0	0
T13	579606	493	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	226934	0	0
T1	8868	142	0	0
T2	13693	13	0	0
T3	4429	42	0	0
T7	389434	8	0	0
T8	355168	765	0	0
T9	1771	4	0	0
T10	453078	9	0	0
T11	6003	50	0	0
T12	117829	92	0	0
T13	579606	493	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	539269	0	0
T1	8868	152	0	0
T2	13693	13	0	0
T3	4429	42	0	0
T7	389434	387	0	0
T8	355168	871	0	0
T9	1771	4	0	0
T10	453078	9	0	0
T11	6003	52	0	0
T12	117829	116	0	0
T13	579606	1222	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	226934	0	0
T1	8868	142	0	0
T2	13693	13	0	0
T3	4429	42	0	0
T7	389434	8	0	0
T8	355168	765	0	0
T9	1771	4	0	0
T10	453078	9	0	0
T11	6003	50	0	0
T12	117829	92	0	0
T13	579606	493	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	221092	0	0
GntImpliesValid_A	438663802	221092	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	221092	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	3212864	0	0
ReadyAndValidImplyGrant_A	438663802	221092	0	0
ReqAndReadyImplyGrant_A	438663802	221092	0	0
ReqImpliesValid_A	438663802	562144	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	221092	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	221092	0	0
T1	8868	143	0	0
T2	13693	16	0	0
T3	4429	51	0	0
T7	389434	10	0	0
T8	355168	713	0	0
T9	1771	14	0	0
T10	453078	14	0	0
T11	6003	76	0	0
T12	117829	95	0	0
T13	579606	544	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	221092	0	0
T1	8868	143	0	0
T2	13693	16	0	0
T3	4429	51	0	0
T7	389434	10	0	0
T8	355168	713	0	0
T9	1771	14	0	0
T10	453078	14	0	0
T11	6003	76	0	0
T12	117829	95	0	0
T13	579606	544	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	221092	0	0
T1	8868	143	0	0
T2	13693	16	0	0
T3	4429	51	0	0
T7	389434	10	0	0
T8	355168	713	0	0
T9	1771	14	0	0
T10	453078	14	0	0
T11	6003	76	0	0
T12	117829	95	0	0
T13	579606	544	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	3212864	0	0
T1	8868	136	0	0
T2	13693	57	0	0
T3	4429	51	0	0
T7	389434	3148	0	0
T8	355168	5182	0	0
T9	1771	14	0	0
T10	453078	5170	0	0
T11	6003	73	0	0
T12	117829	421	0	0
T13	579606	1852	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	221092	0	0
T1	8868	143	0	0
T2	13693	16	0	0
T3	4429	51	0	0
T7	389434	10	0	0
T8	355168	713	0	0
T9	1771	14	0	0
T10	453078	14	0	0
T11	6003	76	0	0
T12	117829	95	0	0
T13	579606	544	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	221092	0	0
T1	8868	143	0	0
T2	13693	16	0	0
T3	4429	51	0	0
T7	389434	10	0	0
T8	355168	713	0	0
T9	1771	14	0	0
T10	453078	14	0	0
T11	6003	76	0	0
T12	117829	95	0	0
T13	579606	544	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	562144	0	0
T1	8868	151	0	0
T2	13693	37	0	0
T3	4429	52	0	0
T7	389434	77	0	0
T8	355168	877	0	0
T9	1771	15	0	0
T10	453078	14	0	0
T11	6003	80	0	0
T12	117829	125	0	0
T13	579606	1236	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	221092	0	0
T1	8868	143	0	0
T2	13693	16	0	0
T3	4429	51	0	0
T7	389434	10	0	0
T8	355168	713	0	0
T9	1771	14	0	0
T10	453078	14	0	0
T11	6003	76	0	0
T12	117829	95	0	0
T13	579606	544	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	238645	0	0
GntImpliesValid_A	438663802	238645	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	238645	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	3242663	0	0
ReadyAndValidImplyGrant_A	438663802	238645	0	0
ReqAndReadyImplyGrant_A	438663802	238645	0	0
ReqImpliesValid_A	438663802	641469	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	238645	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	238645	0	0
T1	8868	128	0	0
T2	13693	12	0	0
T3	4429	49	0	0
T7	389434	11	0	0
T8	355168	739	0	0
T9	1771	16	0	0
T10	453078	14	0	0
T11	6003	52	0	0
T12	117829	106	0	0
T13	579606	510	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	238645	0	0
T1	8868	128	0	0
T2	13693	12	0	0
T3	4429	49	0	0
T7	389434	11	0	0
T8	355168	739	0	0
T9	1771	16	0	0
T10	453078	14	0	0
T11	6003	52	0	0
T12	117829	106	0	0
T13	579606	510	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	238645	0	0
T1	8868	128	0	0
T2	13693	12	0	0
T3	4429	49	0	0
T7	389434	11	0	0
T8	355168	739	0	0
T9	1771	16	0	0
T10	453078	14	0	0
T11	6003	52	0	0
T12	117829	106	0	0
T13	579606	510	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	3242663	0	0
T1	8868	120	0	0
T2	13693	102	0	0
T3	4429	49	0	0
T7	389434	2538	0	0
T8	355168	5582	0	0
T9	1771	15	0	0
T10	453078	4098	0	0
T11	6003	52	0	0
T12	117829	442	0	0
T13	579606	1632	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	238645	0	0
T1	8868	128	0	0
T2	13693	12	0	0
T3	4429	49	0	0
T7	389434	11	0	0
T8	355168	739	0	0
T9	1771	16	0	0
T10	453078	14	0	0
T11	6003	52	0	0
T12	117829	106	0	0
T13	579606	510	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	238645	0	0
T1	8868	128	0	0
T2	13693	12	0	0
T3	4429	49	0	0
T7	389434	11	0	0
T8	355168	739	0	0
T9	1771	16	0	0
T10	453078	14	0	0
T11	6003	52	0	0
T12	117829	106	0	0
T13	579606	510	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	641469	0	0
T1	8868	137	0	0
T2	13693	12	0	0
T3	4429	50	0	0
T7	389434	11	0	0
T8	355168	865	0	0
T9	1771	18	0	0
T10	453078	16	0	0
T11	6003	53	0	0
T12	117829	124	0	0
T13	579606	1110	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	238645	0	0
T1	8868	128	0	0
T2	13693	12	0	0
T3	4429	49	0	0
T7	389434	11	0	0
T8	355168	739	0	0
T9	1771	16	0	0
T10	453078	14	0	0
T11	6003	52	0	0
T12	117829	106	0	0
T13	579606	510	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	212962	0	0
GntImpliesValid_A	438663802	212962	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	212962	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	3186064	0	0
ReadyAndValidImplyGrant_A	438663802	212962	0	0
ReqAndReadyImplyGrant_A	438663802	212962	0	0
ReqImpliesValid_A	438663802	523698	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	212962	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	212962	0	0
T1	8868	138	0	0
T2	13693	15	0	0
T3	4429	50	0	0
T7	389434	6	0	0
T8	355168	724	0	0
T9	1771	4	0	0
T10	453078	7	0	0
T11	6003	53	0	0
T12	117829	98	0	0
T13	579606	416	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	212962	0	0
T1	8868	138	0	0
T2	13693	15	0	0
T3	4429	50	0	0
T7	389434	6	0	0
T8	355168	724	0	0
T9	1771	4	0	0
T10	453078	7	0	0
T11	6003	53	0	0
T12	117829	98	0	0
T13	579606	416	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	212962	0	0
T1	8868	138	0	0
T2	13693	15	0	0
T3	4429	50	0	0
T7	389434	6	0	0
T8	355168	724	0	0
T9	1771	4	0	0
T10	453078	7	0	0
T11	6003	53	0	0
T12	117829	98	0	0
T13	579606	416	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	3186064	0	0
T1	8868	134	0	0
T2	13693	127	0	0
T3	4429	48	0	0
T7	389434	1849	0	0
T8	355168	5471	0	0
T9	1771	5	0	0
T10	453078	1802	0	0
T11	6003	49	0	0
T12	117829	401	0	0
T13	579606	1316	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	212962	0	0
T1	8868	138	0	0
T2	13693	15	0	0
T3	4429	50	0	0
T7	389434	6	0	0
T8	355168	724	0	0
T9	1771	4	0	0
T10	453078	7	0	0
T11	6003	53	0	0
T12	117829	98	0	0
T13	579606	416	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	212962	0	0
T1	8868	138	0	0
T2	13693	15	0	0
T3	4429	50	0	0
T7	389434	6	0	0
T8	355168	724	0	0
T9	1771	4	0	0
T10	453078	7	0	0
T11	6003	53	0	0
T12	117829	98	0	0
T13	579606	416	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	523698	0	0
T1	8868	143	0	0
T2	13693	15	0	0
T3	4429	53	0	0
T7	389434	609	0	0
T8	355168	886	0	0
T9	1771	4	0	0
T10	453078	7	0	0
T11	6003	58	0	0
T12	117829	104	0	0
T13	579606	1016	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	212962	0	0
T1	8868	138	0	0
T2	13693	15	0	0
T3	4429	50	0	0
T7	389434	6	0	0
T8	355168	724	0	0
T9	1771	4	0	0
T10	453078	7	0	0
T11	6003	53	0	0
T12	117829	98	0	0
T13	579606	416	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	223026	0	0
GntImpliesValid_A	438663802	223026	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	223026	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	3231428	0	0
ReadyAndValidImplyGrant_A	438663802	223026	0	0
ReqAndReadyImplyGrant_A	438663802	223026	0	0
ReqImpliesValid_A	438663802	555890	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	223026	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	223026	0	0
T1	8868	134	0	0
T2	13693	11	0	0
T3	4429	50	0	0
T7	389434	10	0	0
T8	355168	759	0	0
T9	1771	10	0	0
T10	453078	17	0	0
T11	6003	58	0	0
T12	117829	131	0	0
T13	579606	0	0	0
T14	0	477	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	223026	0	0
T1	8868	134	0	0
T2	13693	11	0	0
T3	4429	50	0	0
T7	389434	10	0	0
T8	355168	759	0	0
T9	1771	10	0	0
T10	453078	17	0	0
T11	6003	58	0	0
T12	117829	131	0	0
T13	579606	0	0	0
T14	0	477	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	223026	0	0
T1	8868	134	0	0
T2	13693	11	0	0
T3	4429	50	0	0
T7	389434	10	0	0
T8	355168	759	0	0
T9	1771	10	0	0
T10	453078	17	0	0
T11	6003	58	0	0
T12	117829	131	0	0
T13	579606	0	0	0
T14	0	477	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	3231428	0	0
T1	8868	130	0	0
T2	13693	91	0	0
T3	4429	48	0	0
T7	389434	3314	0	0
T8	355168	5436	0	0
T9	1771	10	0	0
T10	453078	5245	0	0
T11	6003	57	0	0
T12	117829	589	0	0
T13	579606	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	223026	0	0
T1	8868	134	0	0
T2	13693	11	0	0
T3	4429	50	0	0
T7	389434	10	0	0
T8	355168	759	0	0
T9	1771	10	0	0
T10	453078	17	0	0
T11	6003	58	0	0
T12	117829	131	0	0
T13	579606	0	0	0
T14	0	477	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	223026	0	0
T1	8868	134	0	0
T2	13693	11	0	0
T3	4429	50	0	0
T7	389434	10	0	0
T8	355168	759	0	0
T9	1771	10	0	0
T10	453078	17	0	0
T11	6003	58	0	0
T12	117829	131	0	0
T13	579606	0	0	0
T14	0	477	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	555890	0	0
T1	8868	139	0	0
T2	13693	11	0	0
T3	4429	53	0	0
T7	389434	10	0	0
T8	355168	1094	0	0
T9	1771	11	0	0
T10	453078	306	0	0
T11	6003	60	0	0
T12	117829	156	0	0
T13	579606	0	0	0
T14	0	4412	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	223026	0	0
T1	8868	134	0	0
T2	13693	11	0	0
T3	4429	50	0	0
T7	389434	10	0	0
T8	355168	759	0	0
T9	1771	10	0	0
T10	453078	17	0	0
T11	6003	58	0	0
T12	117829	131	0	0
T13	579606	0	0	0
T14	0	477	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	219630	0	0
GntImpliesValid_A	438663802	219630	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	219630	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	3234584	0	0
ReadyAndValidImplyGrant_A	438663802	219630	0	0
ReqAndReadyImplyGrant_A	438663802	219630	0	0
ReqImpliesValid_A	438663802	506991	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	219630	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	219630	0	0
T1	8868	127	0	0
T2	13693	16	0	0
T3	4429	43	0	0
T7	389434	10	0	0
T8	355168	734	0	0
T9	1771	11	0	0
T10	453078	8	0	0
T11	6003	62	0	0
T12	117829	107	0	0
T13	579606	0	0	0
T14	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	219630	0	0
T1	8868	127	0	0
T2	13693	16	0	0
T3	4429	43	0	0
T7	389434	10	0	0
T8	355168	734	0	0
T9	1771	11	0	0
T10	453078	8	0	0
T11	6003	62	0	0
T12	117829	107	0	0
T13	579606	0	0	0
T14	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	219630	0	0
T1	8868	127	0	0
T2	13693	16	0	0
T3	4429	43	0	0
T7	389434	10	0	0
T8	355168	734	0	0
T9	1771	11	0	0
T10	453078	8	0	0
T11	6003	62	0	0
T12	117829	107	0	0
T13	579606	0	0	0
T14	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	3234584	0	0
T1	8868	122	0	0
T2	13693	110	0	0
T3	4429	43	0	0
T7	389434	1701	0	0
T8	355168	5520	0	0
T9	1771	12	0	0
T10	453078	2409	0	0
T11	6003	61	0	0
T12	117829	454	0	0
T13	579606	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	219630	0	0
T1	8868	127	0	0
T2	13693	16	0	0
T3	4429	43	0	0
T7	389434	10	0	0
T8	355168	734	0	0
T9	1771	11	0	0
T10	453078	8	0	0
T11	6003	62	0	0
T12	117829	107	0	0
T13	579606	0	0	0
T14	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	219630	0	0
T1	8868	127	0	0
T2	13693	16	0	0
T3	4429	43	0	0
T7	389434	10	0	0
T8	355168	734	0	0
T9	1771	11	0	0
T10	453078	8	0	0
T11	6003	62	0	0
T12	117829	107	0	0
T13	579606	0	0	0
T14	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	506991	0	0
T1	8868	133	0	0
T2	13693	16	0	0
T3	4429	44	0	0
T7	389434	623	0	0
T8	355168	804	0	0
T9	1771	11	0	0
T10	453078	8	0	0
T11	6003	64	0	0
T12	117829	118	0	0
T13	579606	0	0	0
T14	0	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	219630	0	0
T1	8868	127	0	0
T2	13693	16	0	0
T3	4429	43	0	0
T7	389434	10	0	0
T8	355168	734	0	0
T9	1771	11	0	0
T10	453078	8	0	0
T11	6003	62	0	0
T12	117829	107	0	0
T13	579606	0	0	0
T14	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	226269	0	0
GntImpliesValid_A	438663802	226269	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	226269	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	3212494	0	0
ReadyAndValidImplyGrant_A	438663802	226269	0	0
ReqAndReadyImplyGrant_A	438663802	226269	0	0
ReqImpliesValid_A	438663802	564843	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	226269	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	226269	0	0
T1	8868	147	0	0
T2	13693	14	0	0
T3	4429	44	0	0
T7	389434	7	0	0
T8	355168	706	0	0
T9	1771	18	0	0
T10	453078	11	0	0
T11	6003	63	0	0
T12	117829	92	0	0
T13	579606	449	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	226269	0	0
T1	8868	147	0	0
T2	13693	14	0	0
T3	4429	44	0	0
T7	389434	7	0	0
T8	355168	706	0	0
T9	1771	18	0	0
T10	453078	11	0	0
T11	6003	63	0	0
T12	117829	92	0	0
T13	579606	449	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	226269	0	0
T1	8868	147	0	0
T2	13693	14	0	0
T3	4429	44	0	0
T7	389434	7	0	0
T8	355168	706	0	0
T9	1771	18	0	0
T10	453078	11	0	0
T11	6003	63	0	0
T12	117829	92	0	0
T13	579606	449	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	3212494	0	0
T1	8868	139	0	0
T2	13693	85	0	0
T3	4429	45	0	0
T7	389434	2038	0	0
T8	355168	5323	0	0
T9	1771	19	0	0
T10	453078	3450	0	0
T11	6003	61	0	0
T12	117829	371	0	0
T13	579606	1399	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	226269	0	0
T1	8868	147	0	0
T2	13693	14	0	0
T3	4429	44	0	0
T7	389434	7	0	0
T8	355168	706	0	0
T9	1771	18	0	0
T10	453078	11	0	0
T11	6003	63	0	0
T12	117829	92	0	0
T13	579606	449	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	226269	0	0
T1	8868	147	0	0
T2	13693	14	0	0
T3	4429	44	0	0
T7	389434	7	0	0
T8	355168	706	0	0
T9	1771	18	0	0
T10	453078	11	0	0
T11	6003	63	0	0
T12	117829	92	0	0
T13	579606	449	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	564843	0	0
T1	8868	156	0	0
T2	13693	30	0	0
T3	4429	44	0	0
T7	389434	7	0	0
T8	355168	852	0	0
T9	1771	18	0	0
T10	453078	11	0	0
T11	6003	66	0	0
T12	117829	111	0	0
T13	579606	1077	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	226269	0	0
T1	8868	147	0	0
T2	13693	14	0	0
T3	4429	44	0	0
T7	389434	7	0	0
T8	355168	706	0	0
T9	1771	18	0	0
T10	453078	11	0	0
T11	6003	63	0	0
T12	117829	92	0	0
T13	579606	449	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	217518	0	0
GntImpliesValid_A	438663802	217518	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	217518	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	3202144	0	0
ReadyAndValidImplyGrant_A	438663802	217518	0	0
ReqAndReadyImplyGrant_A	438663802	217518	0	0
ReqImpliesValid_A	438663802	568151	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	217518	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	217518	0	0
T1	8868	136	0	0
T2	13693	11	0	0
T3	4429	52	0	0
T7	389434	14	0	0
T8	355168	743	0	0
T9	1771	20	0	0
T10	453078	9	0	0
T11	6003	49	0	0
T12	117829	98	0	0
T13	579606	0	0	0
T14	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	217518	0	0
T1	8868	136	0	0
T2	13693	11	0	0
T3	4429	52	0	0
T7	389434	14	0	0
T8	355168	743	0	0
T9	1771	20	0	0
T10	453078	9	0	0
T11	6003	49	0	0
T12	117829	98	0	0
T13	579606	0	0	0
T14	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	217518	0	0
T1	8868	136	0	0
T2	13693	11	0	0
T3	4429	52	0	0
T7	389434	14	0	0
T8	355168	743	0	0
T9	1771	20	0	0
T10	453078	9	0	0
T11	6003	49	0	0
T12	117829	98	0	0
T13	579606	0	0	0
T14	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	3202144	0	0
T1	8868	132	0	0
T2	13693	57	0	0
T3	4429	48	0	0
T7	389434	5189	0	0
T8	355168	5989	0	0
T9	1771	19	0	0
T10	453078	2830	0	0
T11	6003	49	0	0
T12	117829	400	0	0
T13	579606	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	217518	0	0
T1	8868	136	0	0
T2	13693	11	0	0
T3	4429	52	0	0
T7	389434	14	0	0
T8	355168	743	0	0
T9	1771	20	0	0
T10	453078	9	0	0
T11	6003	49	0	0
T12	117829	98	0	0
T13	579606	0	0	0
T14	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	217518	0	0
T1	8868	136	0	0
T2	13693	11	0	0
T3	4429	52	0	0
T7	389434	14	0	0
T8	355168	743	0	0
T9	1771	20	0	0
T10	453078	9	0	0
T11	6003	49	0	0
T12	117829	98	0	0
T13	579606	0	0	0
T14	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	568151	0	0
T1	8868	141	0	0
T2	13693	11	0	0
T3	4429	57	0	0
T7	389434	992	0	0
T8	355168	857	0	0
T9	1771	22	0	0
T10	453078	9	0	0
T11	6003	50	0	0
T12	117829	140	0	0
T13	579606	0	0	0
T14	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	217518	0	0
T1	8868	136	0	0
T2	13693	11	0	0
T3	4429	52	0	0
T7	389434	14	0	0
T8	355168	743	0	0
T9	1771	20	0	0
T10	453078	9	0	0
T11	6003	49	0	0
T12	117829	98	0	0
T13	579606	0	0	0
T14	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	238207	0	0
GntImpliesValid_A	438663802	238207	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	238207	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	3282814	0	0
ReadyAndValidImplyGrant_A	438663802	238207	0	0
ReqAndReadyImplyGrant_A	438663802	238207	0	0
ReqImpliesValid_A	438663802	607112	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	238207	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	238207	0	0
T1	8868	140	0	0
T2	13693	17	0	0
T3	4429	80	0	0
T7	389434	13	0	0
T8	355168	755	0	0
T9	1771	15	0	0
T10	453078	15	0	0
T11	6003	116	0	0
T12	117829	111	0	0
T13	579606	537	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	238207	0	0
T1	8868	140	0	0
T2	13693	17	0	0
T3	4429	80	0	0
T7	389434	13	0	0
T8	355168	755	0	0
T9	1771	15	0	0
T10	453078	15	0	0
T11	6003	116	0	0
T12	117829	111	0	0
T13	579606	537	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	238207	0	0
T1	8868	140	0	0
T2	13693	17	0	0
T3	4429	80	0	0
T7	389434	13	0	0
T8	355168	755	0	0
T9	1771	15	0	0
T10	453078	15	0	0
T11	6003	116	0	0
T12	117829	111	0	0
T13	579606	537	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	3282814	0	0
T1	8868	136	0	0
T2	13693	135	0	0
T3	4429	79	0	0
T7	389434	5495	0	0
T8	355168	5824	0	0
T9	1771	12	0	0
T10	453078	5553	0	0
T11	6003	112	0	0
T12	117829	447	0	0
T13	579606	1915	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	238207	0	0
T1	8868	140	0	0
T2	13693	17	0	0
T3	4429	80	0	0
T7	389434	13	0	0
T8	355168	755	0	0
T9	1771	15	0	0
T10	453078	15	0	0
T11	6003	116	0	0
T12	117829	111	0	0
T13	579606	537	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	238207	0	0
T1	8868	140	0	0
T2	13693	17	0	0
T3	4429	80	0	0
T7	389434	13	0	0
T8	355168	755	0	0
T9	1771	15	0	0
T10	453078	15	0	0
T11	6003	116	0	0
T12	117829	111	0	0
T13	579606	537	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	607112	0	0
T1	8868	145	0	0
T2	13693	28	0	0
T3	4429	82	0	0
T7	389434	39	0	0
T8	355168	890	0	0
T9	1771	19	0	0
T10	453078	15	0	0
T11	6003	121	0	0
T12	117829	147	0	0
T13	579606	1311	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	238207	0	0
T1	8868	140	0	0
T2	13693	17	0	0
T3	4429	80	0	0
T7	389434	13	0	0
T8	355168	755	0	0
T9	1771	15	0	0
T10	453078	15	0	0
T11	6003	116	0	0
T12	117829	111	0	0
T13	579606	537	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	221473	0	0
GntImpliesValid_A	438663802	221473	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	221473	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	3217987	0	0
ReadyAndValidImplyGrant_A	438663802	221473	0	0
ReqAndReadyImplyGrant_A	438663802	221473	0	0
ReqImpliesValid_A	438663802	575080	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	221473	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	221473	0	0
T1	8868	132	0	0
T2	13693	21	0	0
T3	4429	56	0	0
T7	389434	7	0	0
T8	355168	794	0	0
T9	1771	6	0	0
T10	453078	10	0	0
T11	6003	65	0	0
T12	117829	112	0	0
T13	579606	469	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	221473	0	0
T1	8868	132	0	0
T2	13693	21	0	0
T3	4429	56	0	0
T7	389434	7	0	0
T8	355168	794	0	0
T9	1771	6	0	0
T10	453078	10	0	0
T11	6003	65	0	0
T12	117829	112	0	0
T13	579606	469	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	221473	0	0
T1	8868	132	0	0
T2	13693	21	0	0
T3	4429	56	0	0
T7	389434	7	0	0
T8	355168	794	0	0
T9	1771	6	0	0
T10	453078	10	0	0
T11	6003	65	0	0
T12	117829	112	0	0
T13	579606	469	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	3217987	0	0
T1	8868	128	0	0
T2	13693	174	0	0
T3	4429	54	0	0
T7	389434	1667	0	0
T8	355168	5846	0	0
T9	1771	7	0	0
T10	453078	2860	0	0
T11	6003	60	0	0
T12	117829	455	0	0
T13	579606	1517	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	221473	0	0
T1	8868	132	0	0
T2	13693	21	0	0
T3	4429	56	0	0
T7	389434	7	0	0
T8	355168	794	0	0
T9	1771	6	0	0
T10	453078	10	0	0
T11	6003	65	0	0
T12	117829	112	0	0
T13	579606	469	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	221473	0	0
T1	8868	132	0	0
T2	13693	21	0	0
T3	4429	56	0	0
T7	389434	7	0	0
T8	355168	794	0	0
T9	1771	6	0	0
T10	453078	10	0	0
T11	6003	65	0	0
T12	117829	112	0	0
T13	579606	469	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	575080	0	0
T1	8868	137	0	0
T2	13693	21	0	0
T3	4429	59	0	0
T7	389434	129	0	0
T8	355168	888	0	0
T9	1771	6	0	0
T10	453078	10	0	0
T11	6003	71	0	0
T12	117829	133	0	0
T13	579606	1221	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	221473	0	0
T1	8868	132	0	0
T2	13693	21	0	0
T3	4429	56	0	0
T7	389434	7	0	0
T8	355168	794	0	0
T9	1771	6	0	0
T10	453078	10	0	0
T11	6003	65	0	0
T12	117829	112	0	0
T13	579606	469	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	225275	0	0
GntImpliesValid_A	438663802	225275	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	225275	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	3237862	0	0
ReadyAndValidImplyGrant_A	438663802	225275	0	0
ReqAndReadyImplyGrant_A	438663802	225275	0	0
ReqImpliesValid_A	438663802	578091	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	225275	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	225275	0	0
T1	8868	122	0	0
T2	13693	12	0	0
T3	4429	46	0	0
T7	389434	13	0	0
T8	355168	736	0	0
T9	1771	12	0	0
T10	453078	20	0	0
T11	6003	56	0	0
T12	117829	116	0	0
T13	579606	522	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	225275	0	0
T1	8868	122	0	0
T2	13693	12	0	0
T3	4429	46	0	0
T7	389434	13	0	0
T8	355168	736	0	0
T9	1771	12	0	0
T10	453078	20	0	0
T11	6003	56	0	0
T12	117829	116	0	0
T13	579606	522	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	225275	0	0
T1	8868	122	0	0
T2	13693	12	0	0
T3	4429	46	0	0
T7	389434	13	0	0
T8	355168	736	0	0
T9	1771	12	0	0
T10	453078	20	0	0
T11	6003	56	0	0
T12	117829	116	0	0
T13	579606	522	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	3237862	0	0
T1	8868	120	0	0
T2	13693	107	0	0
T3	4429	46	0	0
T7	389434	4514	0	0
T8	355168	5598	0	0
T9	1771	13	0	0
T10	453078	4662	0	0
T11	6003	55	0	0
T12	117829	483	0	0
T13	579606	1712	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	225275	0	0
T1	8868	122	0	0
T2	13693	12	0	0
T3	4429	46	0	0
T7	389434	13	0	0
T8	355168	736	0	0
T9	1771	12	0	0
T10	453078	20	0	0
T11	6003	56	0	0
T12	117829	116	0	0
T13	579606	522	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	225275	0	0
T1	8868	122	0	0
T2	13693	12	0	0
T3	4429	46	0	0
T7	389434	13	0	0
T8	355168	736	0	0
T9	1771	12	0	0
T10	453078	20	0	0
T11	6003	56	0	0
T12	117829	116	0	0
T13	579606	522	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	578091	0	0
T1	8868	125	0	0
T2	13693	25	0	0
T3	4429	47	0	0
T7	389434	13	0	0
T8	355168	828	0	0
T9	1771	12	0	0
T10	453078	194	0	0
T11	6003	58	0	0
T12	117829	158	0	0
T13	579606	1246	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	225275	0	0
T1	8868	122	0	0
T2	13693	12	0	0
T3	4429	46	0	0
T7	389434	13	0	0
T8	355168	736	0	0
T9	1771	12	0	0
T10	453078	20	0	0
T11	6003	56	0	0
T12	117829	116	0	0
T13	579606	522	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	213031	0	0
GntImpliesValid_A	438663802	213031	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	213031	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	3184251	0	0
ReadyAndValidImplyGrant_A	438663802	213031	0	0
ReqAndReadyImplyGrant_A	438663802	213031	0	0
ReqImpliesValid_A	438663802	535162	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	213031	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	213031	0	0
T1	8868	145	0	0
T2	13693	20	0	0
T3	4429	53	0	0
T7	389434	7	0	0
T8	355168	815	0	0
T9	1771	13	0	0
T10	453078	15	0	0
T11	6003	58	0	0
T12	117829	111	0	0
T13	579606	0	0	0
T14	0	1007	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	213031	0	0
T1	8868	145	0	0
T2	13693	20	0	0
T3	4429	53	0	0
T7	389434	7	0	0
T8	355168	815	0	0
T9	1771	13	0	0
T10	453078	15	0	0
T11	6003	58	0	0
T12	117829	111	0	0
T13	579606	0	0	0
T14	0	1007	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	213031	0	0
T1	8868	145	0	0
T2	13693	20	0	0
T3	4429	53	0	0
T7	389434	7	0	0
T8	355168	815	0	0
T9	1771	13	0	0
T10	453078	15	0	0
T11	6003	58	0	0
T12	117829	111	0	0
T13	579606	0	0	0
T14	0	1007	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	3184251	0	0
T1	8868	141	0	0
T2	13693	138	0	0
T3	4429	51	0	0
T7	389434	2355	0	0
T8	355168	6062	0	0
T9	1771	14	0	0
T10	453078	5267	0	0
T11	6003	56	0	0
T12	117829	484	0	0
T13	579606	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	213031	0	0
T1	8868	145	0	0
T2	13693	20	0	0
T3	4429	53	0	0
T7	389434	7	0	0
T8	355168	815	0	0
T9	1771	13	0	0
T10	453078	15	0	0
T11	6003	58	0	0
T12	117829	111	0	0
T13	579606	0	0	0
T14	0	1007	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	213031	0	0
T1	8868	145	0	0
T2	13693	20	0	0
T3	4429	53	0	0
T7	389434	7	0	0
T8	355168	815	0	0
T9	1771	13	0	0
T10	453078	15	0	0
T11	6003	58	0	0
T12	117829	111	0	0
T13	579606	0	0	0
T14	0	1007	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	535162	0	0
T1	8868	150	0	0
T2	13693	25	0	0
T3	4429	56	0	0
T7	389434	7	0	0
T8	355168	951	0	0
T9	1771	13	0	0
T10	453078	15	0	0
T11	6003	61	0	0
T12	117829	138	0	0
T13	579606	0	0	0
T14	0	3904	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	213031	0	0
T1	8868	145	0	0
T2	13693	20	0	0
T3	4429	53	0	0
T7	389434	7	0	0
T8	355168	815	0	0
T9	1771	13	0	0
T10	453078	15	0	0
T11	6003	58	0	0
T12	117829	111	0	0
T13	579606	0	0	0
T14	0	1007	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	216002	0	0
GntImpliesValid_A	438663802	216002	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	216002	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	3177411	0	0
ReadyAndValidImplyGrant_A	438663802	216002	0	0
ReqAndReadyImplyGrant_A	438663802	216002	0	0
ReqImpliesValid_A	438663802	530006	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	216002	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	216002	0	0
T1	8868	140	0	0
T2	13693	17	0	0
T3	4429	59	0	0
T7	389434	9	0	0
T8	355168	768	0	0
T9	1771	13	0	0
T10	453078	7	0	0
T11	6003	60	0	0
T12	117829	101	0	0
T13	579606	508	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	216002	0	0
T1	8868	140	0	0
T2	13693	17	0	0
T3	4429	59	0	0
T7	389434	9	0	0
T8	355168	768	0	0
T9	1771	13	0	0
T10	453078	7	0	0
T11	6003	60	0	0
T12	117829	101	0	0
T13	579606	508	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	216002	0	0
T1	8868	140	0	0
T2	13693	17	0	0
T3	4429	59	0	0
T7	389434	9	0	0
T8	355168	768	0	0
T9	1771	13	0	0
T10	453078	7	0	0
T11	6003	60	0	0
T12	117829	101	0	0
T13	579606	508	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	3177411	0	0
T1	8868	132	0	0
T2	13693	144	0	0
T3	4429	57	0	0
T7	389434	3468	0	0
T8	355168	5799	0	0
T9	1771	14	0	0
T10	453078	1312	0	0
T11	6003	57	0	0
T12	117829	416	0	0
T13	579606	1756	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	216002	0	0
T1	8868	140	0	0
T2	13693	17	0	0
T3	4429	59	0	0
T7	389434	9	0	0
T8	355168	768	0	0
T9	1771	13	0	0
T10	453078	7	0	0
T11	6003	60	0	0
T12	117829	101	0	0
T13	579606	508	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	216002	0	0
T1	8868	140	0	0
T2	13693	17	0	0
T3	4429	59	0	0
T7	389434	9	0	0
T8	355168	768	0	0
T9	1771	13	0	0
T10	453078	7	0	0
T11	6003	60	0	0
T12	117829	101	0	0
T13	579606	508	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	530006	0	0
T1	8868	149	0	0
T2	13693	31	0	0
T3	4429	62	0	0
T7	389434	218	0	0
T8	355168	862	0	0
T9	1771	13	0	0
T10	453078	681	0	0
T11	6003	64	0	0
T12	117829	138	0	0
T13	579606	1115	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	216002	0	0
T1	8868	140	0	0
T2	13693	17	0	0
T3	4429	59	0	0
T7	389434	9	0	0
T8	355168	768	0	0
T9	1771	13	0	0
T10	453078	7	0	0
T11	6003	60	0	0
T12	117829	101	0	0
T13	579606	508	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	213379	0	0
GntImpliesValid_A	438663802	213379	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	213379	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	3220812	0	0
ReadyAndValidImplyGrant_A	438663802	213379	0	0
ReqAndReadyImplyGrant_A	438663802	213379	0	0
ReqImpliesValid_A	438663802	598122	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	0	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	213379	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	213379	0	0
T1	8868	126	0	0
T2	13693	17	0	0
T3	4429	48	0	0
T7	389434	10	0	0
T8	355168	748	0	0
T9	1771	17	0	0
T10	453078	17	0	0
T11	6003	63	0	0
T12	117829	106	0	0
T13	579606	0	0	0
T14	0	510	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	213379	0	0
T1	8868	126	0	0
T2	13693	17	0	0
T3	4429	48	0	0
T7	389434	10	0	0
T8	355168	748	0	0
T9	1771	17	0	0
T10	453078	17	0	0
T11	6003	63	0	0
T12	117829	106	0	0
T13	579606	0	0	0
T14	0	510	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	213379	0	0
T1	8868	126	0	0
T2	13693	17	0	0
T3	4429	48	0	0
T7	389434	10	0	0
T8	355168	748	0	0
T9	1771	17	0	0
T10	453078	17	0	0
T11	6003	63	0	0
T12	117829	106	0	0
T13	579606	0	0	0
T14	0	510	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	3220812	0	0
T1	8868	121	0	0
T2	13693	122	0	0
T3	4429	49	0	0
T7	389434	4435	0	0
T8	355168	5514	0	0
T9	1771	15	0	0
T10	453078	5495	0	0
T11	6003	64	0	0
T12	117829	439	0	0
T13	579606	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	213379	0	0
T1	8868	126	0	0
T2	13693	17	0	0
T3	4429	48	0	0
T7	389434	10	0	0
T8	355168	748	0	0
T9	1771	17	0	0
T10	453078	17	0	0
T11	6003	63	0	0
T12	117829	106	0	0
T13	579606	0	0	0
T14	0	510	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	213379	0	0
T1	8868	126	0	0
T2	13693	17	0	0
T3	4429	48	0	0
T7	389434	10	0	0
T8	355168	748	0	0
T9	1771	17	0	0
T10	453078	17	0	0
T11	6003	63	0	0
T12	117829	106	0	0
T13	579606	0	0	0
T14	0	510	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	598122	0	0
T1	8868	132	0	0
T2	13693	24	0	0
T3	4429	48	0	0
T7	389434	10	0	0
T8	355168	887	0	0
T9	1771	20	0	0
T10	453078	17	0	0
T11	6003	63	0	0
T12	117829	137	0	0
T13	579606	0	0	0
T14	0	4662	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	213379	0	0
T1	8868	126	0	0
T2	13693	17	0	0
T3	4429	48	0	0
T7	389434	10	0	0
T8	355168	748	0	0
T9	1771	17	0	0
T10	453078	17	0	0
T11	6003	63	0	0
T12	117829	106	0	0
T13	579606	0	0	0
T14	0	510	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	908084	0	0
GntImpliesValid_A	438663802	908084	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	908084	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	12076623	0	0
ReadyAndValidImplyGrant_A	438663802	908084	0	0
ReqAndReadyImplyGrant_A	438663802	908084	0	0
ReqImpliesValid_A	438663802	2320786	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	22864	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	908084	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	908084	0	0
T1	8868	585	0	0
T2	13693	58	0	0
T3	4429	202	0	0
T7	389434	49	0	0
T8	355168	2858	0	0
T9	1771	45	0	0
T10	453078	52	0	0
T11	6003	249	0	0
T12	117829	382	0	0
T13	579606	1582	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	908084	0	0
T1	8868	585	0	0
T2	13693	58	0	0
T3	4429	202	0	0
T7	389434	49	0	0
T8	355168	2858	0	0
T9	1771	45	0	0
T10	453078	52	0	0
T11	6003	249	0	0
T12	117829	382	0	0
T13	579606	1582	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	908084	0	0
T1	8868	585	0	0
T2	13693	58	0	0
T3	4429	202	0	0
T7	389434	49	0	0
T8	355168	2858	0	0
T9	1771	45	0	0
T10	453078	52	0	0
T11	6003	249	0	0
T12	117829	382	0	0
T13	579606	1582	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	12076623	0	0
T1	8868	1	0	0
T2	13693	333	0	0
T3	4429	1	0	0
T7	389434	17008	0	0
T8	355168	18767	0	0
T9	1771	1	0	0
T10	453078	13152	0	0
T11	6003	1	0	0
T12	117829	1190	0	0
T13	579606	4489	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	908084	0	0
T1	8868	585	0	0
T2	13693	58	0	0
T3	4429	202	0	0
T7	389434	49	0	0
T8	355168	2858	0	0
T9	1771	45	0	0
T10	453078	52	0	0
T11	6003	249	0	0
T12	117829	382	0	0
T13	579606	1582	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	908084	0	0
T1	8868	585	0	0
T2	13693	58	0	0
T3	4429	202	0	0
T7	389434	49	0	0
T8	355168	2858	0	0
T9	1771	45	0	0
T10	453078	52	0	0
T11	6003	249	0	0
T12	117829	382	0	0
T13	579606	1582	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	2320786	0	0
T1	8868	585	0	0
T2	13693	98	0	0
T3	4429	202	0	0
T7	389434	583	0	0
T8	355168	4027	0	0
T9	1771	45	0	0
T10	453078	190	0	0
T11	6003	249	0	0
T12	117829	511	0	0
T13	579606	2785	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	22864	0	900
T1	8868	10	0	1
T2	13693	0	0	1
T3	4429	1	0	1
T7	389434	0	0	1
T8	355168	0	0	1
T9	1771	0	0	1
T10	453078	0	0	1
T11	6003	1	0	1
T12	117829	0	0	1
T13	579606	12	0	1
T15	0	38	0	0
T16	0	8	0	0
T17	0	15	0	0
T18	0	15	0	0
T19	0	86	0	0
T20	0	4	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	908084	0	0
T1	8868	585	0	0
T2	13693	58	0	0
T3	4429	202	0	0
T7	389434	49	0	0
T8	355168	2858	0	0
T9	1771	45	0	0
T10	453078	52	0	0
T11	6003	249	0	0
T12	117829	382	0	0
T13	579606	1582	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438663802	438552008	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438663802	889015	0	0
GntImpliesValid_A	438663802	889015	0	0
GrantKnown_A	438663802	438552008	0	0
IdxKnown_A	438663802	438552008	0	0
IndexIsCorrect_A	438663802	889015	0	0
LockArbDecision_A	438663802	0	0	0
NoReadyValidNoGrant_A	438663802	368651883	0	0
ReadyAndValidImplyGrant_A	438663802	889015	0	0
ReqAndReadyImplyGrant_A	438663802	889015	0	0
ReqImpliesValid_A	438663802	13848636	0	0
ReqStaysHighUntilGranted0_M	438663802	0	0	0
RoundRobin_A	438663802	36291	0	900
ValidKnown_A	438663802	438552008	0	0
gen_data_port_assertion.DataFlow_A	438663802	889015	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	889015	0	0
T1	8868	584	0	0
T2	13693	43	0	0
T3	4429	205	0	0
T7	389434	43	0	0
T8	355168	2701	0	0
T9	1771	55	0	0
T10	453078	40	0	0
T11	6003	240	0	0
T12	117829	452	0	0
T13	579606	694	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	889015	0	0
T1	8868	584	0	0
T2	13693	43	0	0
T3	4429	205	0	0
T7	389434	43	0	0
T8	355168	2701	0	0
T9	1771	55	0	0
T10	453078	40	0	0
T11	6003	240	0	0
T12	117829	452	0	0
T13	579606	694	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	889015	0	0
T1	8868	584	0	0
T2	13693	43	0	0
T3	4429	205	0	0
T7	389434	43	0	0
T8	355168	2701	0	0
T9	1771	55	0	0
T10	453078	40	0	0
T11	6003	240	0	0
T12	117829	452	0	0
T13	579606	694	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	368651883	0	0
T1	8868	1	0	0
T2	13693	12092	0	0
T3	4429	1	0	0
T7	389434	365892	0	0
T8	355168	302796	0	0
T9	1771	1	0	0
T10	453078	431676	0	0
T11	6003	1	0	0
T12	117829	980478	0	0
T13	579606	482780	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	889015	0	0
T1	8868	584	0	0
T2	13693	43	0	0
T3	4429	205	0	0
T7	389434	43	0	0
T8	355168	2701	0	0
T9	1771	55	0	0
T10	453078	40	0	0
T11	6003	240	0	0
T12	117829	452	0	0
T13	579606	694	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	889015	0	0
T1	8868	584	0	0
T2	13693	43	0	0
T3	4429	205	0	0
T7	389434	43	0	0
T8	355168	2701	0	0
T9	1771	55	0	0
T10	453078	40	0	0
T11	6003	240	0	0
T12	117829	452	0	0
T13	579606	694	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	13848636	0	0
T1	8868	584	0	0
T2	13693	379	0	0
T3	4429	205	0	0
T7	389434	14957	0	0
T8	355168	21640	0	0
T9	1771	55	0	0
T10	453078	14536	0	0
T11	6003	240	0	0
T12	117829	1936	0	0
T13	579606	3083	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	36291	0	900
T1	8868	9	0	1
T2	13693	0	0	1
T3	4429	2	0	1
T7	389434	0	0	1
T8	355168	2	0	1
T9	1771	0	0	1
T10	453078	0	0	1
T11	6003	4	0	1
T12	117829	0	0	1
T13	579606	0	0	1
T15	0	235	0	0
T16	0	7	0	0
T17	0	7	0	0
T18	0	10	0	0
T19	0	585	0	0
T20	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	438552008	0	0
T1	8868	8840	0	0
T2	13693	13667	0	0
T3	4429	4420	0	0
T7	389434	389397	0	0
T8	355168	353770	0	0
T9	1771	1764	0	0
T10	453078	453059	0	0
T11	6003	5982	0	0
T12	117829	117825	0	0
T13	579606	579598	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438663802	889015	0	0
T1	8868	584	0	0
T2	13693	43	0	0
T3	4429	205	0	0
T7	389434	43	0	0
T8	355168	2701	0	0
T9	1771	55	0	0
T10	453078	40	0	0
T11	6003	240	0	0
T12	117829	452	0	0
T13	579606	694	0	0