Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1520287	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

240537

1

T1

323

T2

81

T3

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	597804	1			T1	737		T2	202		T3	34
values[0x0]	564093	1			T1	746		T2	189		T3	34
values[0x1]	598927	1			T1	835		T2	212		T3	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1175219	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

585605

1

T1

772

T2

207

T3

45

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27204	1			T1	34		T3	2		T8	6
valid_sources[0x01]	26691	1			T1	35		T2	15		T7	16
valid_sources[0x02]	27486	1			T1	43		T2	7		T3	1
valid_sources[0x03]	27400	1			T1	44		T2	10		T3	1
valid_sources[0x04]	27012	1			T1	29		T2	19		T3	2
valid_sources[0x05]	28428	1			T1	32		T3	1		T8	9
valid_sources[0x06]	27132	1			T1	38		T3	1		T8	3
valid_sources[0x07]	27565	1			T1	37		T2	36		T8	17
valid_sources[0x08]	28519	1			T1	35		T2	6		T3	4
valid_sources[0x09]	26594	1			T1	36		T3	2		T8	4
valid_sources[0x0a]	27363	1			T1	44		T3	3		T8	8
valid_sources[0x0b]	27752	1			T1	33		T3	1		T8	5
valid_sources[0x0c]	28022	1			T1	43		T2	14		T3	2
valid_sources[0x0d]	26961	1			T1	48		T3	2		T8	13
valid_sources[0x0e]	27191	1			T1	34		T3	5		T8	7
valid_sources[0x0f]	28244	1			T1	31		T2	12		T3	1
valid_sources[0x10]	27657	1			T1	39		T2	17		T3	4
valid_sources[0x11]	27660	1			T1	39		T3	1		T7	59
valid_sources[0x12]	28544	1			T1	29		T2	33		T3	4
valid_sources[0x13]	26901	1			T1	33		T3	1		T8	3
valid_sources[0x14]	26833	1			T1	29		T3	4		T8	5
valid_sources[0x15]	27977	1			T1	27		T3	2		T8	2
valid_sources[0x16]	27558	1			T1	36		T3	1		T8	12
valid_sources[0x17]	27485	1			T1	41		T2	18		T3	1
valid_sources[0x18]	28128	1			T1	31		T2	17		T8	2
valid_sources[0x19]	27489	1			T1	31		T3	1		T8	1
valid_sources[0x1a]	27119	1			T1	35		T3	2		T8	3
valid_sources[0x1b]	27673	1			T1	44		T3	2		T8	3
valid_sources[0x1c]	27671	1			T1	40		T3	1		T8	8
valid_sources[0x1d]	28091	1			T1	31		T2	16		T3	2
valid_sources[0x1e]	26811	1			T1	34		T2	6		T3	1
valid_sources[0x1f]	28126	1			T1	42		T2	23		T3	2
valid_sources[0x20]	27685	1			T1	36		T3	1		T8	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25417

1

T1

30

T2

3

T3

3

values[0x0]

all_enables

biggest_size

189636

1

T1

260

T2

66

T3

16

values[0x1]

all_enables

biggest_size

25484

1

T1

33

T2

12

T3

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1535602	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

249672

1

T1

345

T2

66

T3

31

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	611531	1			T1	759		T2	208		T3	63
values[0x0]	562468	1			T1	742		T2	181		T3	68
values[0x1]	611275	1			T1	750		T2	173		T3	66

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1178497	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

606777

1

T1

769

T2

175

T3

59

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27133	1			T1	32		T8	6		T7	68
valid_sources[0x01]	27924	1			T1	36		T2	10		T3	5
valid_sources[0x02]	28559	1			T1	34		T2	20		T3	4
valid_sources[0x03]	27383	1			T1	41		T2	9		T3	1
valid_sources[0x04]	27285	1			T1	31		T2	9		T3	1
valid_sources[0x05]	27899	1			T1	38		T3	3		T8	2
valid_sources[0x06]	27715	1			T1	48		T3	5		T8	6
valid_sources[0x07]	28422	1			T1	37		T2	28		T3	5
valid_sources[0x08]	27890	1			T1	23		T2	8		T3	4
valid_sources[0x09]	28244	1			T1	27		T3	1		T8	4
valid_sources[0x0a]	28150	1			T1	42		T3	2		T8	2
valid_sources[0x0b]	27554	1			T1	35		T3	3		T8	5
valid_sources[0x0c]	28253	1			T1	32		T2	17		T3	1
valid_sources[0x0d]	28482	1			T1	32		T3	2		T8	7
valid_sources[0x0e]	27974	1			T1	22		T3	3		T8	8
valid_sources[0x0f]	28290	1			T1	39		T2	19		T3	1
valid_sources[0x10]	28178	1			T1	21		T2	12		T3	4
valid_sources[0x11]	27976	1			T1	45		T3	5		T8	12
valid_sources[0x12]	28019	1			T1	36		T2	18		T8	1
valid_sources[0x13]	27808	1			T1	42		T3	2		T8	3
valid_sources[0x14]	27155	1			T1	28		T3	4		T8	4
valid_sources[0x15]	27306	1			T1	39		T3	4		T8	5
valid_sources[0x16]	28178	1			T1	40		T3	5		T8	8
valid_sources[0x17]	27846	1			T1	26		T2	9		T3	4
valid_sources[0x18]	27852	1			T1	35		T2	15		T3	2
valid_sources[0x19]	27189	1			T1	29		T3	4		T8	3
valid_sources[0x1a]	28507	1			T1	37		T3	2		T8	6
valid_sources[0x1b]	28240	1			T1	39		T3	5		T8	11
valid_sources[0x1c]	27482	1			T1	29		T3	5		T8	4
valid_sources[0x1d]	28424	1			T1	46		T2	12		T3	5
valid_sources[0x1e]	27532	1			T1	27		T2	8		T3	2
valid_sources[0x1f]	27487	1			T1	33		T2	27		T3	2
valid_sources[0x20]	28162	1			T1	29		T3	5		T7	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26161

1

T1

27

T2

3

T3

3

values[0x0]

all_enables

biggest_size

197421

1

T1

282

T2

56

T3

26

values[0x1]

all_enables

biggest_size

26090

1

T1

36

T2

7

T3

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1532185	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

244105

1

T1

330

T2

81

T3

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	604243	1			T1	758		T2	209		T3	58
values[0x0]	569258	1			T1	771		T2	224		T3	45
values[0x1]	602789	1			T1	751		T2	214		T3	51

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1183113	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

593177

1

T1

768

T2

205

T3

56

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27029	1			T1	28		T3	5		T8	4
valid_sources[0x01]	27811	1			T1	33		T2	19		T3	6
valid_sources[0x02]	27508	1			T1	29		T2	20		T3	6
valid_sources[0x03]	27414	1			T1	69		T2	5		T8	5
valid_sources[0x04]	28803	1			T1	35		T2	19		T8	2
valid_sources[0x05]	27525	1			T1	36		T3	11		T8	6
valid_sources[0x06]	27602	1			T1	22		T3	9		T8	4
valid_sources[0x07]	27390	1			T1	18		T2	37		T8	3
valid_sources[0x08]	27722	1			T1	26		T2	15		T8	8
valid_sources[0x09]	27360	1			T1	32		T8	5		T7	109
valid_sources[0x0a]	27632	1			T1	30		T8	5		T7	8
valid_sources[0x0b]	28620	1			T1	25		T3	6		T8	5
valid_sources[0x0c]	27738	1			T1	53		T2	15		T8	8
valid_sources[0x0d]	27514	1			T1	41		T3	3		T8	6
valid_sources[0x0e]	27897	1			T1	39		T3	1		T8	3
valid_sources[0x0f]	28446	1			T1	40		T2	8		T8	8
valid_sources[0x10]	28873	1			T1	43		T2	16		T8	6
valid_sources[0x11]	28761	1			T1	38		T8	4		T7	27
valid_sources[0x12]	28255	1			T1	36		T2	22		T3	3
valid_sources[0x13]	26955	1			T1	21		T3	10		T8	5
valid_sources[0x14]	28154	1			T1	9		T3	3		T8	9
valid_sources[0x15]	27484	1			T1	47		T3	4		T8	4
valid_sources[0x16]	27896	1			T1	47		T8	8		T7	26
valid_sources[0x17]	27448	1			T1	28		T2	18		T3	6
valid_sources[0x18]	27513	1			T1	29		T2	5		T3	14
valid_sources[0x19]	27228	1			T1	57		T3	4		T8	4
valid_sources[0x1a]	28513	1			T1	43		T3	2		T8	4
valid_sources[0x1b]	27954	1			T1	43		T3	2		T8	8
valid_sources[0x1c]	27223	1			T1	23		T3	6		T8	4
valid_sources[0x1d]	27311	1			T1	41		T2	20		T3	3
valid_sources[0x1e]	27455	1			T1	36		T2	10		T8	5
valid_sources[0x1f]	27146	1			T1	53		T2	36		T3	4
valid_sources[0x20]	27642	1			T1	14		T3	1		T8	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25781

1

T1

28

T2

6

T3

6

values[0x0]

all_enables

biggest_size

192866

1

T1

272

T2

69

T3

14

values[0x1]

all_enables

biggest_size

25458

1

T1

30

T2

6

T3

2