Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7927762	0	0
GntImpliesValid_A	2147483647	7927762	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7927762	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	472843216	0	0
ReadyAndValidImplyGrant_A	2147483647	7927762	0	0
ReqAndReadyImplyGrant_A	2147483647	7927762	0	0
ReqImpliesValid_A	2147483647	35270688	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	45855	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7927762	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1213344	1211736	0	0
T2	133512	132600	0	0
T3	10355040	10353720	0	0
T7	3666672	3664800	0	0
T8	54456	52824	0	0
T9	1089216	1087464	0	0
T10	3338808	3338664	0	0
T11	11868120	11834040	0	0
T12	7552464	7540152	0	0
T13	1855992	1854840	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7927762	0	0
T1	1213344	3503	0	0
T2	133512	1806	0	0
T3	10355040	452	0	0
T7	3666672	7359	0	0
T8	54456	988	0	0
T9	1089216	2063	0	0
T10	3338808	2342	0	0
T11	11868120	52035	0	0
T12	7552464	25592	0	0
T13	1855992	4364	0	0
T14	0	2378	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7927762	0	0
T1	1213344	3503	0	0
T2	133512	1806	0	0
T3	10355040	452	0	0
T7	3666672	7359	0	0
T8	54456	988	0	0
T9	1089216	2063	0	0
T10	3338808	2342	0	0
T11	11868120	52035	0	0
T12	7552464	25592	0	0
T13	1855992	4364	0	0
T14	0	2378	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1213344	1211736	0	0
T2	133512	132600	0	0
T3	10355040	10353720	0	0
T7	3666672	3664800	0	0
T8	54456	52824	0	0
T9	1089216	1087464	0	0
T10	3338808	3338664	0	0
T11	11868120	11834040	0	0
T12	7552464	7540152	0	0
T13	1855992	1854840	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1213344	1211736	0	0
T2	133512	132600	0	0
T3	10355040	10353720	0	0
T7	3666672	3664800	0	0
T8	54456	52824	0	0
T9	1089216	1087464	0	0
T10	3338808	3338664	0	0
T11	11868120	11834040	0	0
T12	7552464	7540152	0	0
T13	1855992	1854840	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7927762	0	0
T1	1213344	3503	0	0
T2	133512	1806	0	0
T3	10355040	452	0	0
T7	3666672	7359	0	0
T8	54456	988	0	0
T9	1089216	2063	0	0
T10	3338808	2342	0	0
T11	11868120	52035	0	0
T12	7552464	25592	0	0
T13	1855992	4364	0	0
T14	0	2378	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	472843216	0	0
T1	1213344	69598	0	0
T2	133512	2662	0	0
T3	10355040	543430	0	0
T7	3666672	206172	0	0
T8	54456	1467	0	0
T9	1089216	61536	0	0
T10	3338808	128636	0	0
T11	11868120	658221	0	0
T12	7552464	420036	0	0
T13	1855992	98462	0	0
T14	0	1750	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7927762	0	0
T1	1213344	3503	0	0
T2	133512	1806	0	0
T3	10355040	452	0	0
T7	3666672	7359	0	0
T8	54456	988	0	0
T9	1089216	2063	0	0
T10	3338808	2342	0	0
T11	11868120	52035	0	0
T12	7552464	25592	0	0
T13	1855992	4364	0	0
T14	0	2378	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7927762	0	0
T1	1213344	3503	0	0
T2	133512	1806	0	0
T3	10355040	452	0	0
T7	3666672	7359	0	0
T8	54456	988	0	0
T9	1089216	2063	0	0
T10	3338808	2342	0	0
T11	11868120	52035	0	0
T12	7552464	25592	0	0
T13	1855992	4364	0	0
T14	0	2378	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35270688	0	0
T1	1213344	7543	0	0
T2	133512	1883	0	0
T3	10355040	28285	0	0
T7	3666672	13447	0	0
T8	54456	1123	0	0
T9	1089216	3912	0	0
T10	3338808	7159	0	0
T11	11868120	223842	0	0
T12	7552464	66311	0	0
T13	1855992	8171	0	0
T14	0	2658	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	45855	0	21600
T1	50556	2	0	1
T2	11126	9	0	2
T3	862920	0	0	2
T7	305556	0	0	2
T8	4538	3	0	2
T9	90768	0	0	2
T10	278234	0	0	2
T11	989010	171	0	2
T12	629372	6	0	2
T13	154666	2	0	2
T14	8245	18	0	1
T15	0	61	0	0
T16	0	34	0	0
T17	0	1261	0	0
T18	0	3	0	0
T19	0	11	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1213344	1211736	0	0
T2	133512	132600	0	0
T3	10355040	10353720	0	0
T7	3666672	3664800	0	0
T8	54456	52824	0	0
T9	1089216	1087464	0	0
T10	3338808	3338664	0	0
T11	11868120	11834040	0	0
T12	7552464	7540152	0	0
T13	1855992	1854840	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7927762	0	0
T1	1213344	3503	0	0
T2	133512	1806	0	0
T3	10355040	452	0	0
T7	3666672	7359	0	0
T8	54456	988	0	0
T9	1089216	2063	0	0
T10	3338808	2342	0	0
T11	11868120	52035	0	0
T12	7552464	25592	0	0
T13	1855992	4364	0	0
T14	0	2378	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	876144	0	0
GntImpliesValid_A	438779748	876144	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	876144	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	11801953	0	0
ReadyAndValidImplyGrant_A	438779748	876144	0	0
ReqAndReadyImplyGrant_A	438779748	876144	0	0
ReqImpliesValid_A	438779748	2461487	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	876144	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	876144	0	0
T1	50556	375	0	0
T2	5563	185	0	0
T3	431460	53	0	0
T7	152778	838	0	0
T8	2269	107	0	0
T9	45384	262	0	0
T10	139117	916	0	0
T11	494505	5936	0	0
T12	314686	3287	0	0
T13	77333	448	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	876144	0	0
T1	50556	375	0	0
T2	5563	185	0	0
T3	431460	53	0	0
T7	152778	838	0	0
T8	2269	107	0	0
T9	45384	262	0	0
T10	139117	916	0	0
T11	494505	5936	0	0
T12	314686	3287	0	0
T13	77333	448	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	876144	0	0
T1	50556	375	0	0
T2	5563	185	0	0
T3	431460	53	0	0
T7	152778	838	0	0
T8	2269	107	0	0
T9	45384	262	0	0
T10	139117	916	0	0
T11	494505	5936	0	0
T12	314686	3287	0	0
T13	77333	448	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	11801953	0	0
T1	50556	2861	0	0
T2	5563	181	0	0
T3	431460	18717	0	0
T7	152778	6632	0	0
T8	2269	85	0	0
T9	45384	2006	0	0
T10	139117	2985	0	0
T11	494505	33951	0	0
T12	314686	22974	0	0
T13	77333	3356	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	876144	0	0
T1	50556	375	0	0
T2	5563	185	0	0
T3	431460	53	0	0
T7	152778	838	0	0
T8	2269	107	0	0
T9	45384	262	0	0
T10	139117	916	0	0
T11	494505	5936	0	0
T12	314686	3287	0	0
T13	77333	448	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	876144	0	0
T1	50556	375	0	0
T2	5563	185	0	0
T3	431460	53	0	0
T7	152778	838	0	0
T8	2269	107	0	0
T9	45384	262	0	0
T10	139117	916	0	0
T11	494505	5936	0	0
T12	314686	3287	0	0
T13	77333	448	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	2461487	0	0
T1	50556	540	0	0
T2	5563	190	0	0
T3	431460	1052	0	0
T7	152778	899	0	0
T8	2269	130	0	0
T9	45384	301	0	0
T10	139117	2039	0	0
T11	494505	12724	0	0
T12	314686	6679	0	0
T13	77333	511	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	876144	0	0
T1	50556	375	0	0
T2	5563	185	0	0
T3	431460	53	0	0
T7	152778	838	0	0
T8	2269	107	0	0
T9	45384	262	0	0
T10	139117	916	0	0
T11	494505	5936	0	0
T12	314686	3287	0	0
T13	77333	448	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	880363	0	0
GntImpliesValid_A	438779748	880363	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	880363	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	11956932	0	0
ReadyAndValidImplyGrant_A	438779748	880363	0	0
ReqAndReadyImplyGrant_A	438779748	880363	0	0
ReqImpliesValid_A	438779748	2503018	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	880363	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	880363	0	0
T1	50556	394	0	0
T2	5563	186	0	0
T3	431460	72	0	0
T7	152778	842	0	0
T8	2269	88	0	0
T9	45384	222	0	0
T10	139117	145	0	0
T11	494505	5187	0	0
T12	314686	2506	0	0
T13	77333	476	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	880363	0	0
T1	50556	394	0	0
T2	5563	186	0	0
T3	431460	72	0	0
T7	152778	842	0	0
T8	2269	88	0	0
T9	45384	222	0	0
T10	139117	145	0	0
T11	494505	5187	0	0
T12	314686	2506	0	0
T13	77333	476	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	880363	0	0
T1	50556	394	0	0
T2	5563	186	0	0
T3	431460	72	0	0
T7	152778	842	0	0
T8	2269	88	0	0
T9	45384	222	0	0
T10	139117	145	0	0
T11	494505	5187	0	0
T12	314686	2506	0	0
T13	77333	476	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	11956932	0	0
T1	50556	2970	0	0
T2	5563	182	0	0
T3	431460	24344	0	0
T7	152778	6394	0	0
T8	2269	71	0	0
T9	45384	1610	0	0
T10	139117	598	0	0
T11	494505	36432	0	0
T12	314686	19189	0	0
T13	77333	3759	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	880363	0	0
T1	50556	394	0	0
T2	5563	186	0	0
T3	431460	72	0	0
T7	152778	842	0	0
T8	2269	88	0	0
T9	45384	222	0	0
T10	139117	145	0	0
T11	494505	5187	0	0
T12	314686	2506	0	0
T13	77333	476	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	880363	0	0
T1	50556	394	0	0
T2	5563	186	0	0
T3	431460	72	0	0
T7	152778	842	0	0
T8	2269	88	0	0
T9	45384	222	0	0
T10	139117	145	0	0
T11	494505	5187	0	0
T12	314686	2506	0	0
T13	77333	476	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	2503018	0	0
T1	50556	736	0	0
T2	5563	191	0	0
T3	431460	3518	0	0
T7	152778	929	0	0
T8	2269	106	0	0
T9	45384	265	0	0
T10	139117	210	0	0
T11	494505	11585	0	0
T12	314686	3737	0	0
T13	77333	538	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	880363	0	0
T1	50556	394	0	0
T2	5563	186	0	0
T3	431460	72	0	0
T7	152778	842	0	0
T8	2269	88	0	0
T9	45384	222	0	0
T10	139117	145	0	0
T11	494505	5187	0	0
T12	314686	2506	0	0
T13	77333	476	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	226344	0	0
GntImpliesValid_A	438779748	226344	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	226344	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	2938872	0	0
ReadyAndValidImplyGrant_A	438779748	226344	0	0
ReqAndReadyImplyGrant_A	438779748	226344	0	0
ReqImpliesValid_A	438779748	607943	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	226344	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	226344	0	0
T1	50556	87	0	0
T2	5563	53	0	0
T3	431460	7	0	0
T7	152778	213	0	0
T8	2269	32	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1071	0	0
T12	314686	451	0	0
T13	77333	138	0	0
T14	0	141	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	226344	0	0
T1	50556	87	0	0
T2	5563	53	0	0
T3	431460	7	0	0
T7	152778	213	0	0
T8	2269	32	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1071	0	0
T12	314686	451	0	0
T13	77333	138	0	0
T14	0	141	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	226344	0	0
T1	50556	87	0	0
T2	5563	53	0	0
T3	431460	7	0	0
T7	152778	213	0	0
T8	2269	32	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1071	0	0
T12	314686	451	0	0
T13	77333	138	0	0
T14	0	141	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	2938872	0	0
T1	50556	684	0	0
T2	5563	54	0	0
T3	431460	2301	0	0
T7	152778	1610	0	0
T8	2269	33	0	0
T9	45384	506	0	0
T10	139117	1	0	0
T11	494505	5200	0	0
T12	314686	3356	0	0
T13	77333	1067	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	226344	0	0
T1	50556	87	0	0
T2	5563	53	0	0
T3	431460	7	0	0
T7	152778	213	0	0
T8	2269	32	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1071	0	0
T12	314686	451	0	0
T13	77333	138	0	0
T14	0	141	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	226344	0	0
T1	50556	87	0	0
T2	5563	53	0	0
T3	431460	7	0	0
T7	152778	213	0	0
T8	2269	32	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1071	0	0
T12	314686	451	0	0
T13	77333	138	0	0
T14	0	141	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	607943	0	0
T1	50556	109	0	0
T2	5563	53	0	0
T3	431460	7	0	0
T7	152778	230	0	0
T8	2269	32	0	0
T9	45384	58	0	0
T10	139117	0	0	0
T11	494505	5205	0	0
T12	314686	534	0	0
T13	77333	140	0	0
T14	0	147	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	226344	0	0
T1	50556	87	0	0
T2	5563	53	0	0
T3	431460	7	0	0
T7	152778	213	0	0
T8	2269	32	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1071	0	0
T12	314686	451	0	0
T13	77333	138	0	0
T14	0	141	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	221537	0	0
GntImpliesValid_A	438779748	221537	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	221537	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	2959101	0	0
ReadyAndValidImplyGrant_A	438779748	221537	0	0
ReqAndReadyImplyGrant_A	438779748	221537	0	0
ReqImpliesValid_A	438779748	637508	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	221537	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	221537	0	0
T1	50556	106	0	0
T2	5563	59	0	0
T3	431460	12	0	0
T7	152778	207	0	0
T8	2269	36	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	1535	0	0
T12	314686	455	0	0
T13	77333	147	0	0
T14	0	142	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	221537	0	0
T1	50556	106	0	0
T2	5563	59	0	0
T3	431460	12	0	0
T7	152778	207	0	0
T8	2269	36	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	1535	0	0
T12	314686	455	0	0
T13	77333	147	0	0
T14	0	142	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	221537	0	0
T1	50556	106	0	0
T2	5563	59	0	0
T3	431460	12	0	0
T7	152778	207	0	0
T8	2269	36	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	1535	0	0
T12	314686	455	0	0
T13	77333	147	0	0
T14	0	142	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	2959101	0	0
T1	50556	785	0	0
T2	5563	59	0	0
T3	431460	3316	0	0
T7	152778	1604	0	0
T8	2269	35	0	0
T9	45384	394	0	0
T10	139117	1	0	0
T11	494505	5846	0	0
T12	314686	3327	0	0
T13	77333	1039	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	221537	0	0
T1	50556	106	0	0
T2	5563	59	0	0
T3	431460	12	0	0
T7	152778	207	0	0
T8	2269	36	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	1535	0	0
T12	314686	455	0	0
T13	77333	147	0	0
T14	0	142	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	221537	0	0
T1	50556	106	0	0
T2	5563	59	0	0
T3	431460	12	0	0
T7	152778	207	0	0
T8	2269	36	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	1535	0	0
T12	314686	455	0	0
T13	77333	147	0	0
T14	0	142	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	637508	0	0
T1	50556	180	0	0
T2	5563	60	0	0
T3	431460	955	0	0
T7	152778	212	0	0
T8	2269	38	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	10257	0	0
T12	314686	502	0	0
T13	77333	156	0	0
T14	0	148	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	221537	0	0
T1	50556	106	0	0
T2	5563	59	0	0
T3	431460	12	0	0
T7	152778	207	0	0
T8	2269	36	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	1535	0	0
T12	314686	455	0	0
T13	77333	147	0	0
T14	0	142	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	220231	0	0
GntImpliesValid_A	438779748	220231	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	220231	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	6003633	0	0
ReadyAndValidImplyGrant_A	438779748	220231	0	0
ReqAndReadyImplyGrant_A	438779748	220231	0	0
ReqImpliesValid_A	438779748	1303048	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	220231	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	220231	0	0
T1	50556	91	0	0
T2	5563	48	0	0
T3	431460	5	0	0
T7	152778	221	0	0
T8	2269	27	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1554	0	0
T12	314686	462	0	0
T13	77333	121	0	0
T14	0	134	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	220231	0	0
T1	50556	91	0	0
T2	5563	48	0	0
T3	431460	5	0	0
T7	152778	221	0	0
T8	2269	27	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1554	0	0
T12	314686	462	0	0
T13	77333	121	0	0
T14	0	134	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	220231	0	0
T1	50556	91	0	0
T2	5563	48	0	0
T3	431460	5	0	0
T7	152778	221	0	0
T8	2269	27	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1554	0	0
T12	314686	462	0	0
T13	77333	121	0	0
T14	0	134	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	6003633	0	0
T1	50556	1902	0	0
T2	5563	397	0	0
T3	431460	2658	0	0
T7	152778	10966	0	0
T8	2269	177	0	0
T9	45384	3473	0	0
T10	139117	0	0	0
T11	494505	9212	0	0
T12	314686	3445	0	0
T13	77333	1885	0	0
T14	0	655	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	220231	0	0
T1	50556	91	0	0
T2	5563	48	0	0
T3	431460	5	0	0
T7	152778	221	0	0
T8	2269	27	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1554	0	0
T12	314686	462	0	0
T13	77333	121	0	0
T14	0	134	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	220231	0	0
T1	50556	91	0	0
T2	5563	48	0	0
T3	431460	5	0	0
T7	152778	221	0	0
T8	2269	27	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1554	0	0
T12	314686	462	0	0
T13	77333	121	0	0
T14	0	134	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	1303048	0	0
T1	50556	299	0	0
T2	5563	49	0	0
T3	431460	5	0	0
T7	152778	417	0	0
T8	2269	34	0	0
T9	45384	60	0	0
T10	139117	0	0	0
T11	494505	11419	0	0
T12	314686	500	0	0
T13	77333	122	0	0
T14	0	207	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	220231	0	0
T1	50556	91	0	0
T2	5563	48	0	0
T3	431460	5	0	0
T7	152778	221	0	0
T8	2269	27	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1554	0	0
T12	314686	462	0	0
T13	77333	121	0	0
T14	0	134	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	211854	0	0
GntImpliesValid_A	438779748	211854	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	211854	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	5357460	0	0
ReadyAndValidImplyGrant_A	438779748	211854	0	0
ReqAndReadyImplyGrant_A	438779748	211854	0	0
ReqImpliesValid_A	438779748	1214049	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	211854	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	211854	0	0
T1	50556	85	0	0
T2	5563	42	0	0
T3	431460	9	0	0
T7	152778	222	0	0
T8	2269	25	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	2077	0	0
T12	314686	890	0	0
T13	77333	137	0	0
T14	0	117	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	211854	0	0
T1	50556	85	0	0
T2	5563	42	0	0
T3	431460	9	0	0
T7	152778	222	0	0
T8	2269	25	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	2077	0	0
T12	314686	890	0	0
T13	77333	137	0	0
T14	0	117	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	211854	0	0
T1	50556	85	0	0
T2	5563	42	0	0
T3	431460	9	0	0
T7	152778	222	0	0
T8	2269	25	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	2077	0	0
T12	314686	890	0	0
T13	77333	137	0	0
T14	0	117	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	5357460	0	0
T1	50556	903	0	0
T2	5563	215	0	0
T3	431460	1686	0	0
T7	152778	9569	0	0
T8	2269	255	0	0
T9	45384	1725	0	0
T10	139117	0	0	0
T11	494505	13333	0	0
T12	314686	4952	0	0
T13	77333	1525	0	0
T14	0	526	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	211854	0	0
T1	50556	85	0	0
T2	5563	42	0	0
T3	431460	9	0	0
T7	152778	222	0	0
T8	2269	25	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	2077	0	0
T12	314686	890	0	0
T13	77333	137	0	0
T14	0	117	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	211854	0	0
T1	50556	85	0	0
T2	5563	42	0	0
T3	431460	9	0	0
T7	152778	222	0	0
T8	2269	25	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	2077	0	0
T12	314686	890	0	0
T13	77333	137	0	0
T14	0	117	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	1214049	0	0
T1	50556	131	0	0
T2	5563	55	0	0
T3	431460	9	0	0
T7	152778	251	0	0
T8	2269	56	0	0
T9	45384	59	0	0
T10	139117	0	0	0
T11	494505	11960	0	0
T12	314686	1216	0	0
T13	77333	147	0	0
T14	0	163	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	211854	0	0
T1	50556	85	0	0
T2	5563	42	0	0
T3	431460	9	0	0
T7	152778	222	0	0
T8	2269	25	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	2077	0	0
T12	314686	890	0	0
T13	77333	137	0	0
T14	0	117	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	214096	0	0
GntImpliesValid_A	438779748	214096	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	214096	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	5952104	0	0
ReadyAndValidImplyGrant_A	438779748	214096	0	0
ReqAndReadyImplyGrant_A	438779748	214096	0	0
ReqImpliesValid_A	438779748	1416758	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	214096	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	214096	0	0
T1	50556	108	0	0
T2	5563	50	0	0
T3	431460	11	0	0
T7	152778	190	0	0
T8	2269	34	0	0
T9	45384	58	0	0
T10	139117	0	0	0
T11	494505	1777	0	0
T12	314686	494	0	0
T13	77333	113	0	0
T14	0	147	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	214096	0	0
T1	50556	108	0	0
T2	5563	50	0	0
T3	431460	11	0	0
T7	152778	190	0	0
T8	2269	34	0	0
T9	45384	58	0	0
T10	139117	0	0	0
T11	494505	1777	0	0
T12	314686	494	0	0
T13	77333	113	0	0
T14	0	147	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	214096	0	0
T1	50556	108	0	0
T2	5563	50	0	0
T3	431460	11	0	0
T7	152778	190	0	0
T8	2269	34	0	0
T9	45384	58	0	0
T10	139117	0	0	0
T11	494505	1777	0	0
T12	314686	494	0	0
T13	77333	113	0	0
T14	0	147	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	5952104	0	0
T1	50556	1654	0	0
T2	5563	335	0	0
T3	431460	3140	0	0
T7	152778	5488	0	0
T8	2269	242	0	0
T9	45384	2761	0	0
T10	139117	0	0	0
T11	494505	8747	0	0
T12	314686	2883	0	0
T13	77333	1693	0	0
T14	0	569	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	214096	0	0
T1	50556	108	0	0
T2	5563	50	0	0
T3	431460	11	0	0
T7	152778	190	0	0
T8	2269	34	0	0
T9	45384	58	0	0
T10	139117	0	0	0
T11	494505	1777	0	0
T12	314686	494	0	0
T13	77333	113	0	0
T14	0	147	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	214096	0	0
T1	50556	108	0	0
T2	5563	50	0	0
T3	431460	11	0	0
T7	152778	190	0	0
T8	2269	34	0	0
T9	45384	58	0	0
T10	139117	0	0	0
T11	494505	1777	0	0
T12	314686	494	0	0
T13	77333	113	0	0
T14	0	147	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	1416758	0	0
T1	50556	275	0	0
T2	5563	56	0	0
T3	431460	172	0	0
T7	152778	210	0	0
T8	2269	46	0	0
T9	45384	99	0	0
T10	139117	0	0	0
T11	494505	13803	0	0
T12	314686	525	0	0
T13	77333	124	0	0
T14	0	199	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	214096	0	0
T1	50556	108	0	0
T2	5563	50	0	0
T3	431460	11	0	0
T7	152778	190	0	0
T8	2269	34	0	0
T9	45384	58	0	0
T10	139117	0	0	0
T11	494505	1777	0	0
T12	314686	494	0	0
T13	77333	113	0	0
T14	0	147	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	216715	0	0
GntImpliesValid_A	438779748	216715	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	216715	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	5114089	0	0
ReadyAndValidImplyGrant_A	438779748	216715	0	0
ReqAndReadyImplyGrant_A	438779748	216715	0	0
ReqImpliesValid_A	438779748	1171181	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	216715	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	216715	0	0
T1	50556	97	0	0
T2	5563	54	0	0
T3	431460	9	0	0
T7	152778	194	0	0
T8	2269	28	0	0
T9	45384	48	0	0
T10	139117	489	0	0
T11	494505	769	0	0
T12	314686	451	0	0
T13	77333	121	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	216715	0	0
T1	50556	97	0	0
T2	5563	54	0	0
T3	431460	9	0	0
T7	152778	194	0	0
T8	2269	28	0	0
T9	45384	48	0	0
T10	139117	489	0	0
T11	494505	769	0	0
T12	314686	451	0	0
T13	77333	121	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	216715	0	0
T1	50556	97	0	0
T2	5563	54	0	0
T3	431460	9	0	0
T7	152778	194	0	0
T8	2269	28	0	0
T9	45384	48	0	0
T10	139117	489	0	0
T11	494505	769	0	0
T12	314686	451	0	0
T13	77333	121	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	5114089	0	0
T1	50556	1169	0	0
T2	5563	489	0	0
T3	431460	2288	0	0
T7	152778	3581	0	0
T8	2269	199	0	0
T9	45384	2716	0	0
T10	139117	6867	0	0
T11	494505	7658	0	0
T12	314686	3408	0	0
T13	77333	1067	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	216715	0	0
T1	50556	97	0	0
T2	5563	54	0	0
T3	431460	9	0	0
T7	152778	194	0	0
T8	2269	28	0	0
T9	45384	48	0	0
T10	139117	489	0	0
T11	494505	769	0	0
T12	314686	451	0	0
T13	77333	121	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	216715	0	0
T1	50556	97	0	0
T2	5563	54	0	0
T3	431460	9	0	0
T7	152778	194	0	0
T8	2269	28	0	0
T9	45384	48	0	0
T10	139117	489	0	0
T11	494505	769	0	0
T12	314686	451	0	0
T13	77333	121	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	1171181	0	0
T1	50556	150	0	0
T2	5563	99	0	0
T3	431460	9	0	0
T7	152778	246	0	0
T8	2269	44	0	0
T9	45384	98	0	0
T10	139117	3105	0	0
T11	494505	1282	0	0
T12	314686	474	0	0
T13	77333	127	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	216715	0	0
T1	50556	97	0	0
T2	5563	54	0	0
T3	431460	9	0	0
T7	152778	194	0	0
T8	2269	28	0	0
T9	45384	48	0	0
T10	139117	489	0	0
T11	494505	769	0	0
T12	314686	451	0	0
T13	77333	121	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	225729	0	0
GntImpliesValid_A	438779748	225729	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	225729	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	2949084	0	0
ReadyAndValidImplyGrant_A	438779748	225729	0	0
ReqAndReadyImplyGrant_A	438779748	225729	0	0
ReqImpliesValid_A	438779748	652958	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	225729	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	225729	0	0
T1	50556	93	0	0
T2	5563	48	0	0
T3	431460	12	0	0
T7	152778	200	0	0
T8	2269	20	0	0
T9	45384	66	0	0
T10	139117	0	0	0
T11	494505	2953	0	0
T12	314686	484	0	0
T13	77333	107	0	0
T14	0	126	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	225729	0	0
T1	50556	93	0	0
T2	5563	48	0	0
T3	431460	12	0	0
T7	152778	200	0	0
T8	2269	20	0	0
T9	45384	66	0	0
T10	139117	0	0	0
T11	494505	2953	0	0
T12	314686	484	0	0
T13	77333	107	0	0
T14	0	126	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	225729	0	0
T1	50556	93	0	0
T2	5563	48	0	0
T3	431460	12	0	0
T7	152778	200	0	0
T8	2269	20	0	0
T9	45384	66	0	0
T10	139117	0	0	0
T11	494505	2953	0	0
T12	314686	484	0	0
T13	77333	107	0	0
T14	0	126	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	2949084	0	0
T1	50556	609	0	0
T2	5563	49	0	0
T3	431460	4167	0	0
T7	152778	1428	0	0
T8	2269	21	0	0
T9	45384	487	0	0
T10	139117	1	0	0
T11	494505	11581	0	0
T12	314686	3844	0	0
T13	77333	867	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	225729	0	0
T1	50556	93	0	0
T2	5563	48	0	0
T3	431460	12	0	0
T7	152778	200	0	0
T8	2269	20	0	0
T9	45384	66	0	0
T10	139117	0	0	0
T11	494505	2953	0	0
T12	314686	484	0	0
T13	77333	107	0	0
T14	0	126	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	225729	0	0
T1	50556	93	0	0
T2	5563	48	0	0
T3	431460	12	0	0
T7	152778	200	0	0
T8	2269	20	0	0
T9	45384	66	0	0
T10	139117	0	0	0
T11	494505	2953	0	0
T12	314686	484	0	0
T13	77333	107	0	0
T14	0	126	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	652958	0	0
T1	50556	113	0	0
T2	5563	48	0	0
T3	431460	12	0	0
T7	152778	220	0	0
T8	2269	20	0	0
T9	45384	66	0	0
T10	139117	0	0	0
T11	494505	19564	0	0
T12	314686	515	0	0
T13	77333	115	0	0
T14	0	132	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	225729	0	0
T1	50556	93	0	0
T2	5563	48	0	0
T3	431460	12	0	0
T7	152778	200	0	0
T8	2269	20	0	0
T9	45384	66	0	0
T10	139117	0	0	0
T11	494505	2953	0	0
T12	314686	484	0	0
T13	77333	107	0	0
T14	0	126	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T8,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	217881	0	0
GntImpliesValid_A	438779748	217881	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	217881	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	2885345	0	0
ReadyAndValidImplyGrant_A	438779748	217881	0	0
ReqAndReadyImplyGrant_A	438779748	217881	0	0
ReqImpliesValid_A	438779748	579409	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	217881	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	217881	0	0
T1	50556	93	0	0
T2	5563	74	0	0
T3	431460	7	0	0
T7	152778	197	0	0
T8	2269	29	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	1752	0	0
T12	314686	954	0	0
T13	77333	128	0	0
T14	0	140	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	217881	0	0
T1	50556	93	0	0
T2	5563	74	0	0
T3	431460	7	0	0
T7	152778	197	0	0
T8	2269	29	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	1752	0	0
T12	314686	954	0	0
T13	77333	128	0	0
T14	0	140	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	217881	0	0
T1	50556	93	0	0
T2	5563	74	0	0
T3	431460	7	0	0
T7	152778	197	0	0
T8	2269	29	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	1752	0	0
T12	314686	954	0	0
T13	77333	128	0	0
T14	0	140	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	2885345	0	0
T1	50556	703	0	0
T2	5563	75	0	0
T3	431460	1818	0	0
T7	152778	1525	0	0
T8	2269	28	0	0
T9	45384	452	0	0
T10	139117	1	0	0
T11	494505	8177	0	0
T12	314686	6514	0	0
T13	77333	1054	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	217881	0	0
T1	50556	93	0	0
T2	5563	74	0	0
T3	431460	7	0	0
T7	152778	197	0	0
T8	2269	29	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	1752	0	0
T12	314686	954	0	0
T13	77333	128	0	0
T14	0	140	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	217881	0	0
T1	50556	93	0	0
T2	5563	74	0	0
T3	431460	7	0	0
T7	152778	197	0	0
T8	2269	29	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	1752	0	0
T12	314686	954	0	0
T13	77333	128	0	0
T14	0	140	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	579409	0	0
T1	50556	122	0	0
T2	5563	74	0	0
T3	431460	7	0	0
T7	152778	197	0	0
T8	2269	31	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	9583	0	0
T12	314686	2372	0	0
T13	77333	133	0	0
T14	0	148	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	217881	0	0
T1	50556	93	0	0
T2	5563	74	0	0
T3	431460	7	0	0
T7	152778	197	0	0
T8	2269	29	0	0
T9	45384	54	0	0
T10	139117	0	0	0
T11	494505	1752	0	0
T12	314686	954	0	0
T13	77333	128	0	0
T14	0	140	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	214952	0	0
GntImpliesValid_A	438779748	214952	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	214952	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	2932901	0	0
ReadyAndValidImplyGrant_A	438779748	214952	0	0
ReqAndReadyImplyGrant_A	438779748	214952	0	0
ReqImpliesValid_A	438779748	569422	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	214952	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	214952	0	0
T1	50556	123	0	0
T2	5563	49	0	0
T3	431460	14	0	0
T7	152778	189	0	0
T8	2269	24	0	0
T9	45384	58	0	0
T10	139117	526	0	0
T11	494505	1655	0	0
T12	314686	939	0	0
T13	77333	122	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	214952	0	0
T1	50556	123	0	0
T2	5563	49	0	0
T3	431460	14	0	0
T7	152778	189	0	0
T8	2269	24	0	0
T9	45384	58	0	0
T10	139117	526	0	0
T11	494505	1655	0	0
T12	314686	939	0	0
T13	77333	122	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	214952	0	0
T1	50556	123	0	0
T2	5563	49	0	0
T3	431460	14	0	0
T7	152778	189	0	0
T8	2269	24	0	0
T9	45384	58	0	0
T10	139117	526	0	0
T11	494505	1655	0	0
T12	314686	939	0	0
T13	77333	122	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	2932901	0	0
T1	50556	926	0	0
T2	5563	50	0	0
T3	431460	5966	0	0
T7	152778	1460	0	0
T8	2269	25	0	0
T9	45384	355	0	0
T10	139117	1839	0	0
T11	494505	8849	0	0
T12	314686	6069	0	0
T13	77333	940	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	214952	0	0
T1	50556	123	0	0
T2	5563	49	0	0
T3	431460	14	0	0
T7	152778	189	0	0
T8	2269	24	0	0
T9	45384	58	0	0
T10	139117	526	0	0
T11	494505	1655	0	0
T12	314686	939	0	0
T13	77333	122	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	214952	0	0
T1	50556	123	0	0
T2	5563	49	0	0
T3	431460	14	0	0
T7	152778	189	0	0
T8	2269	24	0	0
T9	45384	58	0	0
T10	139117	526	0	0
T11	494505	1655	0	0
T12	314686	939	0	0
T13	77333	122	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	569422	0	0
T1	50556	180	0	0
T2	5563	49	0	0
T3	431460	852	0	0
T7	152778	193	0	0
T8	2269	24	0	0
T9	45384	58	0	0
T10	139117	1108	0	0
T11	494505	3922	0	0
T12	314686	3208	0	0
T13	77333	122	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	214952	0	0
T1	50556	123	0	0
T2	5563	49	0	0
T3	431460	14	0	0
T7	152778	189	0	0
T8	2269	24	0	0
T9	45384	58	0	0
T10	139117	526	0	0
T11	494505	1655	0	0
T12	314686	939	0	0
T13	77333	122	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	210022	0	0
GntImpliesValid_A	438779748	210022	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	210022	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	2940919	0	0
ReadyAndValidImplyGrant_A	438779748	210022	0	0
ReqAndReadyImplyGrant_A	438779748	210022	0	0
ReqImpliesValid_A	438779748	563047	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	210022	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	210022	0	0
T1	50556	89	0	0
T2	5563	57	0	0
T3	431460	5	0	0
T7	152778	201	0	0
T8	2269	29	0	0
T9	45384	45	0	0
T10	139117	0	0	0
T11	494505	1612	0	0
T12	314686	926	0	0
T13	77333	132	0	0
T14	0	112	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	210022	0	0
T1	50556	89	0	0
T2	5563	57	0	0
T3	431460	5	0	0
T7	152778	201	0	0
T8	2269	29	0	0
T9	45384	45	0	0
T10	139117	0	0	0
T11	494505	1612	0	0
T12	314686	926	0	0
T13	77333	132	0	0
T14	0	112	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	210022	0	0
T1	50556	89	0	0
T2	5563	57	0	0
T3	431460	5	0	0
T7	152778	201	0	0
T8	2269	29	0	0
T9	45384	45	0	0
T10	139117	0	0	0
T11	494505	1612	0	0
T12	314686	926	0	0
T13	77333	132	0	0
T14	0	112	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	2940919	0	0
T1	50556	690	0	0
T2	5563	58	0	0
T3	431460	1548	0	0
T7	152778	1591	0	0
T8	2269	28	0	0
T9	45384	315	0	0
T10	139117	1	0	0
T11	494505	9079	0	0
T12	314686	6362	0	0
T13	77333	981	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	210022	0	0
T1	50556	89	0	0
T2	5563	57	0	0
T3	431460	5	0	0
T7	152778	201	0	0
T8	2269	29	0	0
T9	45384	45	0	0
T10	139117	0	0	0
T11	494505	1612	0	0
T12	314686	926	0	0
T13	77333	132	0	0
T14	0	112	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	210022	0	0
T1	50556	89	0	0
T2	5563	57	0	0
T3	431460	5	0	0
T7	152778	201	0	0
T8	2269	29	0	0
T9	45384	45	0	0
T10	139117	0	0	0
T11	494505	1612	0	0
T12	314686	926	0	0
T13	77333	132	0	0
T14	0	112	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	563047	0	0
T1	50556	122	0	0
T2	5563	57	0	0
T3	431460	355	0	0
T7	152778	211	0	0
T8	2269	31	0	0
T9	45384	45	0	0
T10	139117	0	0	0
T11	494505	7155	0	0
T12	314686	2428	0	0
T13	77333	151	0	0
T14	0	118	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	210022	0	0
T1	50556	89	0	0
T2	5563	57	0	0
T3	431460	5	0	0
T7	152778	201	0	0
T8	2269	29	0	0
T9	45384	45	0	0
T10	139117	0	0	0
T11	494505	1612	0	0
T12	314686	926	0	0
T13	77333	132	0	0
T14	0	112	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T8,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	229183	0	0
GntImpliesValid_A	438779748	229183	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	229183	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	2914289	0	0
ReadyAndValidImplyGrant_A	438779748	229183	0	0
ReqAndReadyImplyGrant_A	438779748	229183	0	0
ReqImpliesValid_A	438779748	625635	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	229183	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	229183	0	0
T1	50556	86	0	0
T2	5563	48	0	0
T3	431460	13	0	0
T7	152778	202	0	0
T8	2269	30	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1077	0	0
T12	314686	1421	0	0
T13	77333	123	0	0
T14	0	143	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	229183	0	0
T1	50556	86	0	0
T2	5563	48	0	0
T3	431460	13	0	0
T7	152778	202	0	0
T8	2269	30	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1077	0	0
T12	314686	1421	0	0
T13	77333	123	0	0
T14	0	143	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	229183	0	0
T1	50556	86	0	0
T2	5563	48	0	0
T3	431460	13	0	0
T7	152778	202	0	0
T8	2269	30	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1077	0	0
T12	314686	1421	0	0
T13	77333	123	0	0
T14	0	143	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	2914289	0	0
T1	50556	675	0	0
T2	5563	49	0	0
T3	431460	3486	0	0
T7	152778	1492	0	0
T8	2269	29	0	0
T9	45384	404	0	0
T10	139117	1	0	0
T11	494505	6937	0	0
T12	314686	9025	0	0
T13	77333	1032	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	229183	0	0
T1	50556	86	0	0
T2	5563	48	0	0
T3	431460	13	0	0
T7	152778	202	0	0
T8	2269	30	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1077	0	0
T12	314686	1421	0	0
T13	77333	123	0	0
T14	0	143	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	229183	0	0
T1	50556	86	0	0
T2	5563	48	0	0
T3	431460	13	0	0
T7	152778	202	0	0
T8	2269	30	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1077	0	0
T12	314686	1421	0	0
T13	77333	123	0	0
T14	0	143	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	625635	0	0
T1	50556	92	0	0
T2	5563	48	0	0
T3	431460	13	0	0
T7	152778	210	0	0
T8	2269	32	0	0
T9	45384	69	0	0
T10	139117	0	0	0
T11	494505	1835	0	0
T12	314686	2384	0	0
T13	77333	123	0	0
T14	0	152	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	229183	0	0
T1	50556	86	0	0
T2	5563	48	0	0
T3	431460	13	0	0
T7	152778	202	0	0
T8	2269	30	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1077	0	0
T12	314686	1421	0	0
T13	77333	123	0	0
T14	0	143	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	212133	0	0
GntImpliesValid_A	438779748	212133	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	212133	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	2912205	0	0
ReadyAndValidImplyGrant_A	438779748	212133	0	0
ReqAndReadyImplyGrant_A	438779748	212133	0	0
ReqImpliesValid_A	438779748	548286	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	212133	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	212133	0	0
T1	50556	100	0	0
T2	5563	55	0	0
T3	431460	15	0	0
T7	152778	182	0	0
T8	2269	26	0	0
T9	45384	56	0	0
T10	139117	0	0	0
T11	494505	643	0	0
T12	314686	459	0	0
T13	77333	111	0	0
T14	0	144	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	212133	0	0
T1	50556	100	0	0
T2	5563	55	0	0
T3	431460	15	0	0
T7	152778	182	0	0
T8	2269	26	0	0
T9	45384	56	0	0
T10	139117	0	0	0
T11	494505	643	0	0
T12	314686	459	0	0
T13	77333	111	0	0
T14	0	144	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	212133	0	0
T1	50556	100	0	0
T2	5563	55	0	0
T3	431460	15	0	0
T7	152778	182	0	0
T8	2269	26	0	0
T9	45384	56	0	0
T10	139117	0	0	0
T11	494505	643	0	0
T12	314686	459	0	0
T13	77333	111	0	0
T14	0	144	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	2912205	0	0
T1	50556	712	0	0
T2	5563	56	0	0
T3	431460	4901	0	0
T7	152778	1261	0	0
T8	2269	27	0	0
T9	45384	445	0	0
T10	139117	1	0	0
T11	494505	4768	0	0
T12	314686	3567	0	0
T13	77333	884	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	212133	0	0
T1	50556	100	0	0
T2	5563	55	0	0
T3	431460	15	0	0
T7	152778	182	0	0
T8	2269	26	0	0
T9	45384	56	0	0
T10	139117	0	0	0
T11	494505	643	0	0
T12	314686	459	0	0
T13	77333	111	0	0
T14	0	144	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	212133	0	0
T1	50556	100	0	0
T2	5563	55	0	0
T3	431460	15	0	0
T7	152778	182	0	0
T8	2269	26	0	0
T9	45384	56	0	0
T10	139117	0	0	0
T11	494505	643	0	0
T12	314686	459	0	0
T13	77333	111	0	0
T14	0	144	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	548286	0	0
T1	50556	115	0	0
T2	5563	55	0	0
T3	431460	15	0	0
T7	152778	189	0	0
T8	2269	26	0	0
T9	45384	56	0	0
T10	139117	0	0	0
T11	494505	795	0	0
T12	314686	502	0	0
T13	77333	113	0	0
T14	0	154	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	212133	0	0
T1	50556	100	0	0
T2	5563	55	0	0
T3	431460	15	0	0
T7	152778	182	0	0
T8	2269	26	0	0
T9	45384	56	0	0
T10	139117	0	0	0
T11	494505	643	0	0
T12	314686	459	0	0
T13	77333	111	0	0
T14	0	144	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	224438	0	0
GntImpliesValid_A	438779748	224438	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	224438	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	2889543	0	0
ReadyAndValidImplyGrant_A	438779748	224438	0	0
ReqAndReadyImplyGrant_A	438779748	224438	0	0
ReqImpliesValid_A	438779748	651308	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	224438	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	224438	0	0
T1	50556	96	0	0
T2	5563	48	0	0
T3	431460	12	0	0
T7	152778	182	0	0
T8	2269	19	0	0
T9	45384	53	0	0
T10	139117	0	0	0
T11	494505	1136	0	0
T12	314686	473	0	0
T13	77333	98	0	0
T14	0	125	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	224438	0	0
T1	50556	96	0	0
T2	5563	48	0	0
T3	431460	12	0	0
T7	152778	182	0	0
T8	2269	19	0	0
T9	45384	53	0	0
T10	139117	0	0	0
T11	494505	1136	0	0
T12	314686	473	0	0
T13	77333	98	0	0
T14	0	125	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	224438	0	0
T1	50556	96	0	0
T2	5563	48	0	0
T3	431460	12	0	0
T7	152778	182	0	0
T8	2269	19	0	0
T9	45384	53	0	0
T10	139117	0	0	0
T11	494505	1136	0	0
T12	314686	473	0	0
T13	77333	98	0	0
T14	0	125	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	2889543	0	0
T1	50556	722	0	0
T2	5563	49	0	0
T3	431460	2944	0	0
T7	152778	1452	0	0
T8	2269	19	0	0
T9	45384	458	0	0
T10	139117	1	0	0
T11	494505	5139	0	0
T12	314686	3560	0	0
T13	77333	768	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	224438	0	0
T1	50556	96	0	0
T2	5563	48	0	0
T3	431460	12	0	0
T7	152778	182	0	0
T8	2269	19	0	0
T9	45384	53	0	0
T10	139117	0	0	0
T11	494505	1136	0	0
T12	314686	473	0	0
T13	77333	98	0	0
T14	0	125	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	224438	0	0
T1	50556	96	0	0
T2	5563	48	0	0
T3	431460	12	0	0
T7	152778	182	0	0
T8	2269	19	0	0
T9	45384	53	0	0
T10	139117	0	0	0
T11	494505	1136	0	0
T12	314686	473	0	0
T13	77333	98	0	0
T14	0	125	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	651308	0	0
T1	50556	114	0	0
T2	5563	48	0	0
T3	431460	877	0	0
T7	152778	182	0	0
T8	2269	20	0	0
T9	45384	53	0	0
T10	139117	0	0	0
T11	494505	6523	0	0
T12	314686	480	0	0
T13	77333	98	0	0
T14	0	132	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	224438	0	0
T1	50556	96	0	0
T2	5563	48	0	0
T3	431460	12	0	0
T7	152778	182	0	0
T8	2269	19	0	0
T9	45384	53	0	0
T10	139117	0	0	0
T11	494505	1136	0	0
T12	314686	473	0	0
T13	77333	98	0	0
T14	0	125	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T8,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	222722	0	0
GntImpliesValid_A	438779748	222722	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	222722	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	2865157	0	0
ReadyAndValidImplyGrant_A	438779748	222722	0	0
ReqAndReadyImplyGrant_A	438779748	222722	0	0
ReqImpliesValid_A	438779748	607811	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	222722	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	222722	0	0
T1	50556	102	0	0
T2	5563	50	0	0
T3	431460	9	0	0
T7	152778	225	0	0
T8	2269	30	0	0
T9	45384	48	0	0
T10	139117	0	0	0
T11	494505	1417	0	0
T12	314686	893	0	0
T13	77333	128	0	0
T14	0	135	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	222722	0	0
T1	50556	102	0	0
T2	5563	50	0	0
T3	431460	9	0	0
T7	152778	225	0	0
T8	2269	30	0	0
T9	45384	48	0	0
T10	139117	0	0	0
T11	494505	1417	0	0
T12	314686	893	0	0
T13	77333	128	0	0
T14	0	135	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	222722	0	0
T1	50556	102	0	0
T2	5563	50	0	0
T3	431460	9	0	0
T7	152778	225	0	0
T8	2269	30	0	0
T9	45384	48	0	0
T10	139117	0	0	0
T11	494505	1417	0	0
T12	314686	893	0	0
T13	77333	128	0	0
T14	0	135	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	2865157	0	0
T1	50556	708	0	0
T2	5563	51	0	0
T3	431460	3205	0	0
T7	152778	1584	0	0
T8	2269	29	0	0
T9	45384	252	0	0
T10	139117	1	0	0
T11	494505	7296	0	0
T12	314686	6651	0	0
T13	77333	905	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	222722	0	0
T1	50556	102	0	0
T2	5563	50	0	0
T3	431460	9	0	0
T7	152778	225	0	0
T8	2269	30	0	0
T9	45384	48	0	0
T10	139117	0	0	0
T11	494505	1417	0	0
T12	314686	893	0	0
T13	77333	128	0	0
T14	0	135	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	222722	0	0
T1	50556	102	0	0
T2	5563	50	0	0
T3	431460	9	0	0
T7	152778	225	0	0
T8	2269	30	0	0
T9	45384	48	0	0
T10	139117	0	0	0
T11	494505	1417	0	0
T12	314686	893	0	0
T13	77333	128	0	0
T14	0	135	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	607811	0	0
T1	50556	115	0	0
T2	5563	50	0	0
T3	431460	9	0	0
T7	152778	227	0	0
T8	2269	32	0	0
T9	45384	48	0	0
T10	139117	0	0	0
T11	494505	6503	0	0
T12	314686	2248	0	0
T13	77333	140	0	0
T14	0	149	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	222722	0	0
T1	50556	102	0	0
T2	5563	50	0	0
T3	431460	9	0	0
T7	152778	225	0	0
T8	2269	30	0	0
T9	45384	48	0	0
T10	139117	0	0	0
T11	494505	1417	0	0
T12	314686	893	0	0
T13	77333	128	0	0
T14	0	135	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	231993	0	0
GntImpliesValid_A	438779748	231993	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	231993	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	2933888	0	0
ReadyAndValidImplyGrant_A	438779748	231993	0	0
ReqAndReadyImplyGrant_A	438779748	231993	0	0
ReqImpliesValid_A	438779748	553214	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	231993	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	231993	0	0
T1	50556	151	0	0
T2	5563	53	0	0
T3	431460	11	0	0
T7	152778	210	0	0
T8	2269	28	0	0
T9	45384	59	0	0
T10	139117	0	0	0
T11	494505	2866	0	0
T12	314686	552	0	0
T13	77333	136	0	0
T14	0	143	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	231993	0	0
T1	50556	151	0	0
T2	5563	53	0	0
T3	431460	11	0	0
T7	152778	210	0	0
T8	2269	28	0	0
T9	45384	59	0	0
T10	139117	0	0	0
T11	494505	2866	0	0
T12	314686	552	0	0
T13	77333	136	0	0
T14	0	143	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	231993	0	0
T1	50556	151	0	0
T2	5563	53	0	0
T3	431460	11	0	0
T7	152778	210	0	0
T8	2269	28	0	0
T9	45384	59	0	0
T10	139117	0	0	0
T11	494505	2866	0	0
T12	314686	552	0	0
T13	77333	136	0	0
T14	0	143	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	2933888	0	0
T1	50556	1125	0	0
T2	5563	54	0	0
T3	431460	3567	0	0
T7	152778	1672	0	0
T8	2269	22	0	0
T9	45384	417	0	0
T10	139117	1	0	0
T11	494505	13848	0	0
T12	314686	4001	0	0
T13	77333	959	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	231993	0	0
T1	50556	151	0	0
T2	5563	53	0	0
T3	431460	11	0	0
T7	152778	210	0	0
T8	2269	28	0	0
T9	45384	59	0	0
T10	139117	0	0	0
T11	494505	2866	0	0
T12	314686	552	0	0
T13	77333	136	0	0
T14	0	143	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	231993	0	0
T1	50556	151	0	0
T2	5563	53	0	0
T3	431460	11	0	0
T7	152778	210	0	0
T8	2269	28	0	0
T9	45384	59	0	0
T10	139117	0	0	0
T11	494505	2866	0	0
T12	314686	552	0	0
T13	77333	136	0	0
T14	0	143	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	553214	0	0
T1	50556	215	0	0
T2	5563	53	0	0
T3	431460	281	0	0
T7	152778	233	0	0
T8	2269	35	0	0
T9	45384	59	0	0
T10	139117	0	0	0
T11	494505	7971	0	0
T12	314686	616	0	0
T13	77333	145	0	0
T14	0	150	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	231993	0	0
T1	50556	151	0	0
T2	5563	53	0	0
T3	431460	11	0	0
T7	152778	210	0	0
T8	2269	28	0	0
T9	45384	59	0	0
T10	139117	0	0	0
T11	494505	2866	0	0
T12	314686	552	0	0
T13	77333	136	0	0
T14	0	143	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	222447	0	0
GntImpliesValid_A	438779748	222447	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	222447	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	2893119	0	0
ReadyAndValidImplyGrant_A	438779748	222447	0	0
ReqAndReadyImplyGrant_A	438779748	222447	0	0
ReqImpliesValid_A	438779748	607290	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	222447	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	222447	0	0
T1	50556	101	0	0
T2	5563	53	0	0
T3	431460	11	0	0
T7	152778	212	0	0
T8	2269	28	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1133	0	0
T12	314686	2031	0	0
T13	77333	135	0	0
T14	0	135	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	222447	0	0
T1	50556	101	0	0
T2	5563	53	0	0
T3	431460	11	0	0
T7	152778	212	0	0
T8	2269	28	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1133	0	0
T12	314686	2031	0	0
T13	77333	135	0	0
T14	0	135	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	222447	0	0
T1	50556	101	0	0
T2	5563	53	0	0
T3	431460	11	0	0
T7	152778	212	0	0
T8	2269	28	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1133	0	0
T12	314686	2031	0	0
T13	77333	135	0	0
T14	0	135	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	2893119	0	0
T1	50556	793	0	0
T2	5563	54	0	0
T3	431460	4122	0	0
T7	152778	1785	0	0
T8	2269	27	0	0
T9	45384	381	0	0
T10	139117	1	0	0
T11	494505	5643	0	0
T12	314686	12997	0	0
T13	77333	1076	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	222447	0	0
T1	50556	101	0	0
T2	5563	53	0	0
T3	431460	11	0	0
T7	152778	212	0	0
T8	2269	28	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1133	0	0
T12	314686	2031	0	0
T13	77333	135	0	0
T14	0	135	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	222447	0	0
T1	50556	101	0	0
T2	5563	53	0	0
T3	431460	11	0	0
T7	152778	212	0	0
T8	2269	28	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1133	0	0
T12	314686	2031	0	0
T13	77333	135	0	0
T14	0	135	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	607290	0	0
T1	50556	121	0	0
T2	5563	53	0	0
T3	431460	436	0	0
T7	152778	218	0	0
T8	2269	30	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	5767	0	0
T12	314686	6377	0	0
T13	77333	135	0	0
T14	0	142	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	222447	0	0
T1	50556	101	0	0
T2	5563	53	0	0
T3	431460	11	0	0
T7	152778	212	0	0
T8	2269	28	0	0
T9	45384	57	0	0
T10	139117	0	0	0
T11	494505	1133	0	0
T12	314686	2031	0	0
T13	77333	135	0	0
T14	0	135	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	218713	0	0
GntImpliesValid_A	438779748	218713	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	218713	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	2893146	0	0
ReadyAndValidImplyGrant_A	438779748	218713	0	0
ReqAndReadyImplyGrant_A	438779748	218713	0	0
ReqImpliesValid_A	438779748	576800	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	218713	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	218713	0	0
T1	50556	93	0	0
T2	5563	43	0	0
T3	431460	16	0	0
T7	152778	213	0	0
T8	2269	28	0	0
T9	45384	53	0	0
T10	139117	0	0	0
T11	494505	1169	0	0
T12	314686	435	0	0
T13	77333	120	0	0
T14	0	119	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	218713	0	0
T1	50556	93	0	0
T2	5563	43	0	0
T3	431460	16	0	0
T7	152778	213	0	0
T8	2269	28	0	0
T9	45384	53	0	0
T10	139117	0	0	0
T11	494505	1169	0	0
T12	314686	435	0	0
T13	77333	120	0	0
T14	0	119	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	218713	0	0
T1	50556	93	0	0
T2	5563	43	0	0
T3	431460	16	0	0
T7	152778	213	0	0
T8	2269	28	0	0
T9	45384	53	0	0
T10	139117	0	0	0
T11	494505	1169	0	0
T12	314686	435	0	0
T13	77333	120	0	0
T14	0	119	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	2893146	0	0
T1	50556	800	0	0
T2	5563	44	0	0
T3	431460	7255	0	0
T7	152778	1648	0	0
T8	2269	28	0	0
T9	45384	382	0	0
T10	139117	1	0	0
T11	494505	5895	0	0
T12	314686	3462	0	0
T13	77333	926	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	218713	0	0
T1	50556	93	0	0
T2	5563	43	0	0
T3	431460	16	0	0
T7	152778	213	0	0
T8	2269	28	0	0
T9	45384	53	0	0
T10	139117	0	0	0
T11	494505	1169	0	0
T12	314686	435	0	0
T13	77333	120	0	0
T14	0	119	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	218713	0	0
T1	50556	93	0	0
T2	5563	43	0	0
T3	431460	16	0	0
T7	152778	213	0	0
T8	2269	28	0	0
T9	45384	53	0	0
T10	139117	0	0	0
T11	494505	1169	0	0
T12	314686	435	0	0
T13	77333	120	0	0
T14	0	119	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	576800	0	0
T1	50556	133	0	0
T2	5563	43	0	0
T3	431460	383	0	0
T7	152778	229	0	0
T8	2269	29	0	0
T9	45384	64	0	0
T10	139117	0	0	0
T11	494505	2684	0	0
T12	314686	547	0	0
T13	77333	120	0	0
T14	0	125	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	218713	0	0
T1	50556	93	0	0
T2	5563	43	0	0
T3	431460	16	0	0
T7	152778	213	0	0
T8	2269	28	0	0
T9	45384	53	0	0
T10	139117	0	0	0
T11	494505	1169	0	0
T12	314686	435	0	0
T13	77333	120	0	0
T14	0	119	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	218404	0	0
GntImpliesValid_A	438779748	218404	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	218404	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	2858526	0	0
ReadyAndValidImplyGrant_A	438779748	218404	0	0
ReqAndReadyImplyGrant_A	438779748	218404	0	0
ReqImpliesValid_A	438779748	570301	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	218404	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	218404	0	0
T1	50556	99	0	0
T2	5563	47	0	0
T3	431460	9	0	0
T7	152778	187	0	0
T8	2269	28	0	0
T9	45384	64	0	0
T10	139117	0	0	0
T11	494505	625	0	0
T12	314686	466	0	0
T13	77333	119	0	0
T14	0	123	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	218404	0	0
T1	50556	99	0	0
T2	5563	47	0	0
T3	431460	9	0	0
T7	152778	187	0	0
T8	2269	28	0	0
T9	45384	64	0	0
T10	139117	0	0	0
T11	494505	625	0	0
T12	314686	466	0	0
T13	77333	119	0	0
T14	0	123	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	218404	0	0
T1	50556	99	0	0
T2	5563	47	0	0
T3	431460	9	0	0
T7	152778	187	0	0
T8	2269	28	0	0
T9	45384	64	0	0
T10	139117	0	0	0
T11	494505	625	0	0
T12	314686	466	0	0
T13	77333	119	0	0
T14	0	123	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	2858526	0	0
T1	50556	786	0	0
T2	5563	48	0	0
T3	431460	2370	0	0
T7	152778	1402	0	0
T8	2269	27	0	0
T9	45384	445	0	0
T10	139117	1	0	0
T11	494505	4707	0	0
T12	314686	3576	0	0
T13	77333	832	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	218404	0	0
T1	50556	99	0	0
T2	5563	47	0	0
T3	431460	9	0	0
T7	152778	187	0	0
T8	2269	28	0	0
T9	45384	64	0	0
T10	139117	0	0	0
T11	494505	625	0	0
T12	314686	466	0	0
T13	77333	119	0	0
T14	0	123	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	218404	0	0
T1	50556	99	0	0
T2	5563	47	0	0
T3	431460	9	0	0
T7	152778	187	0	0
T8	2269	28	0	0
T9	45384	64	0	0
T10	139117	0	0	0
T11	494505	625	0	0
T12	314686	466	0	0
T13	77333	119	0	0
T14	0	123	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	570301	0	0
T1	50556	151	0	0
T2	5563	47	0	0
T3	431460	9	0	0
T7	152778	187	0	0
T8	2269	30	0	0
T9	45384	74	0	0
T10	139117	0	0	0
T11	494505	821	0	0
T12	314686	474	0	0
T13	77333	134	0	0
T14	0	125	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	218404	0	0
T1	50556	99	0	0
T2	5563	47	0	0
T3	431460	9	0	0
T7	152778	187	0	0
T8	2269	28	0	0
T9	45384	64	0	0
T10	139117	0	0	0
T11	494505	625	0	0
T12	314686	466	0	0
T13	77333	119	0	0
T14	0	123	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T8,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	222882	0	0
GntImpliesValid_A	438779748	222882	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	222882	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	2907379	0	0
ReadyAndValidImplyGrant_A	438779748	222882	0	0
ReqAndReadyImplyGrant_A	438779748	222882	0	0
ReqImpliesValid_A	438779748	589585	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	222882	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	222882	0	0
T1	50556	81	0	0
T2	5563	61	0	0
T3	431460	10	0	0
T7	152778	211	0	0
T8	2269	33	0	0
T9	45384	47	0	0
T10	139117	0	0	0
T11	494505	626	0	0
T12	314686	433	0	0
T13	77333	116	0	0
T14	0	125	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	222882	0	0
T1	50556	81	0	0
T2	5563	61	0	0
T3	431460	10	0	0
T7	152778	211	0	0
T8	2269	33	0	0
T9	45384	47	0	0
T10	139117	0	0	0
T11	494505	626	0	0
T12	314686	433	0	0
T13	77333	116	0	0
T14	0	125	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	222882	0	0
T1	50556	81	0	0
T2	5563	61	0	0
T3	431460	10	0	0
T7	152778	211	0	0
T8	2269	33	0	0
T9	45384	47	0	0
T10	139117	0	0	0
T11	494505	626	0	0
T12	314686	433	0	0
T13	77333	116	0	0
T14	0	125	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	2907379	0	0
T1	50556	612	0	0
T2	5563	62	0	0
T3	431460	2893	0	0
T7	152778	1602	0	0
T8	2269	31	0	0
T9	45384	347	0	0
T10	139117	1	0	0
T11	494505	4698	0	0
T12	314686	3276	0	0
T13	77333	949	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	222882	0	0
T1	50556	81	0	0
T2	5563	61	0	0
T3	431460	10	0	0
T7	152778	211	0	0
T8	2269	33	0	0
T9	45384	47	0	0
T10	139117	0	0	0
T11	494505	626	0	0
T12	314686	433	0	0
T13	77333	116	0	0
T14	0	125	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	222882	0	0
T1	50556	81	0	0
T2	5563	61	0	0
T3	431460	10	0	0
T7	152778	211	0	0
T8	2269	33	0	0
T9	45384	47	0	0
T10	139117	0	0	0
T11	494505	626	0	0
T12	314686	433	0	0
T13	77333	116	0	0
T14	0	125	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	589585	0	0
T1	50556	93	0	0
T2	5563	61	0	0
T3	431460	10	0	0
T7	152778	214	0	0
T8	2269	36	0	0
T9	45384	47	0	0
T10	139117	0	0	0
T11	494505	840	0	0
T12	314686	513	0	0
T13	77333	116	0	0
T14	0	132	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	222882	0	0
T1	50556	81	0	0
T2	5563	61	0	0
T3	431460	10	0	0
T7	152778	211	0	0
T8	2269	33	0	0
T9	45384	47	0	0
T10	139117	0	0	0
T11	494505	626	0	0
T12	314686	433	0	0
T13	77333	116	0	0
T14	0	125	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	209472	0	0
GntImpliesValid_A	438779748	209472	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	209472	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	2903228	0	0
ReadyAndValidImplyGrant_A	438779748	209472	0	0
ReqAndReadyImplyGrant_A	438779748	209472	0	0
ReqImpliesValid_A	438779748	574518	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	0	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	209472	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	209472	0	0
T1	50556	96	0	0
T2	5563	49	0	0
T3	431460	13	0	0
T7	152778	211	0	0
T8	2269	28	0	0
T9	45384	63	0	0
T10	139117	0	0	0
T11	494505	1725	0	0
T12	314686	456	0	0
T13	77333	134	0	0
T14	0	127	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	209472	0	0
T1	50556	96	0	0
T2	5563	49	0	0
T3	431460	13	0	0
T7	152778	211	0	0
T8	2269	28	0	0
T9	45384	63	0	0
T10	139117	0	0	0
T11	494505	1725	0	0
T12	314686	456	0	0
T13	77333	134	0	0
T14	0	127	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	209472	0	0
T1	50556	96	0	0
T2	5563	49	0	0
T3	431460	13	0	0
T7	152778	211	0	0
T8	2269	28	0	0
T9	45384	63	0	0
T10	139117	0	0	0
T11	494505	1725	0	0
T12	314686	456	0	0
T13	77333	134	0	0
T14	0	127	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	2903228	0	0
T1	50556	799	0	0
T2	5563	49	0	0
T3	431460	3131	0	0
T7	152778	1634	0	0
T8	2269	27	0	0
T9	45384	548	0	0
T10	139117	1	0	0
T11	494505	8541	0	0
T12	314686	3662	0	0
T13	77333	1037	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	209472	0	0
T1	50556	96	0	0
T2	5563	49	0	0
T3	431460	13	0	0
T7	152778	211	0	0
T8	2269	28	0	0
T9	45384	63	0	0
T10	139117	0	0	0
T11	494505	1725	0	0
T12	314686	456	0	0
T13	77333	134	0	0
T14	0	127	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	209472	0	0
T1	50556	96	0	0
T2	5563	49	0	0
T3	431460	13	0	0
T7	152778	211	0	0
T8	2269	28	0	0
T9	45384	63	0	0
T10	139117	0	0	0
T11	494505	1725	0	0
T12	314686	456	0	0
T13	77333	134	0	0
T14	0	127	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	574518	0	0
T1	50556	98	0	0
T2	5563	50	0	0
T3	431460	13	0	0
T7	152778	231	0	0
T8	2269	30	0	0
T9	45384	63	0	0
T10	139117	0	0	0
T11	494505	8558	0	0
T12	314686	535	0	0
T13	77333	138	0	0
T14	0	135	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	209472	0	0
T1	50556	96	0	0
T2	5563	49	0	0
T3	431460	13	0	0
T7	152778	211	0	0
T8	2269	28	0	0
T9	45384	63	0	0
T10	139117	0	0	0
T11	494505	1725	0	0
T12	314686	456	0	0
T13	77333	134	0	0
T14	0	127	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	899465	0	0
GntImpliesValid_A	438779748	899465	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	899465	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	11372818	0	0
ReadyAndValidImplyGrant_A	438779748	899465	0	0
ReqAndReadyImplyGrant_A	438779748	899465	0	0
ReqImpliesValid_A	438779748	2386550	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	19536	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	899465	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	899465	0	0
T1	50556	400	0	0
T2	5563	189	0	0
T3	431460	64	0	0
T7	152778	835	0	0
T8	2269	107	0	0
T9	45384	245	0	0
T10	139117	131	0	0
T11	494505	5850	0	0
T12	314686	2607	0	0
T13	77333	450	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	899465	0	0
T1	50556	400	0	0
T2	5563	189	0	0
T3	431460	64	0	0
T7	152778	835	0	0
T8	2269	107	0	0
T9	45384	245	0	0
T10	139117	131	0	0
T11	494505	5850	0	0
T12	314686	2607	0	0
T13	77333	450	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	899465	0	0
T1	50556	400	0	0
T2	5563	189	0	0
T3	431460	64	0	0
T7	152778	835	0	0
T8	2269	107	0	0
T9	45384	245	0	0
T10	139117	131	0	0
T11	494505	5850	0	0
T12	314686	2607	0	0
T13	77333	450	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	11372818	0	0
T1	50556	2495	0	0
T2	5563	1	0	0
T3	431460	21562	0	0
T7	152778	5336	0	0
T8	2269	1	0	0
T9	45384	1748	0	0
T10	139117	436	0	0
T11	494505	29836	0	0
T12	314686	16562	0	0
T13	77333	3118	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	899465	0	0
T1	50556	400	0	0
T2	5563	189	0	0
T3	431460	64	0	0
T7	152778	835	0	0
T8	2269	107	0	0
T9	45384	245	0	0
T10	139117	131	0	0
T11	494505	5850	0	0
T12	314686	2607	0	0
T13	77333	450	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	899465	0	0
T1	50556	400	0	0
T2	5563	189	0	0
T3	431460	64	0	0
T7	152778	835	0	0
T8	2269	107	0	0
T9	45384	245	0	0
T10	139117	131	0	0
T11	494505	5850	0	0
T12	314686	2607	0	0
T13	77333	450	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	2386550	0	0
T1	50556	599	0	0
T2	5563	189	0	0
T3	431460	738	0	0
T7	152778	892	0	0
T8	2269	107	0	0
T9	45384	274	0	0
T10	139117	164	0	0
T11	494505	11798	0	0
T12	314686	3588	0	0
T13	77333	467	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	19536	0	900
T2	5563	4	0	1
T3	431460	0	0	1
T7	152778	0	0	1
T8	2269	2	0	1
T9	45384	0	0	1
T10	139117	0	0	1
T11	494505	131	0	1
T12	314686	1	0	1
T13	77333	0	0	1
T14	8245	12	0	1
T15	0	38	0	0
T16	0	19	0	0
T17	0	690	0	0
T18	0	3	0	0
T19	0	11	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	899465	0	0
T1	50556	400	0	0
T2	5563	189	0	0
T3	431460	64	0	0
T7	152778	835	0	0
T8	2269	107	0	0
T9	45384	245	0	0
T10	139117	131	0	0
T11	494505	5850	0	0
T12	314686	2607	0	0
T13	77333	450	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438779748	438659209	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438779748	880042	0	0
GntImpliesValid_A	438779748	880042	0	0
GrantKnown_A	438779748	438659209	0	0
IdxKnown_A	438779748	438659209	0	0
IndexIsCorrect_A	438779748	880042	0	0
LockArbDecision_A	438779748	0	0	0
NoReadyValidNoGrant_A	438779748	368707525	0	0
ReadyAndValidImplyGrant_A	438779748	880042	0	0
ReqAndReadyImplyGrant_A	438779748	880042	0	0
ReqImpliesValid_A	438779748	13299562	0	0
ReqStaysHighUntilGranted0_M	438779748	0	0	0
RoundRobin_A	438779748	26319	0	900
ValidKnown_A	438779748	438659209	0	0
gen_data_port_assertion.DataFlow_A	438779748	880042	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	880042	0	0
T1	50556	357	0	0
T2	5563	205	0	0
T3	431460	53	0	0
T7	152778	775	0	0
T8	2269	124	0	0
T9	45384	226	0	0
T10	139117	135	0	0
T11	494505	5890	0	0
T12	314686	3067	0	0
T13	77333	504	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	880042	0	0
T1	50556	357	0	0
T2	5563	205	0	0
T3	431460	53	0	0
T7	152778	775	0	0
T8	2269	124	0	0
T9	45384	226	0	0
T10	139117	135	0	0
T11	494505	5890	0	0
T12	314686	3067	0	0
T13	77333	504	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	880042	0	0
T1	50556	357	0	0
T2	5563	205	0	0
T3	431460	53	0	0
T7	152778	775	0	0
T8	2269	124	0	0
T9	45384	226	0	0
T10	139117	135	0	0
T11	494505	5890	0	0
T12	314686	3067	0	0
T13	77333	504	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	368707525	0	0
T1	50556	43515	0	0
T2	5563	1	0	0
T3	431460	412045	0	0
T7	152778	133456	0	0
T8	2269	1	0	0
T9	45384	38909	0	0
T10	139117	115896	0	0
T11	494505	402848	0	0
T12	314686	263374	0	0
T13	77333	66743	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	880042	0	0
T1	50556	357	0	0
T2	5563	205	0	0
T3	431460	53	0	0
T7	152778	775	0	0
T8	2269	124	0	0
T9	45384	226	0	0
T10	139117	135	0	0
T11	494505	5890	0	0
T12	314686	3067	0	0
T13	77333	504	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	880042	0	0
T1	50556	357	0	0
T2	5563	205	0	0
T3	431460	53	0	0
T7	152778	775	0	0
T8	2269	124	0	0
T9	45384	226	0	0
T10	139117	135	0	0
T11	494505	5890	0	0
T12	314686	3067	0	0
T13	77333	504	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	13299562	0	0
T1	50556	2740	0	0
T2	5563	205	0	0
T3	431460	18548	0	0
T7	152778	6220	0	0
T8	2269	124	0	0
T9	45384	1831	0	0
T10	139117	533	0	0
T11	494505	51288	0	0
T12	314686	25357	0	0
T13	77333	4056	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	26319	0	900
T1	50556	2	0	1
T2	5563	5	0	1
T3	431460	0	0	1
T7	152778	0	0	1
T8	2269	1	0	1
T9	45384	0	0	1
T10	139117	0	0	1
T11	494505	40	0	1
T12	314686	5	0	1
T13	77333	2	0	1
T14	0	6	0	0
T15	0	23	0	0
T16	0	15	0	0
T17	0	571	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	438659209	0	0
T1	50556	50489	0	0
T2	5563	5525	0	0
T3	431460	431405	0	0
T7	152778	152700	0	0
T8	2269	2201	0	0
T9	45384	45311	0	0
T10	139117	139111	0	0
T11	494505	493085	0	0
T12	314686	314173	0	0
T13	77333	77285	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438779748	880042	0	0
T1	50556	357	0	0
T2	5563	205	0	0
T3	431460	53	0	0
T7	152778	775	0	0
T8	2269	124	0	0
T9	45384	226	0	0
T10	139117	135	0	0
T11	494505	5890	0	0
T12	314686	3067	0	0
T13	77333	504	0	0