Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1727788	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

274619

1

T1

4

T2

9

T3

112

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	679369	1			T1	34		T2	26		T3	259
values[0x0]	645344	1			T1	5		T2	11		T3	238
values[0x1]	677694	1			T1	35		T2	30		T3	250

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1336112	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

666295

1

T1

26

T2

31

T3

278

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32517	1			T1	2		T2	1		T3	27
valid_sources[0x01]	31465	1			T1	1		T2	3		T7	17
valid_sources[0x02]	31559	1			T3	2		T7	10		T8	21
valid_sources[0x03]	30597	1			T2	1		T7	21		T10	15
valid_sources[0x04]	31046	1			T1	1		T2	1		T3	21
valid_sources[0x05]	31618	1			T2	1		T3	17		T7	16
valid_sources[0x06]	31169	1			T1	1		T3	18		T7	13
valid_sources[0x07]	30584	1			T3	16		T7	11		T10	16
valid_sources[0x08]	30899	1			T3	2		T7	18		T8	43
valid_sources[0x09]	31727	1			T1	2		T3	9		T7	13
valid_sources[0x0a]	31326	1			T7	10		T9	10		T10	17
valid_sources[0x0b]	31183	1			T1	4		T2	1		T7	15
valid_sources[0x0c]	31637	1			T1	2		T7	18		T10	18
valid_sources[0x0d]	31919	1			T1	1		T2	1		T3	29
valid_sources[0x0e]	30781	1			T1	2		T2	2		T7	24
valid_sources[0x0f]	31496	1			T1	2		T3	14		T7	14
valid_sources[0x10]	30408	1			T2	2		T7	6		T10	25
valid_sources[0x11]	31851	1			T1	1		T3	16		T7	14
valid_sources[0x12]	30250	1			T1	1		T3	14		T7	15
valid_sources[0x13]	30703	1			T2	1		T7	20		T10	12
valid_sources[0x14]	32176	1			T1	1		T3	10		T7	21
valid_sources[0x15]	31098	1			T1	4		T3	30		T7	15
valid_sources[0x16]	31890	1			T1	1		T2	1		T3	4
valid_sources[0x17]	31286	1			T1	2		T3	20		T7	17
valid_sources[0x18]	31123	1			T2	1		T7	14		T10	12
valid_sources[0x19]	31217	1			T1	2		T2	2		T3	4
valid_sources[0x1a]	31400	1			T1	1		T7	17		T10	22
valid_sources[0x1b]	31398	1			T1	2		T2	2		T7	18
valid_sources[0x1c]	30723	1			T3	4		T7	16		T9	21
valid_sources[0x1d]	31921	1			T1	2		T2	2		T7	13
valid_sources[0x1e]	32479	1			T1	1		T3	63		T7	9
valid_sources[0x1f]	31615	1			T2	1		T3	17		T7	19
valid_sources[0x20]	31042	1			T1	1		T2	1		T3	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28671

1

T1

2

T2

2

T3

13

values[0x0]

all_enables

biggest_size

217406

1

T2

4

T3

92

T7

46

values[0x1]

all_enables

biggest_size

28542

1

T1

2

T2

3

T3

7

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1740360	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

283928

1

T1

8

T2

6

T3

89

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	691707	1			T1	47		T2	39		T3	216
values[0x0]	640802	1			T1	4		T2	1		T3	218
values[0x1]	691779	1			T1	45		T2	48		T3	247

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1336774	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

687514

1

T1

29

T2

27

T3

217

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32161	1			T2	1		T3	7		T7	15
valid_sources[0x01]	31571	1			T1	2		T2	4		T3	10
valid_sources[0x02]	31897	1			T1	2		T3	10		T7	21
valid_sources[0x03]	31510	1			T2	1		T3	17		T7	21
valid_sources[0x04]	30588	1			T1	3		T2	1		T3	7
valid_sources[0x05]	32329	1			T1	2		T2	1		T3	17
valid_sources[0x06]	30900	1			T2	2		T3	14		T7	15
valid_sources[0x07]	31201	1			T1	1		T2	4		T3	12
valid_sources[0x08]	31499	1			T3	10		T7	16		T8	1
valid_sources[0x09]	31942	1			T1	2		T2	5		T3	20
valid_sources[0x0a]	32329	1			T1	2		T2	5		T3	9
valid_sources[0x0b]	32078	1			T1	1		T2	2		T3	17
valid_sources[0x0c]	31533	1			T1	6		T2	3		T3	8
valid_sources[0x0d]	32304	1			T1	2		T2	2		T3	9
valid_sources[0x0e]	31407	1			T1	2		T2	1		T3	12
valid_sources[0x0f]	30558	1			T2	1		T3	9		T7	19
valid_sources[0x10]	31220	1			T1	1		T2	1		T3	14
valid_sources[0x11]	31551	1			T1	1		T2	1		T3	9
valid_sources[0x12]	31702	1			T2	2		T3	10		T7	35
valid_sources[0x13]	31145	1			T3	20		T7	17		T8	2
valid_sources[0x14]	31393	1			T1	1		T2	1		T3	12
valid_sources[0x15]	32057	1			T1	4		T2	1		T3	13
valid_sources[0x16]	31666	1			T1	3		T3	14		T7	9
valid_sources[0x17]	31363	1			T1	1		T2	2		T3	4
valid_sources[0x18]	31538	1			T1	1		T2	1		T3	3
valid_sources[0x19]	31247	1			T2	1		T3	5		T7	21
valid_sources[0x1a]	31970	1			T1	2		T2	2		T3	11
valid_sources[0x1b]	31366	1			T1	1		T3	21		T7	10
valid_sources[0x1c]	31861	1			T1	1		T3	11		T7	21
valid_sources[0x1d]	32156	1			T1	2		T2	2		T3	6
valid_sources[0x1e]	31375	1			T1	3		T3	7		T7	11
valid_sources[0x1f]	31907	1			T1	1		T3	14		T7	20
valid_sources[0x20]	31810	1			T1	3		T3	7		T7	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29499

1

T1

2

T2

3

T3

8

values[0x0]

all_enables

biggest_size

224992

1

T1

2

T3

71

T7

40

values[0x1]

all_enables

biggest_size

29437

1

T1

4

T2

3

T3

10

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1740194	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

277163

1

T1

10

T2

10

T3

95

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	683930	1			T1	33		T2	38		T3	226
values[0x0]	649991	1			T1	6		T2	5		T3	224
values[0x1]	683436	1			T1	41		T2	40		T3	247

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1345865	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

671492

1

T1

28

T2

34

T3

253

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31957	1			T1	1		T2	2		T3	8
valid_sources[0x01]	31743	1			T1	1		T3	5		T7	13
valid_sources[0x02]	32352	1			T1	2		T2	1		T3	18
valid_sources[0x03]	31548	1			T2	1		T3	8		T7	21
valid_sources[0x04]	31362	1			T3	14		T7	14		T8	1
valid_sources[0x05]	31401	1			T1	1		T2	2		T3	25
valid_sources[0x06]	30618	1			T1	1		T3	10		T7	12
valid_sources[0x07]	30904	1			T2	2		T3	21		T7	17
valid_sources[0x08]	30599	1			T2	2		T7	17		T8	1
valid_sources[0x09]	31482	1			T1	1		T3	21		T7	14
valid_sources[0x0a]	31212	1			T2	1		T3	14		T7	17
valid_sources[0x0b]	32020	1			T1	1		T2	2		T3	8
valid_sources[0x0c]	31467	1			T1	4		T7	27		T8	1
valid_sources[0x0d]	32587	1			T1	1		T2	2		T7	21
valid_sources[0x0e]	31687	1			T1	1		T2	3		T3	9
valid_sources[0x0f]	30688	1			T1	5		T2	2		T7	13
valid_sources[0x10]	32252	1			T1	1		T2	4		T3	14
valid_sources[0x11]	31151	1			T3	20		T7	10		T8	1
valid_sources[0x12]	32386	1			T1	1		T2	1		T3	24
valid_sources[0x13]	32381	1			T1	1		T3	8		T7	19
valid_sources[0x14]	31710	1			T1	1		T2	1		T3	21
valid_sources[0x15]	31209	1			T2	3		T3	43		T7	15
valid_sources[0x16]	31477	1			T1	2		T2	1		T7	16
valid_sources[0x17]	31270	1			T1	3		T2	3		T3	8
valid_sources[0x18]	30716	1			T1	2		T7	15		T8	4
valid_sources[0x19]	31174	1			T2	1		T3	39		T7	16
valid_sources[0x1a]	30936	1			T2	4		T3	12		T7	20
valid_sources[0x1b]	31860	1			T1	1		T3	32		T7	16
valid_sources[0x1c]	31058	1			T2	3		T3	19		T7	15
valid_sources[0x1d]	31491	1			T3	2		T7	15		T8	1
valid_sources[0x1e]	31420	1			T1	1		T2	1		T3	1
valid_sources[0x1f]	32969	1			T2	1		T3	20		T7	18
valid_sources[0x20]	31598	1			T1	2		T7	18		T8	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28859

1

T1

3

T2

4

T3

8

values[0x0]

all_enables

biggest_size

219326

1

T1

2

T2

3

T3

77

values[0x1]

all_enables

biggest_size

28978

1

T1

5

T2

3

T3

10