Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8312072	0	0
GntImpliesValid_A	2147483647	8312072	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8312072	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	451563214	0	0
ReadyAndValidImplyGrant_A	2147483647	8312072	0	0
ReqAndReadyImplyGrant_A	2147483647	8312072	0	0
ReqImpliesValid_A	2147483647	34566348	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	50564	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8312072	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	208560	206928	0	0
T2	215208	213552	0	0
T3	19080024	19078368	0	0
T7	14832096	14800512	0	0
T8	9207456	9207048	0	0
T9	285720	285120	0	0
T10	128496	127176	0	0
T11	4776888	4776744	0	0
T12	1253232	1251480	0	0
T13	1014672	1012920	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8312072	0	0
T1	208560	2864	0	0
T2	215208	5291	0	0
T3	19080024	2125	0	0
T7	14832096	62059	0	0
T8	9207456	429	0	0
T9	285720	472	0	0
T10	128496	3656	0	0
T11	4776888	419	0	0
T12	1253232	3429	0	0
T13	1014672	2927	0	0
T14	0	952	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8312072	0	0
T1	208560	2864	0	0
T2	215208	5291	0	0
T3	19080024	2125	0	0
T7	14832096	62059	0	0
T8	9207456	429	0	0
T9	285720	472	0	0
T10	128496	3656	0	0
T11	4776888	419	0	0
T12	1253232	3429	0	0
T13	1014672	2927	0	0
T14	0	952	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	208560	206928	0	0
T2	215208	213552	0	0
T3	19080024	19078368	0	0
T7	14832096	14800512	0	0
T8	9207456	9207048	0	0
T9	285720	285120	0	0
T10	128496	127176	0	0
T11	4776888	4776744	0	0
T12	1253232	1251480	0	0
T13	1014672	1012920	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	208560	206928	0	0
T2	215208	213552	0	0
T3	19080024	19078368	0	0
T7	14832096	14800512	0	0
T8	9207456	9207048	0	0
T9	285720	285120	0	0
T10	128496	127176	0	0
T11	4776888	4776744	0	0
T12	1253232	1251480	0	0
T13	1014672	1012920	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8312072	0	0
T1	208560	2864	0	0
T2	215208	5291	0	0
T3	19080024	2125	0	0
T7	14832096	62059	0	0
T8	9207456	429	0	0
T9	285720	472	0	0
T10	128496	3656	0	0
T11	4776888	419	0	0
T12	1253232	3429	0	0
T13	1014672	2927	0	0
T14	0	952	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	451563214	0	0
T1	208560	5110	0	0
T2	215208	6369	0	0
T3	19080024	673340	0	0
T7	14832096	900892	0	0
T8	9207456	479722	0	0
T9	285720	13956	0	0
T10	128496	582	0	0
T11	4776888	167166	0	0
T12	1253232	74599	0	0
T13	1014672	57111	0	0
T14	0	1662	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8312072	0	0
T1	208560	2864	0	0
T2	215208	5291	0	0
T3	19080024	2125	0	0
T7	14832096	62059	0	0
T8	9207456	429	0	0
T9	285720	472	0	0
T10	128496	3656	0	0
T11	4776888	419	0	0
T12	1253232	3429	0	0
T13	1014672	2927	0	0
T14	0	952	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8312072	0	0
T1	208560	2864	0	0
T2	215208	5291	0	0
T3	19080024	2125	0	0
T7	14832096	62059	0	0
T8	9207456	429	0	0
T9	285720	472	0	0
T10	128496	3656	0	0
T11	4776888	419	0	0
T12	1253232	3429	0	0
T13	1014672	2927	0	0
T14	0	952	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34566348	0	0
T1	208560	3350	0	0
T2	215208	6238	0	0
T3	19080024	3816	0	0
T7	14832096	207945	0	0
T8	9207456	21724	0	0
T9	285720	974	0	0
T10	128496	6119	0	0
T11	4776888	590	0	0
T12	1253232	7580	0	0
T13	1014672	5877	0	0
T14	0	1106	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50564	0	21600
T1	17380	6	0	2
T2	17934	27	0	2
T3	1590002	0	0	2
T7	1236008	47	0	2
T8	767288	0	0	2
T9	23810	0	0	2
T10	10708	0	0	2
T11	398074	0	0	2
T12	104436	0	0	2
T13	84556	0	0	2
T14	0	8	0	0
T15	0	2	0	0
T16	0	21	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	6	0	0
T20	0	16	0	0
T21	0	7	0	0
T22	0	12	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	208560	206928	0	0
T2	215208	213552	0	0
T3	19080024	19078368	0	0
T7	14832096	14800512	0	0
T8	9207456	9207048	0	0
T9	285720	285120	0	0
T10	128496	127176	0	0
T11	4776888	4776744	0	0
T12	1253232	1251480	0	0
T13	1014672	1012920	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8312072	0	0
T1	208560	2864	0	0
T2	215208	5291	0	0
T3	19080024	2125	0	0
T7	14832096	62059	0	0
T8	9207456	429	0	0
T9	285720	472	0	0
T10	128496	3656	0	0
T11	4776888	419	0	0
T12	1253232	3429	0	0
T13	1014672	2927	0	0
T14	0	952	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	933721	0	0
GntImpliesValid_A	413400564	933721	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	933721	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	12376943	0	0
ReadyAndValidImplyGrant_A	413400564	933721	0	0
ReqAndReadyImplyGrant_A	413400564	933721	0	0
ReqImpliesValid_A	413400564	2586622	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	933721	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	933721	0	0
T1	8690	312	0	0
T2	8967	644	0	0
T3	795001	226	0	0
T7	618004	7201	0	0
T8	383644	45	0	0
T9	11905	63	0	0
T10	5354	315	0	0
T11	199037	46	0	0
T12	52218	402	0	0
T13	42278	347	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	933721	0	0
T1	8690	312	0	0
T2	8967	644	0	0
T3	795001	226	0	0
T7	618004	7201	0	0
T8	383644	45	0	0
T9	11905	63	0	0
T10	5354	315	0	0
T11	199037	46	0	0
T12	52218	402	0	0
T13	42278	347	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	933721	0	0
T1	8690	312	0	0
T2	8967	644	0	0
T3	795001	226	0	0
T7	618004	7201	0	0
T8	383644	45	0	0
T9	11905	63	0	0
T10	5354	315	0	0
T11	199037	46	0	0
T12	52218	402	0	0
T13	42278	347	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	12376943	0	0
T1	8690	263	0	0
T2	8967	470	0	0
T3	795001	852	0	0
T7	618004	46510	0	0
T8	383644	17261	0	0
T9	11905	505	0	0
T10	5354	237	0	0
T11	199037	161	0	0
T12	52218	3029	0	0
T13	42278	2578	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	933721	0	0
T1	8690	312	0	0
T2	8967	644	0	0
T3	795001	226	0	0
T7	618004	7201	0	0
T8	383644	45	0	0
T9	11905	63	0	0
T10	5354	315	0	0
T11	199037	46	0	0
T12	52218	402	0	0
T13	42278	347	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	933721	0	0
T1	8690	312	0	0
T2	8967	644	0	0
T3	795001	226	0	0
T7	618004	7201	0	0
T8	383644	45	0	0
T9	11905	63	0	0
T10	5354	315	0	0
T11	199037	46	0	0
T12	52218	402	0	0
T13	42278	347	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	2586622	0	0
T1	8690	362	0	0
T2	8967	819	0	0
T3	795001	348	0	0
T7	618004	13048	0	0
T8	383644	1508	0	0
T9	11905	104	0	0
T10	5354	394	0	0
T11	199037	53	0	0
T12	52218	590	0	0
T13	42278	587	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	933721	0	0
T1	8690	312	0	0
T2	8967	644	0	0
T3	795001	226	0	0
T7	618004	7201	0	0
T8	383644	45	0	0
T9	11905	63	0	0
T10	5354	315	0	0
T11	199037	46	0	0
T12	52218	402	0	0
T13	42278	347	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	917626	0	0
GntImpliesValid_A	413400564	917626	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	917626	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	12261815	0	0
ReadyAndValidImplyGrant_A	413400564	917626	0	0
ReqAndReadyImplyGrant_A	413400564	917626	0	0
ReqImpliesValid_A	413400564	2503352	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	917626	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	917626	0	0
T1	8690	341	0	0
T2	8967	620	0	0
T3	795001	239	0	0
T7	618004	6620	0	0
T8	383644	50	0	0
T9	11905	54	0	0
T10	5354	315	0	0
T11	199037	56	0	0
T12	52218	394	0	0
T13	42278	308	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	917626	0	0
T1	8690	341	0	0
T2	8967	620	0	0
T3	795001	239	0	0
T7	618004	6620	0	0
T8	383644	50	0	0
T9	11905	54	0	0
T10	5354	315	0	0
T11	199037	56	0	0
T12	52218	394	0	0
T13	42278	308	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	917626	0	0
T1	8690	341	0	0
T2	8967	620	0	0
T3	795001	239	0	0
T7	618004	6620	0	0
T8	383644	50	0	0
T9	11905	54	0	0
T10	5354	315	0	0
T11	199037	56	0	0
T12	52218	394	0	0
T13	42278	308	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	12261815	0	0
T1	8690	285	0	0
T2	8967	444	0	0
T3	795001	1031	0	0
T7	618004	46878	0	0
T8	383644	17681	0	0
T9	11905	396	0	0
T10	5354	227	0	0
T11	199037	246	0	0
T12	52218	2849	0	0
T13	42278	2293	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	917626	0	0
T1	8690	341	0	0
T2	8967	620	0	0
T3	795001	239	0	0
T7	618004	6620	0	0
T8	383644	50	0	0
T9	11905	54	0	0
T10	5354	315	0	0
T11	199037	56	0	0
T12	52218	394	0	0
T13	42278	308	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	917626	0	0
T1	8690	341	0	0
T2	8967	620	0	0
T3	795001	239	0	0
T7	618004	6620	0	0
T8	383644	50	0	0
T9	11905	54	0	0
T10	5354	315	0	0
T11	199037	56	0	0
T12	52218	394	0	0
T13	42278	308	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	2503352	0	0
T1	8690	398	0	0
T2	8967	797	0	0
T3	795001	332	0	0
T7	618004	14378	0	0
T8	383644	385	0	0
T9	11905	84	0	0
T10	5354	404	0	0
T11	199037	70	0	0
T12	52218	655	0	0
T13	42278	451	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	917626	0	0
T1	8690	341	0	0
T2	8967	620	0	0
T3	795001	239	0	0
T7	618004	6620	0	0
T8	383644	50	0	0
T9	11905	54	0	0
T10	5354	315	0	0
T11	199037	56	0	0
T12	52218	394	0	0
T13	42278	308	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	229694	0	0
GntImpliesValid_A	413400564	229694	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	229694	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	3076147	0	0
ReadyAndValidImplyGrant_A	413400564	229694	0	0
ReqAndReadyImplyGrant_A	413400564	229694	0	0
ReqImpliesValid_A	413400564	602377	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	229694	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	229694	0	0
T1	8690	82	0	0
T2	8967	136	0	0
T3	795001	51	0	0
T7	618004	1597	0	0
T8	383644	13	0	0
T9	11905	12	0	0
T10	5354	504	0	0
T11	199037	9	0	0
T12	52218	99	0	0
T13	42278	81	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	229694	0	0
T1	8690	82	0	0
T2	8967	136	0	0
T3	795001	51	0	0
T7	618004	1597	0	0
T8	383644	13	0	0
T9	11905	12	0	0
T10	5354	504	0	0
T11	199037	9	0	0
T12	52218	99	0	0
T13	42278	81	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	229694	0	0
T1	8690	82	0	0
T2	8967	136	0	0
T3	795001	51	0	0
T7	618004	1597	0	0
T8	383644	13	0	0
T9	11905	12	0	0
T10	5354	504	0	0
T11	199037	9	0	0
T12	52218	99	0	0
T13	42278	81	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	3076147	0	0
T1	8690	80	0	0
T2	8967	130	0	0
T3	795001	189	0	0
T7	618004	10642	0	0
T8	383644	3519	0	0
T9	11905	153	0	0
T10	5354	6	0	0
T11	199037	36	0	0
T12	52218	735	0	0
T13	42278	543	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	229694	0	0
T1	8690	82	0	0
T2	8967	136	0	0
T3	795001	51	0	0
T7	618004	1597	0	0
T8	383644	13	0	0
T9	11905	12	0	0
T10	5354	504	0	0
T11	199037	9	0	0
T12	52218	99	0	0
T13	42278	81	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	229694	0	0
T1	8690	82	0	0
T2	8967	136	0	0
T3	795001	51	0	0
T7	618004	1597	0	0
T8	383644	13	0	0
T9	11905	12	0	0
T10	5354	504	0	0
T11	199037	9	0	0
T12	52218	99	0	0
T13	42278	81	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	602377	0	0
T1	8690	85	0	0
T2	8967	143	0	0
T3	795001	63	0	0
T7	618004	4014	0	0
T8	383644	149	0	0
T9	11905	12	0	0
T10	5354	1003	0	0
T11	199037	9	0	0
T12	52218	121	0	0
T13	42278	98	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	229694	0	0
T1	8690	82	0	0
T2	8967	136	0	0
T3	795001	51	0	0
T7	618004	1597	0	0
T8	383644	13	0	0
T9	11905	12	0	0
T10	5354	504	0	0
T11	199037	9	0	0
T12	52218	99	0	0
T13	42278	81	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	237021	0	0
GntImpliesValid_A	413400564	237021	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	237021	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	3052989	0	0
ReadyAndValidImplyGrant_A	413400564	237021	0	0
ReqAndReadyImplyGrant_A	413400564	237021	0	0
ReqImpliesValid_A	413400564	579964	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	237021	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	237021	0	0
T1	8690	76	0	0
T2	8967	137	0	0
T3	795001	53	0	0
T7	618004	1546	0	0
T8	383644	16	0	0
T9	11905	17	0	0
T10	5354	0	0	0
T11	199037	11	0	0
T12	52218	101	0	0
T13	42278	81	0	0
T14	0	65	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	237021	0	0
T1	8690	76	0	0
T2	8967	137	0	0
T3	795001	53	0	0
T7	618004	1546	0	0
T8	383644	16	0	0
T9	11905	17	0	0
T10	5354	0	0	0
T11	199037	11	0	0
T12	52218	101	0	0
T13	42278	81	0	0
T14	0	65	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	237021	0	0
T1	8690	76	0	0
T2	8967	137	0	0
T3	795001	53	0	0
T7	618004	1546	0	0
T8	383644	16	0	0
T9	11905	17	0	0
T10	5354	0	0	0
T11	199037	11	0	0
T12	52218	101	0	0
T13	42278	81	0	0
T14	0	65	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	3052989	0	0
T1	8690	75	0	0
T2	8967	135	0	0
T3	795001	217	0	0
T7	618004	11959	0	0
T8	383644	3533	0	0
T9	11905	148	0	0
T10	5354	1	0	0
T11	199037	61	0	0
T12	52218	775	0	0
T13	42278	608	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	237021	0	0
T1	8690	76	0	0
T2	8967	137	0	0
T3	795001	53	0	0
T7	618004	1546	0	0
T8	383644	16	0	0
T9	11905	17	0	0
T10	5354	0	0	0
T11	199037	11	0	0
T12	52218	101	0	0
T13	42278	81	0	0
T14	0	65	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	237021	0	0
T1	8690	76	0	0
T2	8967	137	0	0
T3	795001	53	0	0
T7	618004	1546	0	0
T8	383644	16	0	0
T9	11905	17	0	0
T10	5354	0	0	0
T11	199037	11	0	0
T12	52218	101	0	0
T13	42278	81	0	0
T14	0	65	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	579964	0	0
T1	8690	78	0	0
T2	8967	140	0	0
T3	795001	54	0	0
T7	618004	2368	0	0
T8	383644	16	0	0
T9	11905	17	0	0
T10	5354	0	0	0
T11	199037	11	0	0
T12	52218	114	0	0
T13	42278	91	0	0
T14	0	68	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	237021	0	0
T1	8690	76	0	0
T2	8967	137	0	0
T3	795001	53	0	0
T7	618004	1546	0	0
T8	383644	16	0	0
T9	11905	17	0	0
T10	5354	0	0	0
T11	199037	11	0	0
T12	52218	101	0	0
T13	42278	81	0	0
T14	0	65	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	223082	0	0
GntImpliesValid_A	413400564	223082	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	223082	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	5275497	0	0
ReadyAndValidImplyGrant_A	413400564	223082	0	0
ReqAndReadyImplyGrant_A	413400564	223082	0	0
ReqImpliesValid_A	413400564	1100052	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	223082	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	223082	0	0
T1	8690	83	0	0
T2	8967	128	0	0
T3	795001	60	0	0
T7	618004	1043	0	0
T8	383644	14	0	0
T9	11905	14	0	0
T10	5354	0	0	0
T11	199037	13	0	0
T12	52218	111	0	0
T13	42278	92	0	0
T14	0	81	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	223082	0	0
T1	8690	83	0	0
T2	8967	128	0	0
T3	795001	60	0	0
T7	618004	1043	0	0
T8	383644	14	0	0
T9	11905	14	0	0
T10	5354	0	0	0
T11	199037	13	0	0
T12	52218	111	0	0
T13	42278	92	0	0
T14	0	81	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	223082	0	0
T1	8690	83	0	0
T2	8967	128	0	0
T3	795001	60	0	0
T7	618004	1043	0	0
T8	383644	14	0	0
T9	11905	14	0	0
T10	5354	0	0	0
T11	199037	13	0	0
T12	52218	111	0	0
T13	42278	92	0	0
T14	0	81	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	5275497	0	0
T1	8690	868	0	0
T2	8967	694	0	0
T3	795001	921	0	0
T7	618004	17378	0	0
T8	383644	2415	0	0
T9	11905	120	0	0
T10	5354	0	0	0
T11	199037	60	0	0
T12	52218	1836	0	0
T13	42278	1124	0	0
T14	0	511	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	223082	0	0
T1	8690	83	0	0
T2	8967	128	0	0
T3	795001	60	0	0
T7	618004	1043	0	0
T8	383644	14	0	0
T9	11905	14	0	0
T10	5354	0	0	0
T11	199037	13	0	0
T12	52218	111	0	0
T13	42278	92	0	0
T14	0	81	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	223082	0	0
T1	8690	83	0	0
T2	8967	128	0	0
T3	795001	60	0	0
T7	618004	1043	0	0
T8	383644	14	0	0
T9	11905	14	0	0
T10	5354	0	0	0
T11	199037	13	0	0
T12	52218	111	0	0
T13	42278	92	0	0
T14	0	81	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	1100052	0	0
T1	8690	165	0	0
T2	8967	249	0	0
T3	795001	121	0	0
T7	618004	1778	0	0
T8	383644	693	0	0
T9	11905	28	0	0
T10	5354	0	0	0
T11	199037	13	0	0
T12	52218	184	0	0
T13	42278	148	0	0
T14	0	117	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	223082	0	0
T1	8690	83	0	0
T2	8967	128	0	0
T3	795001	60	0	0
T7	618004	1043	0	0
T8	383644	14	0	0
T9	11905	14	0	0
T10	5354	0	0	0
T11	199037	13	0	0
T12	52218	111	0	0
T13	42278	92	0	0
T14	0	81	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	232770	0	0
GntImpliesValid_A	413400564	232770	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	232770	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	4830358	0	0
ReadyAndValidImplyGrant_A	413400564	232770	0	0
ReqAndReadyImplyGrant_A	413400564	232770	0	0
ReqImpliesValid_A	413400564	1099305	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	232770	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232770	0	0
T1	8690	67	0	0
T2	8967	140	0	0
T3	795001	58	0	0
T7	618004	1643	0	0
T8	383644	11	0	0
T9	11905	13	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	97	0	0
T13	42278	78	0	0
T14	0	52	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232770	0	0
T1	8690	67	0	0
T2	8967	140	0	0
T3	795001	58	0	0
T7	618004	1643	0	0
T8	383644	11	0	0
T9	11905	13	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	97	0	0
T13	42278	78	0	0
T14	0	52	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232770	0	0
T1	8690	67	0	0
T2	8967	140	0	0
T3	795001	58	0	0
T7	618004	1643	0	0
T8	383644	11	0	0
T9	11905	13	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	97	0	0
T13	42278	78	0	0
T14	0	52	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	4830358	0	0
T1	8690	350	0	0
T2	8967	898	0	0
T3	795001	1498	0	0
T7	618004	15343	0	0
T8	383644	3804	0	0
T9	11905	150	0	0
T10	5354	0	0	0
T11	199037	45	0	0
T12	52218	1904	0	0
T13	42278	1879	0	0
T14	0	332	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232770	0	0
T1	8690	67	0	0
T2	8967	140	0	0
T3	795001	58	0	0
T7	618004	1643	0	0
T8	383644	11	0	0
T9	11905	13	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	97	0	0
T13	42278	78	0	0
T14	0	52	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232770	0	0
T1	8690	67	0	0
T2	8967	140	0	0
T3	795001	58	0	0
T7	618004	1643	0	0
T8	383644	11	0	0
T9	11905	13	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	97	0	0
T13	42278	78	0	0
T14	0	52	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	1099305	0	0
T1	8690	115	0	0
T2	8967	280	0	0
T3	795001	105	0	0
T7	618004	11226	0	0
T8	383644	11	0	0
T9	11905	13	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	190	0	0
T13	42278	318	0	0
T14	0	103	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232770	0	0
T1	8690	67	0	0
T2	8967	140	0	0
T3	795001	58	0	0
T7	618004	1643	0	0
T8	383644	11	0	0
T9	11905	13	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	97	0	0
T13	42278	78	0	0
T14	0	52	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	219342	0	0
GntImpliesValid_A	413400564	219342	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	219342	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	4995418	0	0
ReadyAndValidImplyGrant_A	413400564	219342	0	0
ReqAndReadyImplyGrant_A	413400564	219342	0	0
ReqImpliesValid_A	413400564	992832	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	219342	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	219342	0	0
T1	8690	87	0	0
T2	8967	138	0	0
T3	795001	76	0	0
T7	618004	1486	0	0
T8	383644	11	0	0
T9	11905	19	0	0
T10	5354	0	0	0
T11	199037	6	0	0
T12	52218	93	0	0
T13	42278	85	0	0
T14	0	55	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	219342	0	0
T1	8690	87	0	0
T2	8967	138	0	0
T3	795001	76	0	0
T7	618004	1486	0	0
T8	383644	11	0	0
T9	11905	19	0	0
T10	5354	0	0	0
T11	199037	6	0	0
T12	52218	93	0	0
T13	42278	85	0	0
T14	0	55	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	219342	0	0
T1	8690	87	0	0
T2	8967	138	0	0
T3	795001	76	0	0
T7	618004	1486	0	0
T8	383644	11	0	0
T9	11905	19	0	0
T10	5354	0	0	0
T11	199037	6	0	0
T12	52218	93	0	0
T13	42278	85	0	0
T14	0	55	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	4995418	0	0
T1	8690	753	0	0
T2	8967	943	0	0
T3	795001	1547	0	0
T7	618004	26321	0	0
T8	383644	1285	0	0
T9	11905	260	0	0
T10	5354	0	0	0
T11	199037	26	0	0
T12	52218	2536	0	0
T13	42278	960	0	0
T14	0	489	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	219342	0	0
T1	8690	87	0	0
T2	8967	138	0	0
T3	795001	76	0	0
T7	618004	1486	0	0
T8	383644	11	0	0
T9	11905	19	0	0
T10	5354	0	0	0
T11	199037	6	0	0
T12	52218	93	0	0
T13	42278	85	0	0
T14	0	55	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	219342	0	0
T1	8690	87	0	0
T2	8967	138	0	0
T3	795001	76	0	0
T7	618004	1486	0	0
T8	383644	11	0	0
T9	11905	19	0	0
T10	5354	0	0	0
T11	199037	6	0	0
T12	52218	93	0	0
T13	42278	85	0	0
T14	0	55	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	992832	0	0
T1	8690	173	0	0
T2	8967	247	0	0
T3	795001	333	0	0
T7	618004	3734	0	0
T8	383644	11	0	0
T9	11905	37	0	0
T10	5354	0	0	0
T11	199037	6	0	0
T12	52218	362	0	0
T13	42278	116	0	0
T14	0	82	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	219342	0	0
T1	8690	87	0	0
T2	8967	138	0	0
T3	795001	76	0	0
T7	618004	1486	0	0
T8	383644	11	0	0
T9	11905	19	0	0
T10	5354	0	0	0
T11	199037	6	0	0
T12	52218	93	0	0
T13	42278	85	0	0
T14	0	55	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	223491	0	0
GntImpliesValid_A	413400564	223491	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	223491	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	5299042	0	0
ReadyAndValidImplyGrant_A	413400564	223491	0	0
ReqAndReadyImplyGrant_A	413400564	223491	0	0
ReqImpliesValid_A	413400564	1077415	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	223491	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	223491	0	0
T1	8690	71	0	0
T2	8967	135	0	0
T3	795001	56	0	0
T7	618004	1514	0	0
T8	383644	12	0	0
T9	11905	18	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	88	0	0
T13	42278	68	0	0
T14	0	62	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	223491	0	0
T1	8690	71	0	0
T2	8967	135	0	0
T3	795001	56	0	0
T7	618004	1514	0	0
T8	383644	12	0	0
T9	11905	18	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	88	0	0
T13	42278	68	0	0
T14	0	62	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	223491	0	0
T1	8690	71	0	0
T2	8967	135	0	0
T3	795001	56	0	0
T7	618004	1514	0	0
T8	383644	12	0	0
T9	11905	18	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	88	0	0
T13	42278	68	0	0
T14	0	62	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	5299042	0	0
T1	8690	1352	0	0
T2	8967	779	0	0
T3	795001	1010	0	0
T7	618004	14236	0	0
T8	383644	1189	0	0
T9	11905	123	0	0
T10	5354	0	0	0
T11	199037	80	0	0
T12	52218	3296	0	0
T13	42278	806	0	0
T14	0	330	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	223491	0	0
T1	8690	71	0	0
T2	8967	135	0	0
T3	795001	56	0	0
T7	618004	1514	0	0
T8	383644	12	0	0
T9	11905	18	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	88	0	0
T13	42278	68	0	0
T14	0	62	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	223491	0	0
T1	8690	71	0	0
T2	8967	135	0	0
T3	795001	56	0	0
T7	618004	1514	0	0
T8	383644	12	0	0
T9	11905	18	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	88	0	0
T13	42278	68	0	0
T14	0	62	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	1077415	0	0
T1	8690	192	0	0
T2	8967	228	0	0
T3	795001	194	0	0
T7	618004	2286	0	0
T8	383644	12	0	0
T9	11905	45	0	0
T10	5354	0	0	0
T11	199037	16	0	0
T12	52218	375	0	0
T13	42278	84	0	0
T14	0	68	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	223491	0	0
T1	8690	71	0	0
T2	8967	135	0	0
T3	795001	56	0	0
T7	618004	1514	0	0
T8	383644	12	0	0
T9	11905	18	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	88	0	0
T13	42278	68	0	0
T14	0	62	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	230656	0	0
GntImpliesValid_A	413400564	230656	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	230656	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	3023062	0	0
ReadyAndValidImplyGrant_A	413400564	230656	0	0
ReqAndReadyImplyGrant_A	413400564	230656	0	0
ReqImpliesValid_A	413400564	569835	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	230656	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	230656	0	0
T1	8690	59	0	0
T2	8967	141	0	0
T3	795001	68	0	0
T7	618004	1491	0	0
T8	383644	11	0	0
T9	11905	13	0	0
T10	5354	931	0	0
T11	199037	9	0	0
T12	52218	84	0	0
T13	42278	92	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	230656	0	0
T1	8690	59	0	0
T2	8967	141	0	0
T3	795001	68	0	0
T7	618004	1491	0	0
T8	383644	11	0	0
T9	11905	13	0	0
T10	5354	931	0	0
T11	199037	9	0	0
T12	52218	84	0	0
T13	42278	92	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	230656	0	0
T1	8690	59	0	0
T2	8967	141	0	0
T3	795001	68	0	0
T7	618004	1491	0	0
T8	383644	11	0	0
T9	11905	13	0	0
T10	5354	931	0	0
T11	199037	9	0	0
T12	52218	84	0	0
T13	42278	92	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	3023062	0	0
T1	8690	57	0	0
T2	8967	135	0	0
T3	795001	297	0	0
T7	618004	10245	0	0
T8	383644	3420	0	0
T9	11905	89	0	0
T10	5354	62	0	0
T11	199037	35	0	0
T12	52218	659	0	0
T13	42278	712	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	230656	0	0
T1	8690	59	0	0
T2	8967	141	0	0
T3	795001	68	0	0
T7	618004	1491	0	0
T8	383644	11	0	0
T9	11905	13	0	0
T10	5354	931	0	0
T11	199037	9	0	0
T12	52218	84	0	0
T13	42278	92	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	230656	0	0
T1	8690	59	0	0
T2	8967	141	0	0
T3	795001	68	0	0
T7	618004	1491	0	0
T8	383644	11	0	0
T9	11905	13	0	0
T10	5354	931	0	0
T11	199037	9	0	0
T12	52218	84	0	0
T13	42278	92	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	569835	0	0
T1	8690	62	0	0
T2	8967	148	0	0
T3	795001	74	0	0
T7	618004	2170	0	0
T8	383644	11	0	0
T9	11905	13	0	0
T10	5354	1801	0	0
T11	199037	9	0	0
T12	52218	156	0	0
T13	42278	119	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	230656	0	0
T1	8690	59	0	0
T2	8967	141	0	0
T3	795001	68	0	0
T7	618004	1491	0	0
T8	383644	11	0	0
T9	11905	13	0	0
T10	5354	931	0	0
T11	199037	9	0	0
T12	52218	84	0	0
T13	42278	92	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	232624	0	0
GntImpliesValid_A	413400564	232624	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	232624	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	3066626	0	0
ReadyAndValidImplyGrant_A	413400564	232624	0	0
ReqAndReadyImplyGrant_A	413400564	232624	0	0
ReqImpliesValid_A	413400564	584079	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	232624	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232624	0	0
T1	8690	83	0	0
T2	8967	154	0	0
T3	795001	67	0	0
T7	618004	2471	0	0
T8	383644	9	0	0
T9	11905	12	0	0
T10	5354	0	0	0
T11	199037	11	0	0
T12	52218	85	0	0
T13	42278	74	0	0
T14	0	62	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232624	0	0
T1	8690	83	0	0
T2	8967	154	0	0
T3	795001	67	0	0
T7	618004	2471	0	0
T8	383644	9	0	0
T9	11905	12	0	0
T10	5354	0	0	0
T11	199037	11	0	0
T12	52218	85	0	0
T13	42278	74	0	0
T14	0	62	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232624	0	0
T1	8690	83	0	0
T2	8967	154	0	0
T3	795001	67	0	0
T7	618004	2471	0	0
T8	383644	9	0	0
T9	11905	12	0	0
T10	5354	0	0	0
T11	199037	11	0	0
T12	52218	85	0	0
T13	42278	74	0	0
T14	0	62	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	3066626	0	0
T1	8690	83	0	0
T2	8967	142	0	0
T3	795001	258	0	0
T7	618004	13561	0	0
T8	383644	2762	0	0
T9	11905	76	0	0
T10	5354	1	0	0
T11	199037	38	0	0
T12	52218	658	0	0
T13	42278	608	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232624	0	0
T1	8690	83	0	0
T2	8967	154	0	0
T3	795001	67	0	0
T7	618004	2471	0	0
T8	383644	9	0	0
T9	11905	12	0	0
T10	5354	0	0	0
T11	199037	11	0	0
T12	52218	85	0	0
T13	42278	74	0	0
T14	0	62	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232624	0	0
T1	8690	83	0	0
T2	8967	154	0	0
T3	795001	67	0	0
T7	618004	2471	0	0
T8	383644	9	0	0
T9	11905	12	0	0
T10	5354	0	0	0
T11	199037	11	0	0
T12	52218	85	0	0
T13	42278	74	0	0
T14	0	62	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	584079	0	0
T1	8690	84	0	0
T2	8967	167	0	0
T3	795001	79	0	0
T7	618004	11102	0	0
T8	383644	9	0	0
T9	11905	12	0	0
T10	5354	0	0	0
T11	199037	18	0	0
T12	52218	85	0	0
T13	42278	85	0	0
T14	0	63	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232624	0	0
T1	8690	83	0	0
T2	8967	154	0	0
T3	795001	67	0	0
T7	618004	2471	0	0
T8	383644	9	0	0
T9	11905	12	0	0
T10	5354	0	0	0
T11	199037	11	0	0
T12	52218	85	0	0
T13	42278	74	0	0
T14	0	62	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	236309	0	0
GntImpliesValid_A	413400564	236309	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	236309	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	2991326	0	0
ReadyAndValidImplyGrant_A	413400564	236309	0	0
ReqAndReadyImplyGrant_A	413400564	236309	0	0
ReqImpliesValid_A	413400564	596723	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	236309	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	236309	0	0
T1	8690	89	0	0
T2	8967	137	0	0
T3	795001	46	0	0
T7	618004	1592	0	0
T8	383644	12	0	0
T9	11905	12	0	0
T10	5354	0	0	0
T11	199037	9	0	0
T12	52218	94	0	0
T13	42278	78	0	0
T14	0	63	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	236309	0	0
T1	8690	89	0	0
T2	8967	137	0	0
T3	795001	46	0	0
T7	618004	1592	0	0
T8	383644	12	0	0
T9	11905	12	0	0
T10	5354	0	0	0
T11	199037	9	0	0
T12	52218	94	0	0
T13	42278	78	0	0
T14	0	63	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	236309	0	0
T1	8690	89	0	0
T2	8967	137	0	0
T3	795001	46	0	0
T7	618004	1592	0	0
T8	383644	12	0	0
T9	11905	12	0	0
T10	5354	0	0	0
T11	199037	9	0	0
T12	52218	94	0	0
T13	42278	78	0	0
T14	0	63	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	2991326	0	0
T1	8690	87	0	0
T2	8967	135	0	0
T3	795001	179	0	0
T7	618004	11309	0	0
T8	383644	3200	0	0
T9	11905	70	0	0
T10	5354	1	0	0
T11	199037	16	0	0
T12	52218	694	0	0
T13	42278	571	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	236309	0	0
T1	8690	89	0	0
T2	8967	137	0	0
T3	795001	46	0	0
T7	618004	1592	0	0
T8	383644	12	0	0
T9	11905	12	0	0
T10	5354	0	0	0
T11	199037	9	0	0
T12	52218	94	0	0
T13	42278	78	0	0
T14	0	63	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	236309	0	0
T1	8690	89	0	0
T2	8967	137	0	0
T3	795001	46	0	0
T7	618004	1592	0	0
T8	383644	12	0	0
T9	11905	12	0	0
T10	5354	0	0	0
T11	199037	9	0	0
T12	52218	94	0	0
T13	42278	78	0	0
T14	0	63	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	596723	0	0
T1	8690	92	0	0
T2	8967	140	0	0
T3	795001	52	0	0
T7	618004	3043	0	0
T8	383644	12	0	0
T9	11905	12	0	0
T10	5354	0	0	0
T11	199037	13	0	0
T12	52218	111	0	0
T13	42278	81	0	0
T14	0	65	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	236309	0	0
T1	8690	89	0	0
T2	8967	137	0	0
T3	795001	46	0	0
T7	618004	1592	0	0
T8	383644	12	0	0
T9	11905	12	0	0
T10	5354	0	0	0
T11	199037	9	0	0
T12	52218	94	0	0
T13	42278	78	0	0
T14	0	63	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	232908	0	0
GntImpliesValid_A	413400564	232908	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	232908	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	3029731	0	0
ReadyAndValidImplyGrant_A	413400564	232908	0	0
ReqAndReadyImplyGrant_A	413400564	232908	0	0
ReqImpliesValid_A	413400564	611873	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	232908	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232908	0	0
T1	8690	63	0	0
T2	8967	134	0	0
T3	795001	60	0	0
T7	618004	2116	0	0
T8	383644	10	0	0
T9	11905	14	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	102	0	0
T13	42278	72	0	0
T14	0	47	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232908	0	0
T1	8690	63	0	0
T2	8967	134	0	0
T3	795001	60	0	0
T7	618004	2116	0	0
T8	383644	10	0	0
T9	11905	14	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	102	0	0
T13	42278	72	0	0
T14	0	47	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232908	0	0
T1	8690	63	0	0
T2	8967	134	0	0
T3	795001	60	0	0
T7	618004	2116	0	0
T8	383644	10	0	0
T9	11905	14	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	102	0	0
T13	42278	72	0	0
T14	0	47	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	3029731	0	0
T1	8690	64	0	0
T2	8967	124	0	0
T3	795001	256	0	0
T7	618004	9931	0	0
T8	383644	3026	0	0
T9	11905	107	0	0
T10	5354	1	0	0
T11	199037	42	0	0
T12	52218	785	0	0
T13	42278	538	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232908	0	0
T1	8690	63	0	0
T2	8967	134	0	0
T3	795001	60	0	0
T7	618004	2116	0	0
T8	383644	10	0	0
T9	11905	14	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	102	0	0
T13	42278	72	0	0
T14	0	47	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232908	0	0
T1	8690	63	0	0
T2	8967	134	0	0
T3	795001	60	0	0
T7	618004	2116	0	0
T8	383644	10	0	0
T9	11905	14	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	102	0	0
T13	42278	72	0	0
T14	0	47	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	611873	0	0
T1	8690	63	0	0
T2	8967	145	0	0
T3	795001	75	0	0
T7	618004	11481	0	0
T8	383644	10	0	0
T9	11905	23	0	0
T10	5354	0	0	0
T11	199037	19	0	0
T12	52218	116	0	0
T13	42278	77	0	0
T14	0	48	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232908	0	0
T1	8690	63	0	0
T2	8967	134	0	0
T3	795001	60	0	0
T7	618004	2116	0	0
T8	383644	10	0	0
T9	11905	14	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	102	0	0
T13	42278	72	0	0
T14	0	47	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	241794	0	0
GntImpliesValid_A	413400564	241794	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	241794	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	3061569	0	0
ReadyAndValidImplyGrant_A	413400564	241794	0	0
ReqAndReadyImplyGrant_A	413400564	241794	0	0
ReqImpliesValid_A	413400564	599498	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	241794	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	241794	0	0
T1	8690	67	0	0
T2	8967	145	0	0
T3	795001	58	0	0
T7	618004	1138	0	0
T8	383644	26	0	0
T9	11905	5	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	99	0	0
T13	42278	72	0	0
T14	0	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	241794	0	0
T1	8690	67	0	0
T2	8967	145	0	0
T3	795001	58	0	0
T7	618004	1138	0	0
T8	383644	26	0	0
T9	11905	5	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	99	0	0
T13	42278	72	0	0
T14	0	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	241794	0	0
T1	8690	67	0	0
T2	8967	145	0	0
T3	795001	58	0	0
T7	618004	1138	0	0
T8	383644	26	0	0
T9	11905	5	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	99	0	0
T13	42278	72	0	0
T14	0	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	3061569	0	0
T1	8690	66	0	0
T2	8967	137	0	0
T3	795001	279	0	0
T7	618004	8378	0	0
T8	383644	8020	0	0
T9	11905	48	0	0
T10	5354	1	0	0
T11	199037	56	0	0
T12	52218	829	0	0
T13	42278	504	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	241794	0	0
T1	8690	67	0	0
T2	8967	145	0	0
T3	795001	58	0	0
T7	618004	1138	0	0
T8	383644	26	0	0
T9	11905	5	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	99	0	0
T13	42278	72	0	0
T14	0	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	241794	0	0
T1	8690	67	0	0
T2	8967	145	0	0
T3	795001	58	0	0
T7	618004	1138	0	0
T8	383644	26	0	0
T9	11905	5	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	99	0	0
T13	42278	72	0	0
T14	0	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	599498	0	0
T1	8690	69	0	0
T2	8967	154	0	0
T3	795001	69	0	0
T7	618004	1339	0	0
T8	383644	198	0	0
T9	11905	5	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	158	0	0
T13	42278	73	0	0
T14	0	66	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	241794	0	0
T1	8690	67	0	0
T2	8967	145	0	0
T3	795001	58	0	0
T7	618004	1138	0	0
T8	383644	26	0	0
T9	11905	5	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	99	0	0
T13	42278	72	0	0
T14	0	64	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	229656	0	0
GntImpliesValid_A	413400564	229656	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	229656	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	3048601	0	0
ReadyAndValidImplyGrant_A	413400564	229656	0	0
ReqAndReadyImplyGrant_A	413400564	229656	0	0
ReqImpliesValid_A	413400564	543347	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	229656	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	229656	0	0
T1	8690	77	0	0
T2	8967	154	0	0
T3	795001	67	0	0
T7	618004	4005	0	0
T8	383644	5	0	0
T9	11905	8	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	93	0	0
T13	42278	97	0	0
T14	0	43	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	229656	0	0
T1	8690	77	0	0
T2	8967	154	0	0
T3	795001	67	0	0
T7	618004	4005	0	0
T8	383644	5	0	0
T9	11905	8	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	93	0	0
T13	42278	97	0	0
T14	0	43	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	229656	0	0
T1	8690	77	0	0
T2	8967	154	0	0
T3	795001	67	0	0
T7	618004	4005	0	0
T8	383644	5	0	0
T9	11905	8	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	93	0	0
T13	42278	97	0	0
T14	0	43	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	3048601	0	0
T1	8690	76	0	0
T2	8967	147	0	0
T3	795001	263	0	0
T7	618004	21624	0	0
T8	383644	2069	0	0
T9	11905	75	0	0
T10	5354	1	0	0
T11	199037	72	0	0
T12	52218	801	0	0
T13	42278	669	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	229656	0	0
T1	8690	77	0	0
T2	8967	154	0	0
T3	795001	67	0	0
T7	618004	4005	0	0
T8	383644	5	0	0
T9	11905	8	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	93	0	0
T13	42278	97	0	0
T14	0	43	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	229656	0	0
T1	8690	77	0	0
T2	8967	154	0	0
T3	795001	67	0	0
T7	618004	4005	0	0
T8	383644	5	0	0
T9	11905	8	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	93	0	0
T13	42278	97	0	0
T14	0	43	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	543347	0	0
T1	8690	79	0	0
T2	8967	162	0	0
T3	795001	86	0	0
T7	618004	17573	0	0
T8	383644	5	0	0
T9	11905	8	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	100	0	0
T13	42278	134	0	0
T14	0	46	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	229656	0	0
T1	8690	77	0	0
T2	8967	154	0	0
T3	795001	67	0	0
T7	618004	4005	0	0
T8	383644	5	0	0
T9	11905	8	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	93	0	0
T13	42278	97	0	0
T14	0	43	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	232382	0	0
GntImpliesValid_A	413400564	232382	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	232382	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	3101462	0	0
ReadyAndValidImplyGrant_A	413400564	232382	0	0
ReqAndReadyImplyGrant_A	413400564	232382	0	0
ReqImpliesValid_A	413400564	613098	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	232382	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232382	0	0
T1	8690	75	0	0
T2	8967	149	0	0
T3	795001	67	0	0
T7	618004	1505	0	0
T8	383644	14	0	0
T9	11905	16	0	0
T10	5354	434	0	0
T11	199037	10	0	0
T12	52218	109	0	0
T13	42278	77	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232382	0	0
T1	8690	75	0	0
T2	8967	149	0	0
T3	795001	67	0	0
T7	618004	1505	0	0
T8	383644	14	0	0
T9	11905	16	0	0
T10	5354	434	0	0
T11	199037	10	0	0
T12	52218	109	0	0
T13	42278	77	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232382	0	0
T1	8690	75	0	0
T2	8967	149	0	0
T3	795001	67	0	0
T7	618004	1505	0	0
T8	383644	14	0	0
T9	11905	16	0	0
T10	5354	434	0	0
T11	199037	10	0	0
T12	52218	109	0	0
T13	42278	77	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	3101462	0	0
T1	8690	74	0	0
T2	8967	141	0	0
T3	795001	269	0	0
T7	618004	10478	0	0
T8	383644	4896	0	0
T9	11905	103	0	0
T10	5354	34	0	0
T11	199037	40	0	0
T12	52218	840	0	0
T13	42278	572	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232382	0	0
T1	8690	75	0	0
T2	8967	149	0	0
T3	795001	67	0	0
T7	618004	1505	0	0
T8	383644	14	0	0
T9	11905	16	0	0
T10	5354	434	0	0
T11	199037	10	0	0
T12	52218	109	0	0
T13	42278	77	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232382	0	0
T1	8690	75	0	0
T2	8967	149	0	0
T3	795001	67	0	0
T7	618004	1505	0	0
T8	383644	14	0	0
T9	11905	16	0	0
T10	5354	434	0	0
T11	199037	10	0	0
T12	52218	109	0	0
T13	42278	77	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	613098	0	0
T1	8690	77	0	0
T2	8967	158	0	0
T3	795001	84	0	0
T7	618004	3041	0	0
T8	383644	14	0	0
T9	11905	18	0	0
T10	5354	835	0	0
T11	199037	10	0	0
T12	52218	117	0	0
T13	42278	84	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	232382	0	0
T1	8690	75	0	0
T2	8967	149	0	0
T3	795001	67	0	0
T7	618004	1505	0	0
T8	383644	14	0	0
T9	11905	16	0	0
T10	5354	434	0	0
T11	199037	10	0	0
T12	52218	109	0	0
T13	42278	77	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	221933	0	0
GntImpliesValid_A	413400564	221933	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	221933	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	2965070	0	0
ReadyAndValidImplyGrant_A	413400564	221933	0	0
ReqAndReadyImplyGrant_A	413400564	221933	0	0
ReqImpliesValid_A	413400564	511809	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	221933	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	221933	0	0
T1	8690	67	0	0
T2	8967	140	0	0
T3	795001	61	0	0
T7	618004	1087	0	0
T8	383644	14	0	0
T9	11905	11	0	0
T10	5354	0	0	0
T11	199037	11	0	0
T12	52218	96	0	0
T13	42278	91	0	0
T14	0	53	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	221933	0	0
T1	8690	67	0	0
T2	8967	140	0	0
T3	795001	61	0	0
T7	618004	1087	0	0
T8	383644	14	0	0
T9	11905	11	0	0
T10	5354	0	0	0
T11	199037	11	0	0
T12	52218	96	0	0
T13	42278	91	0	0
T14	0	53	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	221933	0	0
T1	8690	67	0	0
T2	8967	140	0	0
T3	795001	61	0	0
T7	618004	1087	0	0
T8	383644	14	0	0
T9	11905	11	0	0
T10	5354	0	0	0
T11	199037	11	0	0
T12	52218	96	0	0
T13	42278	91	0	0
T14	0	53	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	2965070	0	0
T1	8690	67	0	0
T2	8967	135	0	0
T3	795001	255	0	0
T7	618004	8546	0	0
T8	383644	3675	0	0
T9	11905	67	0	0
T10	5354	1	0	0
T11	199037	28	0	0
T12	52218	781	0	0
T13	42278	699	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	221933	0	0
T1	8690	67	0	0
T2	8967	140	0	0
T3	795001	61	0	0
T7	618004	1087	0	0
T8	383644	14	0	0
T9	11905	11	0	0
T10	5354	0	0	0
T11	199037	11	0	0
T12	52218	96	0	0
T13	42278	91	0	0
T14	0	53	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	221933	0	0
T1	8690	67	0	0
T2	8967	140	0	0
T3	795001	61	0	0
T7	618004	1087	0	0
T8	383644	14	0	0
T9	11905	11	0	0
T10	5354	0	0	0
T11	199037	11	0	0
T12	52218	96	0	0
T13	42278	91	0	0
T14	0	53	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	511809	0	0
T1	8690	68	0	0
T2	8967	146	0	0
T3	795001	72	0	0
T7	618004	1356	0	0
T8	383644	702	0	0
T9	11905	14	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	124	0	0
T13	42278	91	0	0
T14	0	56	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	221933	0	0
T1	8690	67	0	0
T2	8967	140	0	0
T3	795001	61	0	0
T7	618004	1087	0	0
T8	383644	14	0	0
T9	11905	11	0	0
T10	5354	0	0	0
T11	199037	11	0	0
T12	52218	96	0	0
T13	42278	91	0	0
T14	0	53	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	241542	0	0
GntImpliesValid_A	413400564	241542	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	241542	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	3092892	0	0
ReadyAndValidImplyGrant_A	413400564	241542	0	0
ReqAndReadyImplyGrant_A	413400564	241542	0	0
ReqImpliesValid_A	413400564	590989	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	241542	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	241542	0	0
T1	8690	137	0	0
T2	8967	124	0	0
T3	795001	59	0	0
T7	618004	1552	0	0
T8	383644	9	0	0
T9	11905	9	0	0
T10	5354	0	0	0
T11	199037	8	0	0
T12	52218	141	0	0
T13	42278	140	0	0
T14	0	98	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	241542	0	0
T1	8690	137	0	0
T2	8967	124	0	0
T3	795001	59	0	0
T7	618004	1552	0	0
T8	383644	9	0	0
T9	11905	9	0	0
T10	5354	0	0	0
T11	199037	8	0	0
T12	52218	141	0	0
T13	42278	140	0	0
T14	0	98	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	241542	0	0
T1	8690	137	0	0
T2	8967	124	0	0
T3	795001	59	0	0
T7	618004	1552	0	0
T8	383644	9	0	0
T9	11905	9	0	0
T10	5354	0	0	0
T11	199037	8	0	0
T12	52218	141	0	0
T13	42278	140	0	0
T14	0	98	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	3092892	0	0
T1	8690	135	0	0
T2	8967	119	0	0
T3	795001	225	0	0
T7	618004	9522	0	0
T8	383644	4615	0	0
T9	11905	74	0	0
T10	5354	1	0	0
T11	199037	43	0	0
T12	52218	1041	0	0
T13	42278	1146	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	241542	0	0
T1	8690	137	0	0
T2	8967	124	0	0
T3	795001	59	0	0
T7	618004	1552	0	0
T8	383644	9	0	0
T9	11905	9	0	0
T10	5354	0	0	0
T11	199037	8	0	0
T12	52218	141	0	0
T13	42278	140	0	0
T14	0	98	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	241542	0	0
T1	8690	137	0	0
T2	8967	124	0	0
T3	795001	59	0	0
T7	618004	1552	0	0
T8	383644	9	0	0
T9	11905	9	0	0
T10	5354	0	0	0
T11	199037	8	0	0
T12	52218	141	0	0
T13	42278	140	0	0
T14	0	98	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	590989	0	0
T1	8690	140	0	0
T2	8967	130	0	0
T3	795001	82	0	0
T7	618004	5112	0	0
T8	383644	9	0	0
T9	11905	9	0	0
T10	5354	0	0	0
T11	199037	8	0	0
T12	52218	159	0	0
T13	42278	187	0	0
T14	0	108	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	241542	0	0
T1	8690	137	0	0
T2	8967	124	0	0
T3	795001	59	0	0
T7	618004	1552	0	0
T8	383644	9	0	0
T9	11905	9	0	0
T10	5354	0	0	0
T11	199037	8	0	0
T12	52218	141	0	0
T13	42278	140	0	0
T14	0	98	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	230699	0	0
GntImpliesValid_A	413400564	230699	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	230699	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	3044712	0	0
ReadyAndValidImplyGrant_A	413400564	230699	0	0
ReqAndReadyImplyGrant_A	413400564	230699	0	0
ReqImpliesValid_A	413400564	562297	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	230699	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	230699	0	0
T1	8690	74	0	0
T2	8967	147	0	0
T3	795001	71	0	0
T7	618004	1029	0	0
T8	383644	8	0	0
T9	11905	16	0	0
T10	5354	526	0	0
T11	199037	11	0	0
T12	52218	102	0	0
T13	42278	59	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	230699	0	0
T1	8690	74	0	0
T2	8967	147	0	0
T3	795001	71	0	0
T7	618004	1029	0	0
T8	383644	8	0	0
T9	11905	16	0	0
T10	5354	526	0	0
T11	199037	11	0	0
T12	52218	102	0	0
T13	42278	59	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	230699	0	0
T1	8690	74	0	0
T2	8967	147	0	0
T3	795001	71	0	0
T7	618004	1029	0	0
T8	383644	8	0	0
T9	11905	16	0	0
T10	5354	526	0	0
T11	199037	11	0	0
T12	52218	102	0	0
T13	42278	59	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	3044712	0	0
T1	8690	72	0	0
T2	8967	141	0	0
T3	795001	283	0	0
T7	618004	7908	0	0
T8	383644	2318	0	0
T9	11905	90	0	0
T10	5354	2	0	0
T11	199037	61	0	0
T12	52218	721	0	0
T13	42278	451	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	230699	0	0
T1	8690	74	0	0
T2	8967	147	0	0
T3	795001	71	0	0
T7	618004	1029	0	0
T8	383644	8	0	0
T9	11905	16	0	0
T10	5354	526	0	0
T11	199037	11	0	0
T12	52218	102	0	0
T13	42278	59	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	230699	0	0
T1	8690	74	0	0
T2	8967	147	0	0
T3	795001	71	0	0
T7	618004	1029	0	0
T8	383644	8	0	0
T9	11905	16	0	0
T10	5354	526	0	0
T11	199037	11	0	0
T12	52218	102	0	0
T13	42278	59	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	562297	0	0
T1	8690	77	0	0
T2	8967	154	0	0
T3	795001	78	0	0
T7	618004	1195	0	0
T8	383644	337	0	0
T9	11905	16	0	0
T10	5354	1051	0	0
T11	199037	11	0	0
T12	52218	149	0	0
T13	42278	71	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	230699	0	0
T1	8690	74	0	0
T2	8967	147	0	0
T3	795001	71	0	0
T7	618004	1029	0	0
T8	383644	8	0	0
T9	11905	16	0	0
T10	5354	526	0	0
T11	199037	11	0	0
T12	52218	102	0	0
T13	42278	59	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	223029	0	0
GntImpliesValid_A	413400564	223029	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	223029	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	3036430	0	0
ReadyAndValidImplyGrant_A	413400564	223029	0	0
ReqAndReadyImplyGrant_A	413400564	223029	0	0
ReqImpliesValid_A	413400564	567948	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	223029	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	223029	0	0
T1	8690	74	0	0
T2	8967	130	0	0
T3	795001	65	0	0
T7	618004	1954	0	0
T8	383644	13	0	0
T9	11905	16	0	0
T10	5354	0	0	0
T11	199037	10	0	0
T12	52218	78	0	0
T13	42278	98	0	0
T14	0	57	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	223029	0	0
T1	8690	74	0	0
T2	8967	130	0	0
T3	795001	65	0	0
T7	618004	1954	0	0
T8	383644	13	0	0
T9	11905	16	0	0
T10	5354	0	0	0
T11	199037	10	0	0
T12	52218	78	0	0
T13	42278	98	0	0
T14	0	57	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	223029	0	0
T1	8690	74	0	0
T2	8967	130	0	0
T3	795001	65	0	0
T7	618004	1954	0	0
T8	383644	13	0	0
T9	11905	16	0	0
T10	5354	0	0	0
T11	199037	10	0	0
T12	52218	78	0	0
T13	42278	98	0	0
T14	0	57	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	3036430	0	0
T1	8690	74	0	0
T2	8967	123	0	0
T3	795001	320	0	0
T7	618004	13931	0	0
T8	383644	6154	0	0
T9	11905	124	0	0
T10	5354	1	0	0
T11	199037	44	0	0
T12	52218	558	0	0
T13	42278	717	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	223029	0	0
T1	8690	74	0	0
T2	8967	130	0	0
T3	795001	65	0	0
T7	618004	1954	0	0
T8	383644	13	0	0
T9	11905	16	0	0
T10	5354	0	0	0
T11	199037	10	0	0
T12	52218	78	0	0
T13	42278	98	0	0
T14	0	57	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	223029	0	0
T1	8690	74	0	0
T2	8967	130	0	0
T3	795001	65	0	0
T7	618004	1954	0	0
T8	383644	13	0	0
T9	11905	16	0	0
T10	5354	0	0	0
T11	199037	10	0	0
T12	52218	78	0	0
T13	42278	98	0	0
T14	0	57	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	567948	0	0
T1	8690	75	0	0
T2	8967	138	0	0
T3	795001	69	0	0
T7	618004	4284	0	0
T8	383644	13	0	0
T9	11905	35	0	0
T10	5354	0	0	0
T11	199037	13	0	0
T12	52218	91	0	0
T13	42278	143	0	0
T14	0	59	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	223029	0	0
T1	8690	74	0	0
T2	8967	130	0	0
T3	795001	65	0	0
T7	618004	1954	0	0
T8	383644	13	0	0
T9	11905	16	0	0
T10	5354	0	0	0
T11	199037	10	0	0
T12	52218	78	0	0
T13	42278	98	0	0
T14	0	57	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	222429	0	0
GntImpliesValid_A	413400564	222429	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	222429	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	2997662	0	0
ReadyAndValidImplyGrant_A	413400564	222429	0	0
ReqAndReadyImplyGrant_A	413400564	222429	0	0
ReqImpliesValid_A	413400564	549822	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	222429	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	222429	0	0
T1	8690	99	0	0
T2	8967	157	0	0
T3	795001	64	0	0
T7	618004	1606	0	0
T8	383644	12	0	0
T9	11905	19	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	89	0	0
T13	42278	67	0	0
T14	0	50	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	222429	0	0
T1	8690	99	0	0
T2	8967	157	0	0
T3	795001	64	0	0
T7	618004	1606	0	0
T8	383644	12	0	0
T9	11905	19	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	89	0	0
T13	42278	67	0	0
T14	0	50	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	222429	0	0
T1	8690	99	0	0
T2	8967	157	0	0
T3	795001	64	0	0
T7	618004	1606	0	0
T8	383644	12	0	0
T9	11905	19	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	89	0	0
T13	42278	67	0	0
T14	0	50	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	2997662	0	0
T1	8690	93	0	0
T2	8967	146	0	0
T3	795001	259	0	0
T7	618004	10966	0	0
T8	383644	2175	0	0
T9	11905	164	0	0
T10	5354	1	0	0
T11	199037	59	0	0
T12	52218	693	0	0
T13	42278	570	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	222429	0	0
T1	8690	99	0	0
T2	8967	157	0	0
T3	795001	64	0	0
T7	618004	1606	0	0
T8	383644	12	0	0
T9	11905	19	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	89	0	0
T13	42278	67	0	0
T14	0	50	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	222429	0	0
T1	8690	99	0	0
T2	8967	157	0	0
T3	795001	64	0	0
T7	618004	1606	0	0
T8	383644	12	0	0
T9	11905	19	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	89	0	0
T13	42278	67	0	0
T14	0	50	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	549822	0	0
T1	8690	106	0	0
T2	8967	169	0	0
T3	795001	89	0	0
T7	618004	3904	0	0
T8	383644	317	0	0
T9	11905	29	0	0
T10	5354	0	0	0
T11	199037	13	0	0
T12	52218	112	0	0
T13	42278	67	0	0
T14	0	53	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	222429	0	0
T1	8690	99	0	0
T2	8967	157	0	0
T3	795001	64	0	0
T7	618004	1606	0	0
T8	383644	12	0	0
T9	11905	19	0	0
T10	5354	0	0	0
T11	199037	12	0	0
T12	52218	89	0	0
T13	42278	67	0	0
T14	0	50	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	239545	0	0
GntImpliesValid_A	413400564	239545	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	239545	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	3033043	0	0
ReadyAndValidImplyGrant_A	413400564	239545	0	0
ReqAndReadyImplyGrant_A	413400564	239545	0	0
ReqImpliesValid_A	413400564	630321	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	239545	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	239545	0	0
T1	8690	70	0	0
T2	8967	128	0	0
T3	795001	57	0	0
T7	618004	1178	0	0
T8	383644	10	0	0
T9	11905	14	0	0
T10	5354	0	0	0
T11	199037	17	0	0
T12	52218	84	0	0
T13	42278	80	0	0
T14	0	63	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	239545	0	0
T1	8690	70	0	0
T2	8967	128	0	0
T3	795001	57	0	0
T7	618004	1178	0	0
T8	383644	10	0	0
T9	11905	14	0	0
T10	5354	0	0	0
T11	199037	17	0	0
T12	52218	84	0	0
T13	42278	80	0	0
T14	0	63	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	239545	0	0
T1	8690	70	0	0
T2	8967	128	0	0
T3	795001	57	0	0
T7	618004	1178	0	0
T8	383644	10	0	0
T9	11905	14	0	0
T10	5354	0	0	0
T11	199037	17	0	0
T12	52218	84	0	0
T13	42278	80	0	0
T14	0	63	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	3033043	0	0
T1	8690	66	0	0
T2	8967	120	0	0
T3	795001	260	0	0
T7	618004	8829	0	0
T8	383644	3346	0	0
T9	11905	110	0	0
T10	5354	1	0	0
T11	199037	54	0	0
T12	52218	636	0	0
T13	42278	538	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	239545	0	0
T1	8690	70	0	0
T2	8967	128	0	0
T3	795001	57	0	0
T7	618004	1178	0	0
T8	383644	10	0	0
T9	11905	14	0	0
T10	5354	0	0	0
T11	199037	17	0	0
T12	52218	84	0	0
T13	42278	80	0	0
T14	0	63	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	239545	0	0
T1	8690	70	0	0
T2	8967	128	0	0
T3	795001	57	0	0
T7	618004	1178	0	0
T8	383644	10	0	0
T9	11905	14	0	0
T10	5354	0	0	0
T11	199037	17	0	0
T12	52218	84	0	0
T13	42278	80	0	0
T14	0	63	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	630321	0	0
T1	8690	75	0	0
T2	8967	137	0	0
T3	795001	62	0	0
T7	618004	1561	0	0
T8	383644	338	0	0
T9	11905	30	0	0
T10	5354	0	0	0
T11	199037	17	0	0
T12	52218	104	0	0
T13	42278	113	0	0
T14	0	67	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	239545	0	0
T1	8690	70	0	0
T2	8967	128	0	0
T3	795001	57	0	0
T7	618004	1178	0	0
T8	383644	10	0	0
T9	11905	14	0	0
T10	5354	0	0	0
T11	199037	17	0	0
T12	52218	84	0	0
T13	42278	80	0	0
T14	0	63	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	222915	0	0
GntImpliesValid_A	413400564	222915	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	222915	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	3002069	0	0
ReadyAndValidImplyGrant_A	413400564	222915	0	0
ReqAndReadyImplyGrant_A	413400564	222915	0	0
ReqImpliesValid_A	413400564	546507	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	0	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	222915	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	222915	0	0
T1	8690	71	0	0
T2	8967	142	0	0
T3	795001	58	0	0
T7	618004	1584	0	0
T8	383644	13	0	0
T9	11905	11	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	80	0	0
T13	42278	76	0	0
T14	0	37	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	222915	0	0
T1	8690	71	0	0
T2	8967	142	0	0
T3	795001	58	0	0
T7	618004	1584	0	0
T8	383644	13	0	0
T9	11905	11	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	80	0	0
T13	42278	76	0	0
T14	0	37	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	222915	0	0
T1	8690	71	0	0
T2	8967	142	0	0
T3	795001	58	0	0
T7	618004	1584	0	0
T8	383644	13	0	0
T9	11905	11	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	80	0	0
T13	42278	76	0	0
T14	0	37	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	3002069	0	0
T1	8690	68	0	0
T2	8967	129	0	0
T3	795001	267	0	0
T7	618004	10882	0	0
T8	383644	5120	0	0
T9	11905	86	0	0
T10	5354	1	0	0
T11	199037	57	0	0
T12	52218	605	0	0
T13	42278	650	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	222915	0	0
T1	8690	71	0	0
T2	8967	142	0	0
T3	795001	58	0	0
T7	618004	1584	0	0
T8	383644	13	0	0
T9	11905	11	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	80	0	0
T13	42278	76	0	0
T14	0	37	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	222915	0	0
T1	8690	71	0	0
T2	8967	142	0	0
T3	795001	58	0	0
T7	618004	1584	0	0
T8	383644	13	0	0
T9	11905	11	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	80	0	0
T13	42278	76	0	0
T14	0	37	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	546507	0	0
T1	8690	75	0	0
T2	8967	156	0	0
T3	795001	58	0	0
T7	618004	3593	0	0
T8	383644	13	0	0
T9	11905	23	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	113	0	0
T13	42278	90	0	0
T14	0	37	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	222915	0	0
T1	8690	71	0	0
T2	8967	142	0	0
T3	795001	58	0	0
T7	618004	1584	0	0
T8	383644	13	0	0
T9	11905	11	0	0
T10	5354	0	0	0
T11	199037	14	0	0
T12	52218	80	0	0
T13	42278	76	0	0
T14	0	37	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	922401	0	0
GntImpliesValid_A	413400564	922401	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	922401	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	11589267	0	0
ReadyAndValidImplyGrant_A	413400564	922401	0	0
ReqAndReadyImplyGrant_A	413400564	922401	0	0
ReqImpliesValid_A	413400564	2353894	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	20265	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	922401	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	922401	0	0
T1	8690	340	0	0
T2	8967	650	0	0
T3	795001	216	0	0
T7	618004	8275	0	0
T8	383644	50	0	0
T9	11905	50	0	0
T10	5354	321	0	0
T11	199037	54	0	0
T12	52218	360	0	0
T13	42278	307	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	922401	0	0
T1	8690	340	0	0
T2	8967	650	0	0
T3	795001	216	0	0
T7	618004	8275	0	0
T8	383644	50	0	0
T9	11905	50	0	0
T10	5354	321	0	0
T11	199037	54	0	0
T12	52218	360	0	0
T13	42278	307	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	922401	0	0
T1	8690	340	0	0
T2	8967	650	0	0
T3	795001	216	0	0
T7	618004	8275	0	0
T8	383644	50	0	0
T9	11905	50	0	0
T10	5354	321	0	0
T11	199037	54	0	0
T12	52218	360	0	0
T13	42278	307	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	11589267	0	0
T1	8690	1	0	0
T2	8967	1	0	0
T3	795001	678	0	0
T7	618004	44170	0	0
T8	383644	14260	0	0
T9	11905	341	0	0
T10	5354	1	0	0
T11	199037	145	0	0
T12	52218	2341	0	0
T13	42278	1850	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	922401	0	0
T1	8690	340	0	0
T2	8967	650	0	0
T3	795001	216	0	0
T7	618004	8275	0	0
T8	383644	50	0	0
T9	11905	50	0	0
T10	5354	321	0	0
T11	199037	54	0	0
T12	52218	360	0	0
T13	42278	307	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	922401	0	0
T1	8690	340	0	0
T2	8967	650	0	0
T3	795001	216	0	0
T7	618004	8275	0	0
T8	383644	50	0	0
T9	11905	50	0	0
T10	5354	321	0	0
T11	199037	54	0	0
T12	52218	360	0	0
T13	42278	307	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	2353894	0	0
T1	8690	340	0	0
T2	8967	650	0	0
T3	795001	285	0	0
T7	618004	28329	0	0
T8	383644	1089	0	0
T9	11905	58	0	0
T10	5354	321	0	0
T11	199037	68	0	0
T12	52218	508	0	0
T13	42278	412	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	20265	0	900
T1	8690	5	0	1
T2	8967	15	0	1
T3	795001	0	0	1
T7	618004	31	0	1
T8	383644	0	0	1
T9	11905	0	0	1
T10	5354	0	0	1
T11	199037	0	0	1
T12	52218	0	0	1
T13	42278	0	0	1
T14	0	5	0	0
T16	0	7	0	0
T18	0	1	0	0
T19	0	2	0	0
T20	0	7	0	0
T21	0	2	0	0
T22	0	12	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	922401	0	0
T1	8690	340	0	0
T2	8967	650	0	0
T3	795001	216	0	0
T7	618004	8275	0	0
T8	383644	50	0	0
T9	11905	50	0	0
T10	5354	321	0	0
T11	199037	54	0	0
T12	52218	360	0	0
T13	42278	307	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413400564	413274519	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	413400564	934503	0	0
GntImpliesValid_A	413400564	934503	0	0
GrantKnown_A	413400564	413274519	0	0
IdxKnown_A	413400564	413274519	0	0
IndexIsCorrect_A	413400564	934503	0	0
LockArbDecision_A	413400564	0	0	0
NoReadyValidNoGrant_A	413400564	346311483	0	0
ReadyAndValidImplyGrant_A	413400564	934503	0	0
ReqAndReadyImplyGrant_A	413400564	934503	0	0
ReqImpliesValid_A	413400564	13592389	0	0
ReqStaysHighUntilGranted0_M	413400564	0	0	0
RoundRobin_A	413400564	30299	0	900
ValidKnown_A	413400564	413274519	0	0
gen_data_port_assertion.DataFlow_A	413400564	934503	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	934503	0	0
T1	8690	300	0	0
T2	8967	581	0	0
T3	795001	222	0	0
T7	618004	6826	0	0
T8	383644	41	0	0
T9	11905	36	0	0
T10	5354	310	0	0
T11	199037	38	0	0
T12	52218	348	0	0
T13	42278	307	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	934503	0	0
T1	8690	300	0	0
T2	8967	581	0	0
T3	795001	222	0	0
T7	618004	6826	0	0
T8	383644	41	0	0
T9	11905	36	0	0
T10	5354	310	0	0
T11	199037	38	0	0
T12	52218	348	0	0
T13	42278	307	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	934503	0	0
T1	8690	300	0	0
T2	8967	581	0	0
T3	795001	222	0	0
T7	618004	6826	0	0
T8	383644	41	0	0
T9	11905	36	0	0
T10	5354	310	0	0
T11	199037	38	0	0
T12	52218	348	0	0
T13	42278	307	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	346311483	0	0
T1	8690	1	0	0
T2	8967	1	0	0
T3	795001	661727	0	0
T7	618004	511345	0	0
T8	383644	359979	0	0
T9	11905	10477	0	0
T10	5354	1	0	0
T11	199037	165661	0	0
T12	52218	44997	0	0
T13	42278	35525	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	934503	0	0
T1	8690	300	0	0
T2	8967	581	0	0
T3	795001	222	0	0
T7	618004	6826	0	0
T8	383644	41	0	0
T9	11905	36	0	0
T10	5354	310	0	0
T11	199037	38	0	0
T12	52218	348	0	0
T13	42278	307	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	934503	0	0
T1	8690	300	0	0
T2	8967	581	0	0
T3	795001	222	0	0
T7	618004	6826	0	0
T8	383644	41	0	0
T9	11905	36	0	0
T10	5354	310	0	0
T11	199037	38	0	0
T12	52218	348	0	0
T13	42278	307	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	13592389	0	0
T1	8690	300	0	0
T2	8967	581	0	0
T3	795001	952	0	0
T7	618004	56030	0	0
T8	383644	15862	0	0
T9	11905	329	0	0
T10	5354	310	0	0
T11	199037	149	0	0
T12	52218	2786	0	0
T13	42278	2157	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	30299	0	900
T1	8690	1	0	1
T2	8967	12	0	1
T3	795001	0	0	1
T7	618004	16	0	1
T8	383644	0	0	1
T9	11905	0	0	1
T10	5354	0	0	1
T11	199037	0	0	1
T12	52218	0	0	1
T13	42278	0	0	1
T14	0	3	0	0
T15	0	2	0	0
T16	0	14	0	0
T17	0	1	0	0
T19	0	4	0	0
T20	0	9	0	0
T21	0	5	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	413274519	0	0
T1	8690	8622	0	0
T2	8967	8898	0	0
T3	795001	794932	0	0
T7	618004	616688	0	0
T8	383644	383627	0	0
T9	11905	11880	0	0
T10	5354	5299	0	0
T11	199037	199031	0	0
T12	52218	52145	0	0
T13	42278	42205	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413400564	934503	0	0
T1	8690	300	0	0
T2	8967	581	0	0
T3	795001	222	0	0
T7	618004	6826	0	0
T8	383644	41	0	0
T9	11905	36	0	0
T10	5354	310	0	0
T11	199037	38	0	0
T12	52218	348	0	0
T13	42278	307	0	0