Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1537985 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 244852 1 T1 237 T2 384 T3 22


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 605850 1 T1 625 T2 933 T3 37
values[0x0] 573704 1 T1 583 T2 892 T3 40
values[0x1] 603283 1 T1 598 T2 945 T3 40


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1189192 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 593645 1 T1 581 T2 975 T3 46


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27726 1 T1 15 T2 39 T7 20
valid_sources[0x01] 27109 1 T1 27 T2 51 T7 23
valid_sources[0x02] 27850 1 T1 42 T2 51 T3 3
valid_sources[0x03] 28537 1 T1 41 T2 45 T6 1
valid_sources[0x04] 28478 1 T1 25 T2 39 T6 4
valid_sources[0x05] 27336 1 T1 37 T2 40 T7 19
valid_sources[0x06] 27706 1 T1 21 T2 32 T3 5
valid_sources[0x07] 27640 1 T1 20 T2 42 T3 2
valid_sources[0x08] 28105 1 T1 18 T2 36 T6 3
valid_sources[0x09] 28151 1 T1 22 T2 40 T6 1
valid_sources[0x0a] 27687 1 T1 14 T2 40 T3 4
valid_sources[0x0b] 27575 1 T1 28 T2 47 T6 1
valid_sources[0x0c] 28175 1 T1 24 T2 45 T7 17
valid_sources[0x0d] 27516 1 T1 23 T2 54 T7 14
valid_sources[0x0e] 28699 1 T1 28 T2 52 T7 19
valid_sources[0x0f] 27740 1 T1 24 T2 43 T7 32
valid_sources[0x10] 28461 1 T1 28 T2 45 T6 1
valid_sources[0x11] 27249 1 T1 15 T2 36 T3 5
valid_sources[0x12] 27783 1 T1 35 T2 41 T7 25
valid_sources[0x13] 28389 1 T1 41 T2 49 T7 16
valid_sources[0x14] 27776 1 T1 14 T2 47 T7 26
valid_sources[0x15] 28189 1 T1 15 T2 44 T3 5
valid_sources[0x16] 28083 1 T1 29 T2 36 T6 1
valid_sources[0x17] 27601 1 T1 34 T2 58 T6 1
valid_sources[0x18] 28532 1 T1 52 T2 36 T6 1
valid_sources[0x19] 27176 1 T1 51 T2 49 T6 2
valid_sources[0x1a] 29642 1 T1 23 T2 45 T6 2
valid_sources[0x1b] 27805 1 T1 27 T2 51 T6 1
valid_sources[0x1c] 28633 1 T1 23 T2 44 T7 19
valid_sources[0x1d] 27162 1 T1 28 T2 38 T7 27
valid_sources[0x1e] 27729 1 T1 25 T2 49 T6 1
valid_sources[0x1f] 27174 1 T1 37 T2 33 T7 17
valid_sources[0x20] 26468 1 T1 29 T2 36 T3 8


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25982 1 T1 29 T2 32 T3 1
values[0x0] all_enables biggest_size 193174 1 T1 192 T2 300 T3 17
values[0x1] all_enables biggest_size 25696 1 T1 16 T2 52 T3 4


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1552083 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 251473 1 T1 285 T2 384 T3 26


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 618629 1 T1 673 T2 867 T3 57
values[0x0] 567509 1 T1 607 T2 860 T3 55
values[0x1] 617418 1 T1 675 T2 890 T3 55


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1191011 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 612545 1 T1 676 T2 881 T3 55


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28607 1 T1 22 T2 74 T6 1
valid_sources[0x01] 27199 1 T1 1 T2 75 T3 2
valid_sources[0x02] 28117 1 T2 20 T3 3 T7 1
valid_sources[0x03] 27695 1 T2 53 T6 1 T7 75
valid_sources[0x04] 28300 1 T1 84 T2 26 T3 2
valid_sources[0x05] 29004 1 T2 50 T3 1 T8 1
valid_sources[0x06] 27376 1 T1 15 T2 17 T3 2
valid_sources[0x07] 27811 1 T1 17 T2 29 T6 2
valid_sources[0x08] 28221 1 T1 1 T2 27 T3 1
valid_sources[0x09] 28284 1 T1 46 T2 5 T3 1
valid_sources[0x0a] 28376 1 T1 12 T2 32 T3 2
valid_sources[0x0b] 27570 1 T1 52 T2 58 T8 1
valid_sources[0x0c] 28994 1 T1 5 T2 96 T7 34
valid_sources[0x0d] 27750 1 T1 41 T2 42 T3 2
valid_sources[0x0e] 29396 1 T1 1 T2 18 T3 8
valid_sources[0x0f] 28547 1 T1 40 T2 25 T3 3
valid_sources[0x10] 28063 1 T2 25 T3 1 T6 2
valid_sources[0x11] 27793 1 T2 56 T3 3 T7 10
valid_sources[0x12] 28647 1 T1 127 T2 94 T3 3
valid_sources[0x13] 28925 1 T1 21 T2 51 T7 45
valid_sources[0x14] 28387 1 T2 71 T3 9 T6 3
valid_sources[0x15] 27466 1 T2 30 T3 2 T9 1
valid_sources[0x16] 28131 1 T1 16 T2 72 T3 3
valid_sources[0x17] 28163 1 T1 88 T2 14 T3 5
valid_sources[0x18] 27785 1 T1 9 T2 124 T3 6
valid_sources[0x19] 28333 1 T1 104 T2 70 T3 3
valid_sources[0x1a] 28694 1 T1 4 T2 12 T3 4
valid_sources[0x1b] 28150 1 T1 13 T2 48 T3 5
valid_sources[0x1c] 27852 1 T1 37 T2 70 T3 2
valid_sources[0x1d] 27839 1 T1 33 T2 57 T3 1
valid_sources[0x1e] 28299 1 T2 70 T3 2 T6 2
valid_sources[0x1f] 27502 1 T1 22 T2 16 T3 5
valid_sources[0x20] 28833 1 T1 63 T2 28 T3 6


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26433 1 T1 28 T2 34 T3 3
values[0x0] all_enables biggest_size 198459 1 T1 228 T2 313 T3 22
values[0x1] all_enables biggest_size 26581 1 T1 29 T2 37 T3 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1556681 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 246985 1 T1 222 T2 379 T3 18


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 612237 1 T1 575 T2 856 T3 34
values[0x0] 578955 1 T1 513 T2 861 T3 37
values[0x1] 612474 1 T1 657 T2 888 T3 51


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1203108 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 600558 1 T1 602 T2 905 T3 43


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28707 1 T1 10 T2 35 T3 5
valid_sources[0x01] 27920 1 T1 33 T2 55 T3 2
valid_sources[0x02] 27732 1 T1 17 T2 32 T3 7
valid_sources[0x03] 28752 1 T1 21 T2 27 T3 1
valid_sources[0x04] 28218 1 T1 40 T2 47 T3 2
valid_sources[0x05] 28317 1 T1 29 T2 30 T3 3
valid_sources[0x06] 29580 1 T1 14 T2 50 T7 22
valid_sources[0x07] 27879 1 T1 27 T2 36 T3 3
valid_sources[0x08] 29184 1 T1 12 T2 33 T3 1
valid_sources[0x09] 28120 1 T1 19 T2 40 T3 2
valid_sources[0x0a] 28088 1 T1 49 T2 56 T3 3
valid_sources[0x0b] 27247 1 T1 24 T2 37 T3 1
valid_sources[0x0c] 28260 1 T1 39 T2 58 T3 1
valid_sources[0x0d] 28291 1 T1 26 T2 61 T3 1
valid_sources[0x0e] 28910 1 T1 13 T2 37 T6 2
valid_sources[0x0f] 28512 1 T1 35 T2 46 T3 1
valid_sources[0x10] 27765 1 T1 38 T2 48 T3 3
valid_sources[0x11] 28701 1 T1 17 T2 53 T3 3
valid_sources[0x12] 27922 1 T1 25 T2 54 T3 2
valid_sources[0x13] 28904 1 T1 34 T2 31 T7 13
valid_sources[0x14] 28308 1 T1 19 T2 29 T3 5
valid_sources[0x15] 28352 1 T1 34 T2 42 T3 1
valid_sources[0x16] 28776 1 T1 30 T2 33 T3 4
valid_sources[0x17] 27740 1 T1 31 T2 31 T3 1
valid_sources[0x18] 29794 1 T1 41 T2 38 T3 1
valid_sources[0x19] 27650 1 T1 16 T2 24 T3 3
valid_sources[0x1a] 28528 1 T1 31 T2 27 T3 1
valid_sources[0x1b] 29375 1 T1 20 T2 28 T3 2
valid_sources[0x1c] 28330 1 T1 26 T2 43 T3 7
valid_sources[0x1d] 28843 1 T1 56 T2 26 T7 20
valid_sources[0x1e] 27483 1 T1 16 T2 66 T3 1
valid_sources[0x1f] 28190 1 T1 34 T2 41 T3 1
valid_sources[0x20] 28139 1 T1 71 T2 39 T6 1


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26028 1 T1 17 T2 38 T3 4
values[0x0] all_enables biggest_size 194898 1 T1 169 T2 300 T3 13
values[0x1] all_enables biggest_size 26059 1 T1 36 T2 41 T3 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%