Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7952289	0	0
GntImpliesValid_A	2147483647	7952289	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7952289	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	464371901	0	0
ReadyAndValidImplyGrant_A	2147483647	7952289	0	0
ReqAndReadyImplyGrant_A	2147483647	7952289	0	0
ReqImpliesValid_A	2147483647	35662047	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	44770	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7952289	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1118160	1116480	0	0
T2	7555848	7555656	0	0
T3	26640	25344	0	0
T6	725568	725112	0	0
T7	665088	663768	0	0
T8	9930504	9929856	0	0
T9	1183344	1182792	0	0
T10	176088	175080	0	0
T11	291240	290400	0	0
T12	5221248	5221128	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7952289	0	0
T1	1118160	2743	0	0
T2	7555848	7990	0	0
T3	26640	405	0	0
T6	725568	3037	0	0
T7	665088	1883	0	0
T8	9930504	394	0	0
T9	1183344	5183	0	0
T10	176088	2372	0	0
T11	291240	7145	0	0
T12	5221248	5020	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7952289	0	0
T1	1118160	2743	0	0
T2	7555848	7990	0	0
T3	26640	405	0	0
T6	725568	3037	0	0
T7	665088	1883	0	0
T8	9930504	394	0	0
T9	1183344	5183	0	0
T10	176088	2372	0	0
T11	291240	7145	0	0
T12	5221248	5020	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1118160	1116480	0	0
T2	7555848	7555656	0	0
T3	26640	25344	0	0
T6	725568	725112	0	0
T7	665088	663768	0	0
T8	9930504	9929856	0	0
T9	1183344	1182792	0	0
T10	176088	175080	0	0
T11	291240	290400	0	0
T12	5221248	5221128	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1118160	1116480	0	0
T2	7555848	7555656	0	0
T3	26640	25344	0	0
T6	725568	725112	0	0
T7	665088	663768	0	0
T8	9930504	9929856	0	0
T9	1183344	1182792	0	0
T10	176088	175080	0	0
T11	291240	290400	0	0
T12	5221248	5221128	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7952289	0	0
T1	1118160	2743	0	0
T2	7555848	7990	0	0
T3	26640	405	0	0
T6	725568	3037	0	0
T7	665088	1883	0	0
T8	9930504	394	0	0
T9	1183344	5183	0	0
T10	176088	2372	0	0
T11	291240	7145	0	0
T12	5221248	5020	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	464371901	0	0
T1	1118160	61261	0	0
T2	7555848	2847274	0	0
T3	26640	477	0	0
T6	725568	46200	0	0
T7	665088	39832	0	0
T8	9930504	519476	0	0
T9	1183344	77485	0	0
T10	176088	4164	0	0
T11	291240	8308	0	0
T12	5221248	1861069	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7952289	0	0
T1	1118160	2743	0	0
T2	7555848	7990	0	0
T3	26640	405	0	0
T6	725568	3037	0	0
T7	665088	1883	0	0
T8	9930504	394	0	0
T9	1183344	5183	0	0
T10	176088	2372	0	0
T11	291240	7145	0	0
T12	5221248	5020	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7952289	0	0
T1	1118160	2743	0	0
T2	7555848	7990	0	0
T3	26640	405	0	0
T6	725568	3037	0	0
T7	665088	1883	0	0
T8	9930504	394	0	0
T9	1183344	5183	0	0
T10	176088	2372	0	0
T11	291240	7145	0	0
T12	5221248	5020	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35662047	0	0
T1	1118160	5830	0	0
T2	7555848	513301	0	0
T3	26640	493	0	0
T6	725568	6548	0	0
T7	665088	4271	0	0
T8	9930504	22378	0	0
T9	1183344	11898	0	0
T10	176088	2947	0	0
T11	291240	8346	0	0
T12	5221248	320364	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	44770	0	21600
T1	93180	2	0	2
T2	629654	0	0	2
T3	2220	0	0	2
T6	60464	2	0	2
T7	55424	0	0	2
T8	827542	0	0	2
T9	98612	0	0	2
T10	14674	5	0	2
T11	24270	27	0	2
T12	435104	1	0	2
T13	0	9	0	0
T14	0	29	0	0
T15	0	378	0	0
T16	0	2732	0	0
T17	0	1	0	0
T18	0	59	0	0
T19	0	1	0	0
T20	0	2	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1118160	1116480	0	0
T2	7555848	7555656	0	0
T3	26640	25344	0	0
T6	725568	725112	0	0
T7	665088	663768	0	0
T8	9930504	9929856	0	0
T9	1183344	1182792	0	0
T10	176088	175080	0	0
T11	291240	290400	0	0
T12	5221248	5221128	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7952289	0	0
T1	1118160	2743	0	0
T2	7555848	7990	0	0
T3	26640	405	0	0
T6	725568	3037	0	0
T7	665088	1883	0	0
T8	9930504	394	0	0
T9	1183344	5183	0	0
T10	176088	2372	0	0
T11	291240	7145	0	0
T12	5221248	5020	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	888158	0	0
GntImpliesValid_A	424903152	888158	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	888158	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	12608745	0	0
ReadyAndValidImplyGrant_A	424903152	888158	0	0
ReqAndReadyImplyGrant_A	424903152	888158	0	0
ReqImpliesValid_A	424903152	2598663	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	888158	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	888158	0	0
T1	46590	312	0	0
T2	314827	875	0	0
T3	1110	56	0	0
T6	30232	310	0	0
T7	27712	192	0	0
T8	413771	43	0	0
T9	49306	596	0	0
T10	7337	250	0	0
T11	12135	792	0	0
T12	217552	576	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	888158	0	0
T1	46590	312	0	0
T2	314827	875	0	0
T3	1110	56	0	0
T6	30232	310	0	0
T7	27712	192	0	0
T8	413771	43	0	0
T9	49306	596	0	0
T10	7337	250	0	0
T11	12135	792	0	0
T12	217552	576	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	888158	0	0
T1	46590	312	0	0
T2	314827	875	0	0
T3	1110	56	0	0
T6	30232	310	0	0
T7	27712	192	0	0
T8	413771	43	0	0
T9	49306	596	0	0
T10	7337	250	0	0
T11	12135	792	0	0
T12	217552	576	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	12608745	0	0
T1	46590	2361	0	0
T2	314827	282758	0	0
T3	1110	32	0	0
T6	30232	1989	0	0
T7	27712	1405	0	0
T8	413771	13590	0	0
T9	49306	4227	0	0
T10	7337	219	0	0
T11	12135	580	0	0
T12	217552	194701	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	888158	0	0
T1	46590	312	0	0
T2	314827	875	0	0
T3	1110	56	0	0
T6	30232	310	0	0
T7	27712	192	0	0
T8	413771	43	0	0
T9	49306	596	0	0
T10	7337	250	0	0
T11	12135	792	0	0
T12	217552	576	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	888158	0	0
T1	46590	312	0	0
T2	314827	875	0	0
T3	1110	56	0	0
T6	30232	310	0	0
T7	27712	192	0	0
T8	413771	43	0	0
T9	49306	596	0	0
T10	7337	250	0	0
T11	12135	792	0	0
T12	217552	576	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	2598663	0	0
T1	46590	448	0	0
T2	314827	29853	0	0
T3	1110	81	0	0
T6	30232	454	0	0
T7	27712	388	0	0
T8	413771	1895	0	0
T9	49306	1285	0	0
T10	7337	282	0	0
T11	12135	1005	0	0
T12	217552	17534	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	888158	0	0
T1	46590	312	0	0
T2	314827	875	0	0
T3	1110	56	0	0
T6	30232	310	0	0
T7	27712	192	0	0
T8	413771	43	0	0
T9	49306	596	0	0
T10	7337	250	0	0
T11	12135	792	0	0
T12	217552	576	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	877787	0	0
GntImpliesValid_A	424903152	877787	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	877787	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	12592436	0	0
ReadyAndValidImplyGrant_A	424903152	877787	0	0
ReqAndReadyImplyGrant_A	424903152	877787	0	0
ReqImpliesValid_A	424903152	2513665	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	877787	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	877787	0	0
T1	46590	288	0	0
T2	314827	881	0	0
T3	1110	46	0	0
T6	30232	324	0	0
T7	27712	189	0	0
T8	413771	51	0	0
T9	49306	588	0	0
T10	7337	272	0	0
T11	12135	785	0	0
T12	217552	582	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	877787	0	0
T1	46590	288	0	0
T2	314827	881	0	0
T3	1110	46	0	0
T6	30232	324	0	0
T7	27712	189	0	0
T8	413771	51	0	0
T9	49306	588	0	0
T10	7337	272	0	0
T11	12135	785	0	0
T12	217552	582	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	877787	0	0
T1	46590	288	0	0
T2	314827	881	0	0
T3	1110	46	0	0
T6	30232	324	0	0
T7	27712	189	0	0
T8	413771	51	0	0
T9	49306	588	0	0
T10	7337	272	0	0
T11	12135	785	0	0
T12	217552	582	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	12592436	0	0
T1	46590	2140	0	0
T2	314827	291690	0	0
T3	1110	32	0	0
T6	30232	2493	0	0
T7	27712	1401	0	0
T8	413771	17532	0	0
T9	49306	4196	0	0
T10	7337	236	0	0
T11	12135	569	0	0
T12	217552	191116	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	877787	0	0
T1	46590	288	0	0
T2	314827	881	0	0
T3	1110	46	0	0
T6	30232	324	0	0
T7	27712	189	0	0
T8	413771	51	0	0
T9	49306	588	0	0
T10	7337	272	0	0
T11	12135	785	0	0
T12	217552	582	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	877787	0	0
T1	46590	288	0	0
T2	314827	881	0	0
T3	1110	46	0	0
T6	30232	324	0	0
T7	27712	189	0	0
T8	413771	51	0	0
T9	49306	588	0	0
T10	7337	272	0	0
T11	12135	785	0	0
T12	217552	582	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	2513665	0	0
T1	46590	391	0	0
T2	314827	32146	0	0
T3	1110	61	0	0
T6	30232	597	0	0
T7	27712	269	0	0
T8	413771	1545	0	0
T9	49306	939	0	0
T10	7337	309	0	0
T11	12135	1002	0	0
T12	217552	24785	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	877787	0	0
T1	46590	288	0	0
T2	314827	881	0	0
T3	1110	46	0	0
T6	30232	324	0	0
T7	27712	189	0	0
T8	413771	51	0	0
T9	49306	588	0	0
T10	7337	272	0	0
T11	12135	785	0	0
T12	217552	582	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	237511	0	0
GntImpliesValid_A	424903152	237511	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	237511	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	3151322	0	0
ReadyAndValidImplyGrant_A	424903152	237511	0	0
ReqAndReadyImplyGrant_A	424903152	237511	0	0
ReqImpliesValid_A	424903152	669065	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	237511	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	237511	0	0
T1	46590	80	0	0
T2	314827	210	0	0
T3	1110	15	0	0
T6	30232	75	0	0
T7	27712	46	0	0
T8	413771	14	0	0
T9	49306	134	0	0
T10	7337	63	0	0
T11	12135	186	0	0
T12	217552	143	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	237511	0	0
T1	46590	80	0	0
T2	314827	210	0	0
T3	1110	15	0	0
T6	30232	75	0	0
T7	27712	46	0	0
T8	413771	14	0	0
T9	49306	134	0	0
T10	7337	63	0	0
T11	12135	186	0	0
T12	217552	143	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	237511	0	0
T1	46590	80	0	0
T2	314827	210	0	0
T3	1110	15	0	0
T6	30232	75	0	0
T7	27712	46	0	0
T8	413771	14	0	0
T9	49306	134	0	0
T10	7337	63	0	0
T11	12135	186	0	0
T12	217552	143	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	3151322	0	0
T1	46590	680	0	0
T2	314827	65881	0	0
T3	1110	15	0	0
T6	30232	494	0	0
T7	27712	338	0	0
T8	413771	3564	0	0
T9	49306	992	0	0
T10	7337	62	0	0
T11	12135	175	0	0
T12	217552	46045	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	237511	0	0
T1	46590	80	0	0
T2	314827	210	0	0
T3	1110	15	0	0
T6	30232	75	0	0
T7	27712	46	0	0
T8	413771	14	0	0
T9	49306	134	0	0
T10	7337	63	0	0
T11	12135	186	0	0
T12	217552	143	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	237511	0	0
T1	46590	80	0	0
T2	314827	210	0	0
T3	1110	15	0	0
T6	30232	75	0	0
T7	27712	46	0	0
T8	413771	14	0	0
T9	49306	134	0	0
T10	7337	63	0	0
T11	12135	186	0	0
T12	217552	143	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	669065	0	0
T1	46590	86	0	0
T2	314827	3066	0	0
T3	1110	16	0	0
T6	30232	101	0	0
T7	27712	70	0	0
T8	413771	14	0	0
T9	49306	165	0	0
T10	7337	65	0	0
T11	12135	198	0	0
T12	217552	3113	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	237511	0	0
T1	46590	80	0	0
T2	314827	210	0	0
T3	1110	15	0	0
T6	30232	75	0	0
T7	27712	46	0	0
T8	413771	14	0	0
T9	49306	134	0	0
T10	7337	63	0	0
T11	12135	186	0	0
T12	217552	143	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	230374	0	0
GntImpliesValid_A	424903152	230374	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	230374	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	3123728	0	0
ReadyAndValidImplyGrant_A	424903152	230374	0	0
ReqAndReadyImplyGrant_A	424903152	230374	0	0
ReqImpliesValid_A	424903152	647469	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	230374	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	230374	0	0
T1	46590	73	0	0
T2	314827	208	0	0
T3	1110	7	0	0
T6	30232	86	0	0
T7	27712	50	0	0
T8	413771	14	0	0
T9	49306	121	0	0
T10	7337	62	0	0
T11	12135	189	0	0
T12	217552	140	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	230374	0	0
T1	46590	73	0	0
T2	314827	208	0	0
T3	1110	7	0	0
T6	30232	86	0	0
T7	27712	50	0	0
T8	413771	14	0	0
T9	49306	121	0	0
T10	7337	62	0	0
T11	12135	189	0	0
T12	217552	140	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	230374	0	0
T1	46590	73	0	0
T2	314827	208	0	0
T3	1110	7	0	0
T6	30232	86	0	0
T7	27712	50	0	0
T8	413771	14	0	0
T9	49306	121	0	0
T10	7337	62	0	0
T11	12135	189	0	0
T12	217552	140	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	3123728	0	0
T1	46590	537	0	0
T2	314827	67665	0	0
T3	1110	8	0	0
T6	30232	590	0	0
T7	27712	431	0	0
T8	413771	3449	0	0
T9	49306	858	0	0
T10	7337	60	0	0
T11	12135	180	0	0
T12	217552	49380	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	230374	0	0
T1	46590	73	0	0
T2	314827	208	0	0
T3	1110	7	0	0
T6	30232	86	0	0
T7	27712	50	0	0
T8	413771	14	0	0
T9	49306	121	0	0
T10	7337	62	0	0
T11	12135	189	0	0
T12	217552	140	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	230374	0	0
T1	46590	73	0	0
T2	314827	208	0	0
T3	1110	7	0	0
T6	30232	86	0	0
T7	27712	50	0	0
T8	413771	14	0	0
T9	49306	121	0	0
T10	7337	62	0	0
T11	12135	189	0	0
T12	217552	140	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	647469	0	0
T1	46590	74	0	0
T2	314827	4009	0	0
T3	1110	7	0	0
T6	30232	122	0	0
T7	27712	60	0	0
T8	413771	14	0	0
T9	49306	169	0	0
T10	7337	65	0	0
T11	12135	199	0	0
T12	217552	3182	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	230374	0	0
T1	46590	73	0	0
T2	314827	208	0	0
T3	1110	7	0	0
T6	30232	86	0	0
T7	27712	50	0	0
T8	413771	14	0	0
T9	49306	121	0	0
T10	7337	62	0	0
T11	12135	189	0	0
T12	217552	140	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	212550	0	0
GntImpliesValid_A	424903152	212550	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	212550	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	5313020	0	0
ReadyAndValidImplyGrant_A	424903152	212550	0	0
ReqAndReadyImplyGrant_A	424903152	212550	0	0
ReqImpliesValid_A	424903152	1125107	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	212550	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	212550	0	0
T1	46590	88	0	0
T2	314827	237	0	0
T3	1110	9	0	0
T6	30232	84	0	0
T7	27712	57	0	0
T8	413771	10	0	0
T9	49306	150	0	0
T10	7337	60	0	0
T11	12135	205	0	0
T12	217552	150	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	212550	0	0
T1	46590	88	0	0
T2	314827	237	0	0
T3	1110	9	0	0
T6	30232	84	0	0
T7	27712	57	0	0
T8	413771	10	0	0
T9	49306	150	0	0
T10	7337	60	0	0
T11	12135	205	0	0
T12	217552	150	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	212550	0	0
T1	46590	88	0	0
T2	314827	237	0	0
T3	1110	9	0	0
T6	30232	84	0	0
T7	27712	57	0	0
T8	413771	10	0	0
T9	49306	150	0	0
T10	7337	60	0	0
T11	12135	205	0	0
T12	217552	150	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	5313020	0	0
T1	46590	1175	0	0
T2	314827	110962	0	0
T3	1110	41	0	0
T6	30232	639	0	0
T7	27712	815	0	0
T8	413771	1784	0	0
T9	49306	1018	0	0
T10	7337	874	0	0
T11	12135	882	0	0
T12	217552	59739	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	212550	0	0
T1	46590	88	0	0
T2	314827	237	0	0
T3	1110	9	0	0
T6	30232	84	0	0
T7	27712	57	0	0
T8	413771	10	0	0
T9	49306	150	0	0
T10	7337	60	0	0
T11	12135	205	0	0
T12	217552	150	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	212550	0	0
T1	46590	88	0	0
T2	314827	237	0	0
T3	1110	9	0	0
T6	30232	84	0	0
T7	27712	57	0	0
T8	413771	10	0	0
T9	49306	150	0	0
T10	7337	60	0	0
T11	12135	205	0	0
T12	217552	150	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	1125107	0	0
T1	46590	102	0	0
T2	314827	9910	0	0
T3	1110	20	0	0
T6	30232	99	0	0
T7	27712	122	0	0
T8	413771	112	0	0
T9	49306	225	0	0
T10	7337	315	0	0
T11	12135	347	0	0
T12	217552	2337	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	212550	0	0
T1	46590	88	0	0
T2	314827	237	0	0
T3	1110	9	0	0
T6	30232	84	0	0
T7	27712	57	0	0
T8	413771	10	0	0
T9	49306	150	0	0
T10	7337	60	0	0
T11	12135	205	0	0
T12	217552	150	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	209765	0	0
GntImpliesValid_A	424903152	209765	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	209765	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	5307417	0	0
ReadyAndValidImplyGrant_A	424903152	209765	0	0
ReqAndReadyImplyGrant_A	424903152	209765	0	0
ReqImpliesValid_A	424903152	1209205	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	209765	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	209765	0	0
T1	46590	72	0	0
T2	314827	210	0	0
T3	1110	7	0	0
T6	30232	82	0	0
T7	27712	53	0	0
T8	413771	9	0	0
T9	49306	138	0	0
T10	7337	61	0	0
T11	12135	179	0	0
T12	217552	135	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	209765	0	0
T1	46590	72	0	0
T2	314827	210	0	0
T3	1110	7	0	0
T6	30232	82	0	0
T7	27712	53	0	0
T8	413771	9	0	0
T9	49306	138	0	0
T10	7337	61	0	0
T11	12135	179	0	0
T12	217552	135	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	209765	0	0
T1	46590	72	0	0
T2	314827	210	0	0
T3	1110	7	0	0
T6	30232	82	0	0
T7	27712	53	0	0
T8	413771	9	0	0
T9	49306	138	0	0
T10	7337	61	0	0
T11	12135	179	0	0
T12	217552	135	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	5307417	0	0
T1	46590	918	0	0
T2	314827	80738	0	0
T3	1110	65	0	0
T6	30232	1215	0	0
T7	27712	2769	0	0
T8	413771	4906	0	0
T9	49306	1145	0	0
T10	7337	645	0	0
T11	12135	911	0	0
T12	217552	73562	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	209765	0	0
T1	46590	72	0	0
T2	314827	210	0	0
T3	1110	7	0	0
T6	30232	82	0	0
T7	27712	53	0	0
T8	413771	9	0	0
T9	49306	138	0	0
T10	7337	61	0	0
T11	12135	179	0	0
T12	217552	135	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	209765	0	0
T1	46590	72	0	0
T2	314827	210	0	0
T3	1110	7	0	0
T6	30232	82	0	0
T7	27712	53	0	0
T8	413771	9	0	0
T9	49306	138	0	0
T10	7337	61	0	0
T11	12135	179	0	0
T12	217552	135	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	1209205	0	0
T1	46590	103	0	0
T2	314827	2105	0	0
T3	1110	16	0	0
T6	30232	189	0	0
T7	27712	339	0	0
T8	413771	529	0	0
T9	49306	234	0	0
T10	7337	123	0	0
T11	12135	245	0	0
T12	217552	4863	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	209765	0	0
T1	46590	72	0	0
T2	314827	210	0	0
T3	1110	7	0	0
T6	30232	82	0	0
T7	27712	53	0	0
T8	413771	9	0	0
T9	49306	138	0	0
T10	7337	61	0	0
T11	12135	179	0	0
T12	217552	135	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	216910	0	0
GntImpliesValid_A	424903152	216910	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	216910	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	4918594	0	0
ReadyAndValidImplyGrant_A	424903152	216910	0	0
ReqAndReadyImplyGrant_A	424903152	216910	0	0
ReqImpliesValid_A	424903152	1131978	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	216910	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	216910	0	0
T1	46590	71	0	0
T2	314827	230	0	0
T3	1110	12	0	0
T6	30232	92	0	0
T7	27712	64	0	0
T8	413771	8	0	0
T9	49306	151	0	0
T10	7337	67	0	0
T11	12135	190	0	0
T12	217552	147	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	216910	0	0
T1	46590	71	0	0
T2	314827	230	0	0
T3	1110	12	0	0
T6	30232	92	0	0
T7	27712	64	0	0
T8	413771	8	0	0
T9	49306	151	0	0
T10	7337	67	0	0
T11	12135	190	0	0
T12	217552	147	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	216910	0	0
T1	46590	71	0	0
T2	314827	230	0	0
T3	1110	12	0	0
T6	30232	92	0	0
T7	27712	64	0	0
T8	413771	8	0	0
T9	49306	151	0	0
T10	7337	67	0	0
T11	12135	190	0	0
T12	217552	147	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	4918594	0	0
T1	46590	2368	0	0
T2	314827	260764	0	0
T3	1110	88	0	0
T6	30232	725	0	0
T7	27712	894	0	0
T8	413771	4273	0	0
T9	49306	4465	0	0
T10	7337	548	0	0
T11	12135	843	0	0
T12	217552	132059	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	216910	0	0
T1	46590	71	0	0
T2	314827	230	0	0
T3	1110	12	0	0
T6	30232	92	0	0
T7	27712	64	0	0
T8	413771	8	0	0
T9	49306	151	0	0
T10	7337	67	0	0
T11	12135	190	0	0
T12	217552	147	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	216910	0	0
T1	46590	71	0	0
T2	314827	230	0	0
T3	1110	12	0	0
T6	30232	92	0	0
T7	27712	64	0	0
T8	413771	8	0	0
T9	49306	151	0	0
T10	7337	67	0	0
T11	12135	190	0	0
T12	217552	147	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	1131978	0	0
T1	46590	265	0	0
T2	314827	21636	0	0
T3	1110	18	0	0
T6	30232	172	0	0
T7	27712	87	0	0
T8	413771	8	0	0
T9	49306	549	0	0
T10	7337	140	0	0
T11	12135	324	0	0
T12	217552	10806	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	216910	0	0
T1	46590	71	0	0
T2	314827	230	0	0
T3	1110	12	0	0
T6	30232	92	0	0
T7	27712	64	0	0
T8	413771	8	0	0
T9	49306	151	0	0
T10	7337	67	0	0
T11	12135	190	0	0
T12	217552	147	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	215866	0	0
GntImpliesValid_A	424903152	215866	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	215866	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	5028332	0	0
ReadyAndValidImplyGrant_A	424903152	215866	0	0
ReqAndReadyImplyGrant_A	424903152	215866	0	0
ReqImpliesValid_A	424903152	1226267	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	215866	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	215866	0	0
T1	46590	75	0	0
T2	314827	234	0	0
T3	1110	8	0	0
T6	30232	83	0	0
T7	27712	53	0	0
T8	413771	13	0	0
T9	49306	139	0	0
T10	7337	71	0	0
T11	12135	202	0	0
T12	217552	127	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	215866	0	0
T1	46590	75	0	0
T2	314827	234	0	0
T3	1110	8	0	0
T6	30232	83	0	0
T7	27712	53	0	0
T8	413771	13	0	0
T9	49306	139	0	0
T10	7337	71	0	0
T11	12135	202	0	0
T12	217552	127	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	215866	0	0
T1	46590	75	0	0
T2	314827	234	0	0
T3	1110	8	0	0
T6	30232	83	0	0
T7	27712	53	0	0
T8	413771	13	0	0
T9	49306	139	0	0
T10	7337	71	0	0
T11	12135	202	0	0
T12	217552	127	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	5028332	0	0
T1	46590	1810	0	0
T2	314827	99387	0	0
T3	1110	50	0	0
T6	30232	979	0	0
T7	27712	1115	0	0
T8	413771	4991	0	0
T9	49306	1853	0	0
T10	7337	622	0	0
T11	12135	1447	0	0
T12	217552	133445	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	215866	0	0
T1	46590	75	0	0
T2	314827	234	0	0
T3	1110	8	0	0
T6	30232	83	0	0
T7	27712	53	0	0
T8	413771	13	0	0
T9	49306	139	0	0
T10	7337	71	0	0
T11	12135	202	0	0
T12	217552	127	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	215866	0	0
T1	46590	75	0	0
T2	314827	234	0	0
T3	1110	8	0	0
T6	30232	83	0	0
T7	27712	53	0	0
T8	413771	13	0	0
T9	49306	139	0	0
T10	7337	71	0	0
T11	12135	202	0	0
T12	217552	127	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	1226267	0	0
T1	46590	200	0	0
T2	314827	7593	0	0
T3	1110	16	0	0
T6	30232	155	0	0
T7	27712	58	0	0
T8	413771	581	0	0
T9	49306	216	0	0
T10	7337	143	0	0
T11	12135	444	0	0
T12	217552	10138	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	215866	0	0
T1	46590	75	0	0
T2	314827	234	0	0
T3	1110	8	0	0
T6	30232	83	0	0
T7	27712	53	0	0
T8	413771	13	0	0
T9	49306	139	0	0
T10	7337	71	0	0
T11	12135	202	0	0
T12	217552	127	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	212734	0	0
GntImpliesValid_A	424903152	212734	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	212734	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	3079540	0	0
ReadyAndValidImplyGrant_A	424903152	212734	0	0
ReqAndReadyImplyGrant_A	424903152	212734	0	0
ReqImpliesValid_A	424903152	584643	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	212734	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	212734	0	0
T1	46590	57	0	0
T2	314827	247	0	0
T3	1110	11	0	0
T6	30232	84	0	0
T7	27712	61	0	0
T8	413771	10	0	0
T9	49306	151	0	0
T10	7337	63	0	0
T11	12135	198	0	0
T12	217552	114	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	212734	0	0
T1	46590	57	0	0
T2	314827	247	0	0
T3	1110	11	0	0
T6	30232	84	0	0
T7	27712	61	0	0
T8	413771	10	0	0
T9	49306	151	0	0
T10	7337	63	0	0
T11	12135	198	0	0
T12	217552	114	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	212734	0	0
T1	46590	57	0	0
T2	314827	247	0	0
T3	1110	11	0	0
T6	30232	84	0	0
T7	27712	61	0	0
T8	413771	10	0	0
T9	49306	151	0	0
T10	7337	63	0	0
T11	12135	198	0	0
T12	217552	114	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	3079540	0	0
T1	46590	463	0	0
T2	314827	76674	0	0
T3	1110	11	0	0
T6	30232	680	0	0
T7	27712	492	0	0
T8	413771	3451	0	0
T9	49306	987	0	0
T10	7337	62	0	0
T11	12135	188	0	0
T12	217552	38555	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	212734	0	0
T1	46590	57	0	0
T2	314827	247	0	0
T3	1110	11	0	0
T6	30232	84	0	0
T7	27712	61	0	0
T8	413771	10	0	0
T9	49306	151	0	0
T10	7337	63	0	0
T11	12135	198	0	0
T12	217552	114	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	212734	0	0
T1	46590	57	0	0
T2	314827	247	0	0
T3	1110	11	0	0
T6	30232	84	0	0
T7	27712	61	0	0
T8	413771	10	0	0
T9	49306	151	0	0
T10	7337	63	0	0
T11	12135	198	0	0
T12	217552	114	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	584643	0	0
T1	46590	71	0	0
T2	314827	5516	0	0
T3	1110	12	0	0
T6	30232	115	0	0
T7	27712	95	0	0
T8	413771	10	0	0
T9	49306	241	0	0
T10	7337	65	0	0
T11	12135	209	0	0
T12	217552	720	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	212734	0	0
T1	46590	57	0	0
T2	314827	247	0	0
T3	1110	11	0	0
T6	30232	84	0	0
T7	27712	61	0	0
T8	413771	10	0	0
T9	49306	151	0	0
T10	7337	63	0	0
T11	12135	198	0	0
T12	217552	114	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	231769	0	0
GntImpliesValid_A	424903152	231769	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	231769	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	3046710	0	0
ReadyAndValidImplyGrant_A	424903152	231769	0	0
ReqAndReadyImplyGrant_A	424903152	231769	0	0
ReqImpliesValid_A	424903152	646991	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	231769	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	231769	0	0
T1	46590	83	0	0
T2	314827	210	0	0
T3	1110	15	0	0
T6	30232	94	0	0
T7	27712	32	0	0
T8	413771	9	0	0
T9	49306	127	0	0
T10	7337	66	0	0
T11	12135	212	0	0
T12	217552	130	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	231769	0	0
T1	46590	83	0	0
T2	314827	210	0	0
T3	1110	15	0	0
T6	30232	94	0	0
T7	27712	32	0	0
T8	413771	9	0	0
T9	49306	127	0	0
T10	7337	66	0	0
T11	12135	212	0	0
T12	217552	130	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	231769	0	0
T1	46590	83	0	0
T2	314827	210	0	0
T3	1110	15	0	0
T6	30232	94	0	0
T7	27712	32	0	0
T8	413771	9	0	0
T9	49306	127	0	0
T10	7337	66	0	0
T11	12135	212	0	0
T12	217552	130	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	3046710	0	0
T1	46590	614	0	0
T2	314827	65398	0	0
T3	1110	14	0	0
T6	30232	554	0	0
T7	27712	260	0	0
T8	413771	2406	0	0
T9	49306	850	0	0
T10	7337	58	0	0
T11	12135	204	0	0
T12	217552	44343	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	231769	0	0
T1	46590	83	0	0
T2	314827	210	0	0
T3	1110	15	0	0
T6	30232	94	0	0
T7	27712	32	0	0
T8	413771	9	0	0
T9	49306	127	0	0
T10	7337	66	0	0
T11	12135	212	0	0
T12	217552	130	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	231769	0	0
T1	46590	83	0	0
T2	314827	210	0	0
T3	1110	15	0	0
T6	30232	94	0	0
T7	27712	32	0	0
T8	413771	9	0	0
T9	49306	127	0	0
T10	7337	66	0	0
T11	12135	212	0	0
T12	217552	130	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	646991	0	0
T1	46590	103	0	0
T2	314827	2971	0	0
T3	1110	17	0	0
T6	30232	155	0	0
T7	27712	36	0	0
T8	413771	11	0	0
T9	49306	176	0	0
T10	7337	75	0	0
T11	12135	221	0	0
T12	217552	2827	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	231769	0	0
T1	46590	83	0	0
T2	314827	210	0	0
T3	1110	15	0	0
T6	30232	94	0	0
T7	27712	32	0	0
T8	413771	9	0	0
T9	49306	127	0	0
T10	7337	66	0	0
T11	12135	212	0	0
T12	217552	130	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	214826	0	0
GntImpliesValid_A	424903152	214826	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	214826	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	3125360	0	0
ReadyAndValidImplyGrant_A	424903152	214826	0	0
ReqAndReadyImplyGrant_A	424903152	214826	0	0
ReqImpliesValid_A	424903152	567831	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	214826	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	214826	0	0
T1	46590	87	0	0
T2	314827	255	0	0
T3	1110	5	0	0
T6	30232	69	0	0
T7	27712	57	0	0
T8	413771	13	0	0
T9	49306	144	0	0
T10	7337	59	0	0
T11	12135	212	0	0
T12	217552	142	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	214826	0	0
T1	46590	87	0	0
T2	314827	255	0	0
T3	1110	5	0	0
T6	30232	69	0	0
T7	27712	57	0	0
T8	413771	13	0	0
T9	49306	144	0	0
T10	7337	59	0	0
T11	12135	212	0	0
T12	217552	142	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	214826	0	0
T1	46590	87	0	0
T2	314827	255	0	0
T3	1110	5	0	0
T6	30232	69	0	0
T7	27712	57	0	0
T8	413771	13	0	0
T9	49306	144	0	0
T10	7337	59	0	0
T11	12135	212	0	0
T12	217552	142	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	3125360	0	0
T1	46590	596	0	0
T2	314827	84640	0	0
T3	1110	6	0	0
T6	30232	493	0	0
T7	27712	411	0	0
T8	413771	6179	0	0
T9	49306	1129	0	0
T10	7337	60	0	0
T11	12135	204	0	0
T12	217552	45338	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	214826	0	0
T1	46590	87	0	0
T2	314827	255	0	0
T3	1110	5	0	0
T6	30232	69	0	0
T7	27712	57	0	0
T8	413771	13	0	0
T9	49306	144	0	0
T10	7337	59	0	0
T11	12135	212	0	0
T12	217552	142	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	214826	0	0
T1	46590	87	0	0
T2	314827	255	0	0
T3	1110	5	0	0
T6	30232	69	0	0
T7	27712	57	0	0
T8	413771	13	0	0
T9	49306	144	0	0
T10	7337	59	0	0
T11	12135	212	0	0
T12	217552	142	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	567831	0	0
T1	46590	104	0	0
T2	314827	4292	0	0
T3	1110	5	0	0
T6	30232	81	0	0
T7	27712	58	0	0
T8	413771	223	0	0
T9	49306	162	0	0
T10	7337	59	0	0
T11	12135	221	0	0
T12	217552	2494	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	214826	0	0
T1	46590	87	0	0
T2	314827	255	0	0
T3	1110	5	0	0
T6	30232	69	0	0
T7	27712	57	0	0
T8	413771	13	0	0
T9	49306	144	0	0
T10	7337	59	0	0
T11	12135	212	0	0
T12	217552	142	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	215998	0	0
GntImpliesValid_A	424903152	215998	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	215998	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	3098820	0	0
ReadyAndValidImplyGrant_A	424903152	215998	0	0
ReqAndReadyImplyGrant_A	424903152	215998	0	0
ReqImpliesValid_A	424903152	583166	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	215998	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	215998	0	0
T1	46590	77	0	0
T2	314827	230	0	0
T3	1110	8	0	0
T6	30232	92	0	0
T7	27712	47	0	0
T8	413771	10	0	0
T9	49306	135	0	0
T10	7337	68	0	0
T11	12135	198	0	0
T12	217552	141	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	215998	0	0
T1	46590	77	0	0
T2	314827	230	0	0
T3	1110	8	0	0
T6	30232	92	0	0
T7	27712	47	0	0
T8	413771	10	0	0
T9	49306	135	0	0
T10	7337	68	0	0
T11	12135	198	0	0
T12	217552	141	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	215998	0	0
T1	46590	77	0	0
T2	314827	230	0	0
T3	1110	8	0	0
T6	30232	92	0	0
T7	27712	47	0	0
T8	413771	10	0	0
T9	49306	135	0	0
T10	7337	68	0	0
T11	12135	198	0	0
T12	217552	141	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	3098820	0	0
T1	46590	573	0	0
T2	314827	76244	0	0
T3	1110	9	0	0
T6	30232	682	0	0
T7	27712	387	0	0
T8	413771	2749	0	0
T9	49306	1044	0	0
T10	7337	68	0	0
T11	12135	187	0	0
T12	217552	45282	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	215998	0	0
T1	46590	77	0	0
T2	314827	230	0	0
T3	1110	8	0	0
T6	30232	92	0	0
T7	27712	47	0	0
T8	413771	10	0	0
T9	49306	135	0	0
T10	7337	68	0	0
T11	12135	198	0	0
T12	217552	141	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	215998	0	0
T1	46590	77	0	0
T2	314827	230	0	0
T3	1110	8	0	0
T6	30232	92	0	0
T7	27712	47	0	0
T8	413771	10	0	0
T9	49306	135	0	0
T10	7337	68	0	0
T11	12135	198	0	0
T12	217552	141	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	583166	0	0
T1	46590	80	0	0
T2	314827	5064	0	0
T3	1110	8	0	0
T6	30232	137	0	0
T7	27712	47	0	0
T8	413771	10	0	0
T9	49306	192	0	0
T10	7337	69	0	0
T11	12135	210	0	0
T12	217552	2605	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	215998	0	0
T1	46590	77	0	0
T2	314827	230	0	0
T3	1110	8	0	0
T6	30232	92	0	0
T7	27712	47	0	0
T8	413771	10	0	0
T9	49306	135	0	0
T10	7337	68	0	0
T11	12135	198	0	0
T12	217552	141	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	214041	0	0
GntImpliesValid_A	424903152	214041	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	214041	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	3130873	0	0
ReadyAndValidImplyGrant_A	424903152	214041	0	0
ReqAndReadyImplyGrant_A	424903152	214041	0	0
ReqImpliesValid_A	424903152	610685	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	214041	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	214041	0	0
T1	46590	74	0	0
T2	314827	228	0	0
T3	1110	8	0	0
T6	30232	87	0	0
T7	27712	54	0	0
T8	413771	16	0	0
T9	49306	149	0	0
T10	7337	81	0	0
T11	12135	201	0	0
T12	217552	131	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	214041	0	0
T1	46590	74	0	0
T2	314827	228	0	0
T3	1110	8	0	0
T6	30232	87	0	0
T7	27712	54	0	0
T8	413771	16	0	0
T9	49306	149	0	0
T10	7337	81	0	0
T11	12135	201	0	0
T12	217552	131	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	214041	0	0
T1	46590	74	0	0
T2	314827	228	0	0
T3	1110	8	0	0
T6	30232	87	0	0
T7	27712	54	0	0
T8	413771	16	0	0
T9	49306	149	0	0
T10	7337	81	0	0
T11	12135	201	0	0
T12	217552	131	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	3130873	0	0
T1	46590	538	0	0
T2	314827	74605	0	0
T3	1110	9	0	0
T6	30232	690	0	0
T7	27712	446	0	0
T8	413771	6453	0	0
T9	49306	1086	0	0
T10	7337	80	0	0
T11	12135	185	0	0
T12	217552	38321	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	214041	0	0
T1	46590	74	0	0
T2	314827	228	0	0
T3	1110	8	0	0
T6	30232	87	0	0
T7	27712	54	0	0
T8	413771	16	0	0
T9	49306	149	0	0
T10	7337	81	0	0
T11	12135	201	0	0
T12	217552	131	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	214041	0	0
T1	46590	74	0	0
T2	314827	228	0	0
T3	1110	8	0	0
T6	30232	87	0	0
T7	27712	54	0	0
T8	413771	16	0	0
T9	49306	149	0	0
T10	7337	81	0	0
T11	12135	201	0	0
T12	217552	131	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	610685	0	0
T1	46590	74	0	0
T2	314827	2489	0	0
T3	1110	8	0	0
T6	30232	102	0	0
T7	27712	72	0	0
T8	413771	16	0	0
T9	49306	223	0	0
T10	7337	83	0	0
T11	12135	218	0	0
T12	217552	3926	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	214041	0	0
T1	46590	74	0	0
T2	314827	228	0	0
T3	1110	8	0	0
T6	30232	87	0	0
T7	27712	54	0	0
T8	413771	16	0	0
T9	49306	149	0	0
T10	7337	81	0	0
T11	12135	201	0	0
T12	217552	131	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	220538	0	0
GntImpliesValid_A	424903152	220538	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	220538	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	3107307	0	0
ReadyAndValidImplyGrant_A	424903152	220538	0	0
ReqAndReadyImplyGrant_A	424903152	220538	0	0
ReqImpliesValid_A	424903152	623242	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	220538	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	220538	0	0
T1	46590	90	0	0
T2	314827	220	0	0
T3	1110	12	0	0
T6	30232	97	0	0
T7	27712	66	0	0
T8	413771	13	0	0
T9	49306	137	0	0
T10	7337	56	0	0
T11	12135	214	0	0
T12	217552	154	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	220538	0	0
T1	46590	90	0	0
T2	314827	220	0	0
T3	1110	12	0	0
T6	30232	97	0	0
T7	27712	66	0	0
T8	413771	13	0	0
T9	49306	137	0	0
T10	7337	56	0	0
T11	12135	214	0	0
T12	217552	154	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	220538	0	0
T1	46590	90	0	0
T2	314827	220	0	0
T3	1110	12	0	0
T6	30232	97	0	0
T7	27712	66	0	0
T8	413771	13	0	0
T9	49306	137	0	0
T10	7337	56	0	0
T11	12135	214	0	0
T12	217552	154	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	3107307	0	0
T1	46590	665	0	0
T2	314827	71552	0	0
T3	1110	13	0	0
T6	30232	721	0	0
T7	27712	489	0	0
T8	413771	3396	0	0
T9	49306	1005	0	0
T10	7337	56	0	0
T11	12135	203	0	0
T12	217552	52663	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	220538	0	0
T1	46590	90	0	0
T2	314827	220	0	0
T3	1110	12	0	0
T6	30232	97	0	0
T7	27712	66	0	0
T8	413771	13	0	0
T9	49306	137	0	0
T10	7337	56	0	0
T11	12135	214	0	0
T12	217552	154	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	220538	0	0
T1	46590	90	0	0
T2	314827	220	0	0
T3	1110	12	0	0
T6	30232	97	0	0
T7	27712	66	0	0
T8	413771	13	0	0
T9	49306	137	0	0
T10	7337	56	0	0
T11	12135	214	0	0
T12	217552	154	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	623242	0	0
T1	46590	114	0	0
T2	314827	4692	0	0
T3	1110	12	0	0
T6	30232	147	0	0
T7	27712	96	0	0
T8	413771	277	0	0
T9	49306	203	0	0
T10	7337	57	0	0
T11	12135	226	0	0
T12	217552	4882	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	220538	0	0
T1	46590	90	0	0
T2	314827	220	0	0
T3	1110	12	0	0
T6	30232	97	0	0
T7	27712	66	0	0
T8	413771	13	0	0
T9	49306	137	0	0
T10	7337	56	0	0
T11	12135	214	0	0
T12	217552	154	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	228307	0	0
GntImpliesValid_A	424903152	228307	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	228307	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	3122204	0	0
ReadyAndValidImplyGrant_A	424903152	228307	0	0
ReqAndReadyImplyGrant_A	424903152	228307	0	0
ReqImpliesValid_A	424903152	637175	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	228307	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	228307	0	0
T1	46590	59	0	0
T2	314827	211	0	0
T3	1110	9	0	0
T6	30232	108	0	0
T7	27712	57	0	0
T8	413771	10	0	0
T9	49306	139	0	0
T10	7337	49	0	0
T11	12135	209	0	0
T12	217552	123	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	228307	0	0
T1	46590	59	0	0
T2	314827	211	0	0
T3	1110	9	0	0
T6	30232	108	0	0
T7	27712	57	0	0
T8	413771	10	0	0
T9	49306	139	0	0
T10	7337	49	0	0
T11	12135	209	0	0
T12	217552	123	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	228307	0	0
T1	46590	59	0	0
T2	314827	211	0	0
T3	1110	9	0	0
T6	30232	108	0	0
T7	27712	57	0	0
T8	413771	10	0	0
T9	49306	139	0	0
T10	7337	49	0	0
T11	12135	209	0	0
T12	217552	123	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	3122204	0	0
T1	46590	475	0	0
T2	314827	69091	0	0
T3	1110	9	0	0
T6	30232	837	0	0
T7	27712	448	0	0
T8	413771	3435	0	0
T9	49306	925	0	0
T10	7337	46	0	0
T11	12135	195	0	0
T12	217552	41248	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	228307	0	0
T1	46590	59	0	0
T2	314827	211	0	0
T3	1110	9	0	0
T6	30232	108	0	0
T7	27712	57	0	0
T8	413771	10	0	0
T9	49306	139	0	0
T10	7337	49	0	0
T11	12135	209	0	0
T12	217552	123	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	228307	0	0
T1	46590	59	0	0
T2	314827	211	0	0
T3	1110	9	0	0
T6	30232	108	0	0
T7	27712	57	0	0
T8	413771	10	0	0
T9	49306	139	0	0
T10	7337	49	0	0
T11	12135	209	0	0
T12	217552	123	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	637175	0	0
T1	46590	64	0	0
T2	314827	4214	0	0
T3	1110	10	0	0
T6	30232	157	0	0
T7	27712	78	0	0
T8	413771	10	0	0
T9	49306	191	0	0
T10	7337	53	0	0
T11	12135	224	0	0
T12	217552	2228	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	228307	0	0
T1	46590	59	0	0
T2	314827	211	0	0
T3	1110	9	0	0
T6	30232	108	0	0
T7	27712	57	0	0
T8	413771	10	0	0
T9	49306	139	0	0
T10	7337	49	0	0
T11	12135	209	0	0
T12	217552	123	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	229748	0	0
GntImpliesValid_A	424903152	229748	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	229748	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	3055069	0	0
ReadyAndValidImplyGrant_A	424903152	229748	0	0
ReqAndReadyImplyGrant_A	424903152	229748	0	0
ReqImpliesValid_A	424903152	646025	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	229748	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	229748	0	0
T1	46590	75	0	0
T2	314827	236	0	0
T3	1110	10	0	0
T6	30232	73	0	0
T7	27712	45	0	0
T8	413771	14	0	0
T9	49306	147	0	0
T10	7337	65	0	0
T11	12135	184	0	0
T12	217552	153	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	229748	0	0
T1	46590	75	0	0
T2	314827	236	0	0
T3	1110	10	0	0
T6	30232	73	0	0
T7	27712	45	0	0
T8	413771	14	0	0
T9	49306	147	0	0
T10	7337	65	0	0
T11	12135	184	0	0
T12	217552	153	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	229748	0	0
T1	46590	75	0	0
T2	314827	236	0	0
T3	1110	10	0	0
T6	30232	73	0	0
T7	27712	45	0	0
T8	413771	14	0	0
T9	49306	147	0	0
T10	7337	65	0	0
T11	12135	184	0	0
T12	217552	153	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	3055069	0	0
T1	46590	624	0	0
T2	314827	72406	0	0
T3	1110	11	0	0
T6	30232	600	0	0
T7	27712	342	0	0
T8	413771	6147	0	0
T9	49306	1194	0	0
T10	7337	63	0	0
T11	12135	174	0	0
T12	217552	45868	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	229748	0	0
T1	46590	75	0	0
T2	314827	236	0	0
T3	1110	10	0	0
T6	30232	73	0	0
T7	27712	45	0	0
T8	413771	14	0	0
T9	49306	147	0	0
T10	7337	65	0	0
T11	12135	184	0	0
T12	217552	153	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	229748	0	0
T1	46590	75	0	0
T2	314827	236	0	0
T3	1110	10	0	0
T6	30232	73	0	0
T7	27712	45	0	0
T8	413771	14	0	0
T9	49306	147	0	0
T10	7337	65	0	0
T11	12135	184	0	0
T12	217552	153	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	646025	0	0
T1	46590	79	0	0
T2	314827	4257	0	0
T3	1110	10	0	0
T6	30232	83	0	0
T7	27712	67	0	0
T8	413771	14	0	0
T9	49306	161	0	0
T10	7337	68	0	0
T11	12135	195	0	0
T12	217552	4572	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	229748	0	0
T1	46590	75	0	0
T2	314827	236	0	0
T3	1110	10	0	0
T6	30232	73	0	0
T7	27712	45	0	0
T8	413771	14	0	0
T9	49306	147	0	0
T10	7337	65	0	0
T11	12135	184	0	0
T12	217552	153	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	238015	0	0
GntImpliesValid_A	424903152	238015	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	238015	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	3194729	0	0
ReadyAndValidImplyGrant_A	424903152	238015	0	0
ReqAndReadyImplyGrant_A	424903152	238015	0	0
ReqImpliesValid_A	424903152	583515	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	238015	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	238015	0	0
T1	46590	113	0	0
T2	314827	226	0	0
T3	1110	11	0	0
T6	30232	74	0	0
T7	27712	90	0	0
T8	413771	11	0	0
T9	49306	140	0	0
T10	7337	102	0	0
T11	12135	202	0	0
T12	217552	134	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	238015	0	0
T1	46590	113	0	0
T2	314827	226	0	0
T3	1110	11	0	0
T6	30232	74	0	0
T7	27712	90	0	0
T8	413771	11	0	0
T9	49306	140	0	0
T10	7337	102	0	0
T11	12135	202	0	0
T12	217552	134	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	238015	0	0
T1	46590	113	0	0
T2	314827	226	0	0
T3	1110	11	0	0
T6	30232	74	0	0
T7	27712	90	0	0
T8	413771	11	0	0
T9	49306	140	0	0
T10	7337	102	0	0
T11	12135	202	0	0
T12	217552	134	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	3194729	0	0
T1	46590	911	0	0
T2	314827	64655	0	0
T3	1110	11	0	0
T6	30232	513	0	0
T7	27712	788	0	0
T8	413771	3882	0	0
T9	49306	1076	0	0
T10	7337	99	0	0
T11	12135	193	0	0
T12	217552	48928	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	238015	0	0
T1	46590	113	0	0
T2	314827	226	0	0
T3	1110	11	0	0
T6	30232	74	0	0
T7	27712	90	0	0
T8	413771	11	0	0
T9	49306	140	0	0
T10	7337	102	0	0
T11	12135	202	0	0
T12	217552	134	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	238015	0	0
T1	46590	113	0	0
T2	314827	226	0	0
T3	1110	11	0	0
T6	30232	74	0	0
T7	27712	90	0	0
T8	413771	11	0	0
T9	49306	140	0	0
T10	7337	102	0	0
T11	12135	202	0	0
T12	217552	134	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	583515	0	0
T1	46590	177	0	0
T2	314827	5426	0	0
T3	1110	12	0	0
T6	30232	88	0	0
T7	27712	93	0	0
T8	413771	11	0	0
T9	49306	161	0	0
T10	7337	106	0	0
T11	12135	212	0	0
T12	217552	3581	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	238015	0	0
T1	46590	113	0	0
T2	314827	226	0	0
T3	1110	11	0	0
T6	30232	74	0	0
T7	27712	90	0	0
T8	413771	11	0	0
T9	49306	140	0	0
T10	7337	102	0	0
T11	12135	202	0	0
T12	217552	134	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	227797	0	0
GntImpliesValid_A	424903152	227797	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	227797	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	3128272	0	0
ReadyAndValidImplyGrant_A	424903152	227797	0	0
ReqAndReadyImplyGrant_A	424903152	227797	0	0
ReqImpliesValid_A	424903152	572521	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	227797	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	227797	0	0
T1	46590	67	0	0
T2	314827	219	0	0
T3	1110	5	0	0
T6	30232	93	0	0
T7	27712	61	0	0
T8	413771	10	0	0
T9	49306	152	0	0
T10	7337	57	0	0
T11	12135	233	0	0
T12	217552	135	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	227797	0	0
T1	46590	67	0	0
T2	314827	219	0	0
T3	1110	5	0	0
T6	30232	93	0	0
T7	27712	61	0	0
T8	413771	10	0	0
T9	49306	152	0	0
T10	7337	57	0	0
T11	12135	233	0	0
T12	217552	135	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	227797	0	0
T1	46590	67	0	0
T2	314827	219	0	0
T3	1110	5	0	0
T6	30232	93	0	0
T7	27712	61	0	0
T8	413771	10	0	0
T9	49306	152	0	0
T10	7337	57	0	0
T11	12135	233	0	0
T12	217552	135	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	3128272	0	0
T1	46590	509	0	0
T2	314827	75885	0	0
T3	1110	6	0	0
T6	30232	712	0	0
T7	27712	488	0	0
T8	413771	3186	0	0
T9	49306	1023	0	0
T10	7337	58	0	0
T11	12135	222	0	0
T12	217552	42630	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	227797	0	0
T1	46590	67	0	0
T2	314827	219	0	0
T3	1110	5	0	0
T6	30232	93	0	0
T7	27712	61	0	0
T8	413771	10	0	0
T9	49306	152	0	0
T10	7337	57	0	0
T11	12135	233	0	0
T12	217552	135	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	227797	0	0
T1	46590	67	0	0
T2	314827	219	0	0
T3	1110	5	0	0
T6	30232	93	0	0
T7	27712	61	0	0
T8	413771	10	0	0
T9	49306	152	0	0
T10	7337	57	0	0
T11	12135	233	0	0
T12	217552	135	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	572521	0	0
T1	46590	89	0	0
T2	314827	3812	0	0
T3	1110	5	0	0
T6	30232	150	0	0
T7	27712	69	0	0
T8	413771	10	0	0
T9	49306	228	0	0
T10	7337	57	0	0
T11	12135	245	0	0
T12	217552	3042	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	227797	0	0
T1	46590	67	0	0
T2	314827	219	0	0
T3	1110	5	0	0
T6	30232	93	0	0
T7	27712	61	0	0
T8	413771	10	0	0
T9	49306	152	0	0
T10	7337	57	0	0
T11	12135	233	0	0
T12	217552	135	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	227644	0	0
GntImpliesValid_A	424903152	227644	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	227644	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	3146082	0	0
ReadyAndValidImplyGrant_A	424903152	227644	0	0
ReqAndReadyImplyGrant_A	424903152	227644	0	0
ReqImpliesValid_A	424903152	647458	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	227644	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	227644	0	0
T1	46590	50	0	0
T2	314827	219	0	0
T3	1110	14	0	0
T6	30232	75	0	0
T7	27712	54	0	0
T8	413771	5	0	0
T9	49306	138	0	0
T10	7337	61	0	0
T11	12135	211	0	0
T12	217552	130	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	227644	0	0
T1	46590	50	0	0
T2	314827	219	0	0
T3	1110	14	0	0
T6	30232	75	0	0
T7	27712	54	0	0
T8	413771	5	0	0
T9	49306	138	0	0
T10	7337	61	0	0
T11	12135	211	0	0
T12	217552	130	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	227644	0	0
T1	46590	50	0	0
T2	314827	219	0	0
T3	1110	14	0	0
T6	30232	75	0	0
T7	27712	54	0	0
T8	413771	5	0	0
T9	49306	138	0	0
T10	7337	61	0	0
T11	12135	211	0	0
T12	217552	130	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	3146082	0	0
T1	46590	417	0	0
T2	314827	71348	0	0
T3	1110	13	0	0
T6	30232	566	0	0
T7	27712	444	0	0
T8	413771	1569	0	0
T9	49306	1005	0	0
T10	7337	61	0	0
T11	12135	203	0	0
T12	217552	42687	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	227644	0	0
T1	46590	50	0	0
T2	314827	219	0	0
T3	1110	14	0	0
T6	30232	75	0	0
T7	27712	54	0	0
T8	413771	5	0	0
T9	49306	138	0	0
T10	7337	61	0	0
T11	12135	211	0	0
T12	217552	130	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	227644	0	0
T1	46590	50	0	0
T2	314827	219	0	0
T3	1110	14	0	0
T6	30232	75	0	0
T7	27712	54	0	0
T8	413771	5	0	0
T9	49306	138	0	0
T10	7337	61	0	0
T11	12135	211	0	0
T12	217552	130	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	647458	0	0
T1	46590	69	0	0
T2	314827	5416	0	0
T3	1110	16	0	0
T6	30232	111	0	0
T7	27712	86	0	0
T8	413771	428	0	0
T9	49306	203	0	0
T10	7337	62	0	0
T11	12135	220	0	0
T12	217552	2403	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	227644	0	0
T1	46590	50	0	0
T2	314827	219	0	0
T3	1110	14	0	0
T6	30232	75	0	0
T7	27712	54	0	0
T8	413771	5	0	0
T9	49306	138	0	0
T10	7337	61	0	0
T11	12135	211	0	0
T12	217552	130	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	218318	0	0
GntImpliesValid_A	424903152	218318	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	218318	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	3149379	0	0
ReadyAndValidImplyGrant_A	424903152	218318	0	0
ReqAndReadyImplyGrant_A	424903152	218318	0	0
ReqImpliesValid_A	424903152	600678	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	218318	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	218318	0	0
T1	46590	80	0	0
T2	314827	197	0	0
T3	1110	8	0	0
T6	30232	89	0	0
T7	27712	44	0	0
T8	413771	5	0	0
T9	49306	150	0	0
T10	7337	64	0	0
T11	12135	176	0	0
T12	217552	147	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	218318	0	0
T1	46590	80	0	0
T2	314827	197	0	0
T3	1110	8	0	0
T6	30232	89	0	0
T7	27712	44	0	0
T8	413771	5	0	0
T9	49306	150	0	0
T10	7337	64	0	0
T11	12135	176	0	0
T12	217552	147	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	218318	0	0
T1	46590	80	0	0
T2	314827	197	0	0
T3	1110	8	0	0
T6	30232	89	0	0
T7	27712	44	0	0
T8	413771	5	0	0
T9	49306	150	0	0
T10	7337	64	0	0
T11	12135	176	0	0
T12	217552	147	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	3149379	0	0
T1	46590	650	0	0
T2	314827	62212	0	0
T3	1110	9	0	0
T6	30232	657	0	0
T7	27712	300	0	0
T8	413771	2316	0	0
T9	49306	985	0	0
T10	7337	62	0	0
T11	12135	164	0	0
T12	217552	41316	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	218318	0	0
T1	46590	80	0	0
T2	314827	197	0	0
T3	1110	8	0	0
T6	30232	89	0	0
T7	27712	44	0	0
T8	413771	5	0	0
T9	49306	150	0	0
T10	7337	64	0	0
T11	12135	176	0	0
T12	217552	147	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	218318	0	0
T1	46590	80	0	0
T2	314827	197	0	0
T3	1110	8	0	0
T6	30232	89	0	0
T7	27712	44	0	0
T8	413771	5	0	0
T9	49306	150	0	0
T10	7337	64	0	0
T11	12135	176	0	0
T12	217552	147	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	600678	0	0
T1	46590	93	0	0
T2	314827	2949	0	0
T3	1110	8	0	0
T6	30232	118	0	0
T7	27712	45	0	0
T8	413771	5	0	0
T9	49306	183	0	0
T10	7337	67	0	0
T11	12135	189	0	0
T12	217552	4976	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	218318	0	0
T1	46590	80	0	0
T2	314827	197	0	0
T3	1110	8	0	0
T6	30232	89	0	0
T7	27712	44	0	0
T8	413771	5	0	0
T9	49306	150	0	0
T10	7337	64	0	0
T11	12135	176	0	0
T12	217552	147	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	216721	0	0
GntImpliesValid_A	424903152	216721	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	216721	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	3085208	0	0
ReadyAndValidImplyGrant_A	424903152	216721	0	0
ReqAndReadyImplyGrant_A	424903152	216721	0	0
ReqImpliesValid_A	424903152	565716	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	216721	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	216721	0	0
T1	46590	68	0	0
T2	314827	234	0	0
T3	1110	16	0	0
T6	30232	111	0	0
T7	27712	51	0	0
T8	413771	12	0	0
T9	49306	163	0	0
T10	7337	76	0	0
T11	12135	196	0	0
T12	217552	138	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	216721	0	0
T1	46590	68	0	0
T2	314827	234	0	0
T3	1110	16	0	0
T6	30232	111	0	0
T7	27712	51	0	0
T8	413771	12	0	0
T9	49306	163	0	0
T10	7337	76	0	0
T11	12135	196	0	0
T12	217552	138	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	216721	0	0
T1	46590	68	0	0
T2	314827	234	0	0
T3	1110	16	0	0
T6	30232	111	0	0
T7	27712	51	0	0
T8	413771	12	0	0
T9	49306	163	0	0
T10	7337	76	0	0
T11	12135	196	0	0
T12	217552	138	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	3085208	0	0
T1	46590	525	0	0
T2	314827	74448	0	0
T3	1110	13	0	0
T6	30232	882	0	0
T7	27712	364	0	0
T8	413771	3162	0	0
T9	49306	1268	0	0
T10	7337	71	0	0
T11	12135	185	0	0
T12	217552	45298	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	216721	0	0
T1	46590	68	0	0
T2	314827	234	0	0
T3	1110	16	0	0
T6	30232	111	0	0
T7	27712	51	0	0
T8	413771	12	0	0
T9	49306	163	0	0
T10	7337	76	0	0
T11	12135	196	0	0
T12	217552	138	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	216721	0	0
T1	46590	68	0	0
T2	314827	234	0	0
T3	1110	16	0	0
T6	30232	111	0	0
T7	27712	51	0	0
T8	413771	12	0	0
T9	49306	163	0	0
T10	7337	76	0	0
T11	12135	196	0	0
T12	217552	138	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	565716	0	0
T1	46590	89	0	0
T2	314827	2825	0	0
T3	1110	20	0	0
T6	30232	212	0	0
T7	27712	69	0	0
T8	413771	101	0	0
T9	49306	244	0	0
T10	7337	82	0	0
T11	12135	208	0	0
T12	217552	2935	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	216721	0	0
T1	46590	68	0	0
T2	314827	234	0	0
T3	1110	16	0	0
T6	30232	111	0	0
T7	27712	51	0	0
T8	413771	12	0	0
T9	49306	163	0	0
T10	7337	76	0	0
T11	12135	196	0	0
T12	217552	138	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	219108	0	0
GntImpliesValid_A	424903152	219108	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	219108	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	3094787	0	0
ReadyAndValidImplyGrant_A	424903152	219108	0	0
ReqAndReadyImplyGrant_A	424903152	219108	0	0
ReqImpliesValid_A	424903152	562348	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	0	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	219108	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	219108	0	0
T1	46590	71	0	0
T2	314827	220	0	0
T3	1110	11	0	0
T6	30232	100	0	0
T7	27712	40	0	0
T8	413771	13	0	0
T9	49306	123	0	0
T10	7337	54	0	0
T11	12135	224	0	0
T12	217552	149	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	219108	0	0
T1	46590	71	0	0
T2	314827	220	0	0
T3	1110	11	0	0
T6	30232	100	0	0
T7	27712	40	0	0
T8	413771	13	0	0
T9	49306	123	0	0
T10	7337	54	0	0
T11	12135	224	0	0
T12	217552	149	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	219108	0	0
T1	46590	71	0	0
T2	314827	220	0	0
T3	1110	11	0	0
T6	30232	100	0	0
T7	27712	40	0	0
T8	413771	13	0	0
T9	49306	123	0	0
T10	7337	54	0	0
T11	12135	224	0	0
T12	217552	149	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	3094787	0	0
T1	46590	517	0	0
T2	314827	71073	0	0
T3	1110	10	0	0
T6	30232	739	0	0
T7	27712	301	0	0
T8	413771	5331	0	0
T9	49306	922	0	0
T10	7337	52	0	0
T11	12135	212	0	0
T12	217552	50100	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	219108	0	0
T1	46590	71	0	0
T2	314827	220	0	0
T3	1110	11	0	0
T6	30232	100	0	0
T7	27712	40	0	0
T8	413771	13	0	0
T9	49306	123	0	0
T10	7337	54	0	0
T11	12135	224	0	0
T12	217552	149	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	219108	0	0
T1	46590	71	0	0
T2	314827	220	0	0
T3	1110	11	0	0
T6	30232	100	0	0
T7	27712	40	0	0
T8	413771	13	0	0
T9	49306	123	0	0
T10	7337	54	0	0
T11	12135	224	0	0
T12	217552	149	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	562348	0	0
T1	46590	82	0	0
T2	314827	4934	0	0
T3	1110	13	0	0
T6	30232	123	0	0
T7	27712	58	0	0
T8	413771	72	0	0
T9	49306	157	0	0
T10	7337	57	0	0
T11	12135	237	0	0
T12	217552	1375	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	219108	0	0
T1	46590	71	0	0
T2	314827	220	0	0
T3	1110	11	0	0
T6	30232	100	0	0
T7	27712	40	0	0
T8	413771	13	0	0
T9	49306	123	0	0
T10	7337	54	0	0
T11	12135	224	0	0
T12	217552	149	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	877215	0	0
GntImpliesValid_A	424903152	877215	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	877215	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	11926867	0	0
ReadyAndValidImplyGrant_A	424903152	877215	0	0
ReqAndReadyImplyGrant_A	424903152	877215	0	0
ReqImpliesValid_A	424903152	2412106	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	16380	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	877215	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	877215	0	0
T1	46590	307	0	0
T2	314827	884	0	0
T3	1110	46	0	0
T6	30232	344	0	0
T7	27712	229	0	0
T8	413771	36	0	0
T9	49306	586	0	0
T10	7337	288	0	0
T11	12135	782	0	0
T12	217552	519	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	877215	0	0
T1	46590	307	0	0
T2	314827	884	0	0
T3	1110	46	0	0
T6	30232	344	0	0
T7	27712	229	0	0
T8	413771	36	0	0
T9	49306	586	0	0
T10	7337	288	0	0
T11	12135	782	0	0
T12	217552	519	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	877215	0	0
T1	46590	307	0	0
T2	314827	884	0	0
T3	1110	46	0	0
T6	30232	344	0	0
T7	27712	229	0	0
T8	413771	36	0	0
T9	49306	586	0	0
T10	7337	288	0	0
T11	12135	782	0	0
T12	217552	519	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	11926867	0	0
T1	46590	1959	0	0
T2	314827	293565	0	0
T3	1110	1	0	0
T6	30232	2278	0	0
T7	27712	1443	0	0
T8	413771	14361	0	0
T9	49306	3352	0	0
T10	7337	1	0	0
T11	12135	1	0	0
T12	217552	169338	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	877215	0	0
T1	46590	307	0	0
T2	314827	884	0	0
T3	1110	46	0	0
T6	30232	344	0	0
T7	27712	229	0	0
T8	413771	36	0	0
T9	49306	586	0	0
T10	7337	288	0	0
T11	12135	782	0	0
T12	217552	519	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	877215	0	0
T1	46590	307	0	0
T2	314827	884	0	0
T3	1110	46	0	0
T6	30232	344	0	0
T7	27712	229	0	0
T8	413771	36	0	0
T9	49306	586	0	0
T10	7337	288	0	0
T11	12135	782	0	0
T12	217552	519	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	2412106	0	0
T1	46590	386	0	0
T2	314827	37680	0	0
T3	1110	46	0	0
T6	30232	557	0	0
T7	27712	396	0	0
T8	413771	898	0	0
T9	49306	854	0	0
T10	7337	288	0	0
T11	12135	782	0	0
T12	217552	14518	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	16380	0	900
T1	46590	1	0	1
T2	314827	0	0	1
T3	1110	0	0	1
T6	30232	0	0	1
T7	27712	0	0	1
T8	413771	0	0	1
T9	49306	0	0	1
T10	7337	4	0	1
T11	12135	14	0	1
T12	217552	0	0	1
T13	0	6	0	0
T14	0	12	0	0
T15	0	142	0	0
T16	0	685	0	0
T18	0	59	0	0
T19	0	1	0	0
T20	0	2	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	877215	0	0
T1	46590	307	0	0
T2	314827	884	0	0
T3	1110	46	0	0
T6	30232	344	0	0
T7	27712	229	0	0
T8	413771	36	0	0
T9	49306	586	0	0
T10	7337	288	0	0
T11	12135	782	0	0
T12	217552	519	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	424903152	424786060	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	424903152	870589	0	0
GntImpliesValid_A	424903152	870589	0	0
GrantKnown_A	424903152	424786060	0	0
IdxKnown_A	424903152	424786060	0	0
IndexIsCorrect_A	424903152	870589	0	0
LockArbDecision_A	424903152	0	0	0
NoReadyValidNoGrant_A	424903152	356837100	0	0
ReadyAndValidImplyGrant_A	424903152	870589	0	0
ReqAndReadyImplyGrant_A	424903152	870589	0	0
ReqImpliesValid_A	424903152	13696528	0	0
ReqStaysHighUntilGranted0_M	424903152	0	0	0
RoundRobin_A	424903152	28390	0	900
ValidKnown_A	424903152	424786060	0	0
gen_data_port_assertion.DataFlow_A	424903152	870589	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	870589	0	0
T1	46590	326	0	0
T2	314827	869	0	0
T3	1110	56	0	0
T6	30232	311	0	0
T7	27712	191	0	0
T8	413771	45	0	0
T9	49306	585	0	0
T10	7337	257	0	0
T11	12135	765	0	0
T12	217552	580	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	870589	0	0
T1	46590	326	0	0
T2	314827	869	0	0
T3	1110	56	0	0
T6	30232	311	0	0
T7	27712	191	0	0
T8	413771	45	0	0
T9	49306	585	0	0
T10	7337	257	0	0
T11	12135	765	0	0
T12	217552	580	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	870589	0	0
T1	46590	326	0	0
T2	314827	869	0	0
T3	1110	56	0	0
T6	30232	311	0	0
T7	27712	191	0	0
T8	413771	45	0	0
T9	49306	585	0	0
T10	7337	257	0	0
T11	12135	765	0	0
T12	217552	580	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	356837100	0	0
T1	46590	39236	0	0
T2	314827	283633	0	0
T3	1110	1	0	0
T6	30232	25472	0	0
T7	27712	23261	0	0
T8	413771	397364	0	0
T9	49306	40880	0	0
T10	7337	1	0	0
T11	12135	1	0	0
T12	217552	189107	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	870589	0	0
T1	46590	326	0	0
T2	314827	869	0	0
T3	1110	56	0	0
T6	30232	311	0	0
T7	27712	191	0	0
T8	413771	45	0	0
T9	49306	585	0	0
T10	7337	257	0	0
T11	12135	765	0	0
T12	217552	580	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	870589	0	0
T1	46590	326	0	0
T2	314827	869	0	0
T3	1110	56	0	0
T6	30232	311	0	0
T7	27712	191	0	0
T8	413771	45	0	0
T9	49306	585	0	0
T10	7337	257	0	0
T11	12135	765	0	0
T12	217552	580	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	13696528	0	0
T1	46590	2487	0	0
T2	314827	306446	0	0
T3	1110	56	0	0
T6	30232	2323	0	0
T7	27712	1513	0	0
T8	413771	15584	0	0
T9	49306	4537	0	0
T10	7337	257	0	0
T11	12135	765	0	0
T12	217552	186522	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	28390	0	900
T1	46590	1	0	1
T2	314827	0	0	1
T3	1110	0	0	1
T6	30232	2	0	1
T7	27712	0	0	1
T8	413771	0	0	1
T9	49306	0	0	1
T10	7337	1	0	1
T11	12135	13	0	1
T12	217552	1	0	1
T13	0	3	0	0
T14	0	17	0	0
T15	0	236	0	0
T16	0	2047	0	0
T17	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	424786060	0	0
T1	46590	46520	0	0
T2	314827	314819	0	0
T3	1110	1056	0	0
T6	30232	30213	0	0
T7	27712	27657	0	0
T8	413771	413744	0	0
T9	49306	49283	0	0
T10	7337	7295	0	0
T11	12135	12100	0	0
T12	217552	217547	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424903152	870589	0	0
T1	46590	326	0	0
T2	314827	869	0	0
T3	1110	56	0	0
T6	30232	311	0	0
T7	27712	191	0	0
T8	413771	45	0	0
T9	49306	585	0	0
T10	7337	257	0	0
T11	12135	765	0	0
T12	217552	580	0	0