Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1460387	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

231856

1

T1

23

T2

17

T3

296

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	575388	1			T1	146		T2	46		T3	770
values[0x0]	542101	1			T1	18		T2	40		T3	742
values[0x1]	574754	1			T1	148		T2	43		T3	765

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1128676	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

563567

1

T1

115

T2

40

T3

749

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26228	1			T1	4		T2	3		T3	5
valid_sources[0x01]	27021	1			T1	4		T2	2		T3	42
valid_sources[0x02]	26661	1			T1	4		T2	1		T7	112
valid_sources[0x03]	26409	1			T1	2		T3	44		T7	58
valid_sources[0x04]	25428	1			T1	2		T7	20		T8	22
valid_sources[0x05]	27007	1			T1	13		T2	6		T3	50
valid_sources[0x06]	26144	1			T1	8		T2	3		T3	17
valid_sources[0x07]	25908	1			T1	5		T2	3		T3	56
valid_sources[0x08]	25989	1			T1	6		T2	7		T3	41
valid_sources[0x09]	26484	1			T1	8		T2	6		T3	57
valid_sources[0x0a]	25615	1			T1	4		T2	1		T3	7
valid_sources[0x0b]	26105	1			T1	4		T2	1		T3	28
valid_sources[0x0c]	26342	1			T1	8		T3	22		T7	12
valid_sources[0x0d]	26399	1			T1	5		T3	28		T7	65
valid_sources[0x0e]	26748	1			T1	3		T2	1		T3	41
valid_sources[0x0f]	26155	1			T1	7		T3	61		T7	93
valid_sources[0x10]	26335	1			T1	5		T2	1		T3	46
valid_sources[0x11]	26220	1			T1	10		T3	5		T7	63
valid_sources[0x12]	25705	1			T1	2		T3	8		T7	31
valid_sources[0x13]	26944	1			T1	6		T2	3		T3	51
valid_sources[0x14]	27164	1			T1	7		T2	5		T3	45
valid_sources[0x15]	25800	1			T1	9		T2	8		T3	20
valid_sources[0x16]	26565	1			T1	7		T3	66		T7	65
valid_sources[0x17]	27479	1			T1	4		T3	31		T7	78
valid_sources[0x18]	26072	1			T1	4		T3	53		T7	25
valid_sources[0x19]	26246	1			T1	7		T2	1		T3	13
valid_sources[0x1a]	26679	1			T1	5		T3	6		T7	47
valid_sources[0x1b]	26804	1			T1	5		T2	1		T3	77
valid_sources[0x1c]	25735	1			T1	6		T2	2		T3	71
valid_sources[0x1d]	26347	1			T1	6		T2	3		T3	14
valid_sources[0x1e]	25573	1			T1	1		T3	16		T7	76
valid_sources[0x1f]	26166	1			T1	5		T3	39		T7	81
valid_sources[0x20]	27178	1			T1	3		T2	1		T3	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24883

1

T1

9

T2

2

T3

25

values[0x0]

all_enables

biggest_size

182476

1

T1

7

T2

14

T3

235

values[0x1]

all_enables

biggest_size

24497

1

T1

7

T2

1

T3

36

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1471458	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

238892

1

T1

46

T2

18

T3

323

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	586383	1			T1	164		T2	37		T3	747
values[0x0]	537507	1			T1	20		T2	43		T3	742
values[0x1]	586460	1			T1	163		T2	53		T3	794

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1128610	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

581740

1

T1

154

T2

38

T3

771

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26788	1			T2	3		T3	8		T7	61
valid_sources[0x01]	26787	1			T1	7		T2	3		T3	58
valid_sources[0x02]	26836	1			T1	3		T2	1		T7	38
valid_sources[0x03]	26371	1			T1	8		T2	5		T3	52
valid_sources[0x04]	26714	1			T1	5		T7	45		T8	41
valid_sources[0x05]	26976	1			T1	2		T2	4		T3	54
valid_sources[0x06]	26446	1			T1	3		T2	1		T3	28
valid_sources[0x07]	26799	1			T1	5		T2	4		T3	52
valid_sources[0x08]	26667	1			T1	3		T2	1		T3	47
valid_sources[0x09]	26434	1			T1	4		T2	1		T3	65
valid_sources[0x0a]	26286	1			T1	5		T2	5		T3	12
valid_sources[0x0b]	26068	1			T1	1		T2	4		T3	16
valid_sources[0x0c]	26665	1			T1	9		T3	29		T7	56
valid_sources[0x0d]	27966	1			T1	3		T2	4		T3	27
valid_sources[0x0e]	26866	1			T1	2		T2	3		T3	42
valid_sources[0x0f]	26320	1			T1	3		T2	2		T3	54
valid_sources[0x10]	27252	1			T1	6		T3	53		T7	40
valid_sources[0x11]	26094	1			T1	5		T2	3		T3	6
valid_sources[0x12]	26366	1			T1	4		T2	2		T3	5
valid_sources[0x13]	26578	1			T1	7		T2	2		T3	54
valid_sources[0x14]	26667	1			T1	4		T2	1		T3	42
valid_sources[0x15]	26138	1			T1	5		T2	2		T3	11
valid_sources[0x16]	26412	1			T1	10		T3	60		T7	35
valid_sources[0x17]	27469	1			T1	6		T2	7		T3	53
valid_sources[0x18]	26990	1			T1	10		T2	2		T3	32
valid_sources[0x19]	26998	1			T1	2		T2	4		T3	5
valid_sources[0x1a]	26417	1			T1	6		T2	1		T3	7
valid_sources[0x1b]	26882	1			T1	6		T2	2		T3	102
valid_sources[0x1c]	26251	1			T1	8		T3	43		T7	39
valid_sources[0x1d]	26189	1			T1	9		T2	3		T3	7
valid_sources[0x1e]	25929	1			T1	4		T2	3		T3	8
valid_sources[0x1f]	27029	1			T1	5		T3	41		T7	49
valid_sources[0x20]	26747	1			T1	7		T2	1		T3	35

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25338

1

T1

22

T2

1

T3

29

values[0x0]

all_enables

biggest_size

188481

1

T1

10

T2

16

T3

255

values[0x1]

all_enables

biggest_size

25073

1

T1

14

T2

1

T3

39

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1479124	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

234000

1

T1

23

T2

32

T3

302

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	582308	1			T1	145		T2	70		T3	742
values[0x0]	548767	1			T1	23		T2	63		T3	778
values[0x1]	582049	1			T1	164		T2	59		T3	764

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1142902	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

570222

1

T1

124

T2

79

T3

765

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27183	1			T1	2		T2	2		T3	13
valid_sources[0x01]	26997	1			T1	1		T2	2		T3	44
valid_sources[0x02]	26963	1			T1	4		T2	1		T7	24
valid_sources[0x03]	27207	1			T1	7		T2	4		T3	31
valid_sources[0x04]	27146	1			T1	4		T2	2		T7	72
valid_sources[0x05]	27389	1			T1	3		T3	61		T7	42
valid_sources[0x06]	27082	1			T1	9		T2	7		T3	19
valid_sources[0x07]	26470	1			T1	5		T2	3		T3	50
valid_sources[0x08]	26660	1			T1	4		T2	5		T3	52
valid_sources[0x09]	26837	1			T1	3		T2	4		T3	90
valid_sources[0x0a]	26115	1			T1	6		T3	17		T7	41
valid_sources[0x0b]	26871	1			T1	4		T2	1		T3	24
valid_sources[0x0c]	26492	1			T1	3		T2	3		T3	17
valid_sources[0x0d]	27123	1			T1	5		T3	29		T7	42
valid_sources[0x0e]	27093	1			T1	6		T2	2		T3	31
valid_sources[0x0f]	26641	1			T1	6		T2	3		T3	54
valid_sources[0x10]	26752	1			T1	5		T2	3		T3	47
valid_sources[0x11]	26570	1			T1	6		T2	2		T3	17
valid_sources[0x12]	25712	1			T1	2		T2	6		T3	17
valid_sources[0x13]	26960	1			T1	3		T3	32		T7	33
valid_sources[0x14]	26922	1			T1	9		T2	1		T3	54
valid_sources[0x15]	26804	1			T1	6		T2	1		T3	14
valid_sources[0x16]	26152	1			T1	3		T2	3		T3	48
valid_sources[0x17]	26572	1			T1	7		T2	6		T3	30
valid_sources[0x18]	26915	1			T1	7		T2	5		T3	32
valid_sources[0x19]	27154	1			T1	5		T2	9		T3	5
valid_sources[0x1a]	27191	1			T1	5		T3	10		T7	26
valid_sources[0x1b]	26860	1			T1	4		T2	2		T3	80
valid_sources[0x1c]	26877	1			T1	8		T2	3		T3	51
valid_sources[0x1d]	27049	1			T1	7		T3	15		T7	33
valid_sources[0x1e]	26044	1			T1	2		T2	2		T3	15
valid_sources[0x1f]	26478	1			T1	3		T2	7		T3	34
valid_sources[0x20]	26799	1			T1	6		T2	2		T3	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24722

1

T1

8

T2

5

T3

37

values[0x0]

all_enables

biggest_size

184495

1

T1

9

T2

23

T3

238

values[0x1]

all_enables

biggest_size

24783

1

T1

6

T2

4

T3

27