Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7785978	0	0
GntImpliesValid_A	2147483647	7785978	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7785978	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	480047679	0	0
ReadyAndValidImplyGrant_A	2147483647	7785978	0	0
ReqAndReadyImplyGrant_A	2147483647	7785978	0	0
ReqImpliesValid_A	2147483647	35876447	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	46772	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7785978	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	974616	972696	0	0
T2	7836912	7835616	0	0
T3	2953728	2952720	0	0
T7	5501496	5501448	0	0
T8	4134792	4134648	0	0
T9	1478472	1477752	0	0
T10	6169272	6169104	0	0
T11	56520	55680	0	0
T12	320568	319200	0	0
T13	249624	249072	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7785978	0	0
T1	974616	20649	0	0
T2	7836912	454	0	0
T3	2953728	6810	0	0
T7	5501496	8230	0	0
T8	4134792	4272	0	0
T9	1478472	5882	0	0
T10	6169272	5774	0	0
T11	56520	556	0	0
T12	320568	498	0	0
T13	249624	445	0	0
T14	0	1406	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7785978	0	0
T1	974616	20649	0	0
T2	7836912	454	0	0
T3	2953728	6810	0	0
T7	5501496	8230	0	0
T8	4134792	4272	0	0
T9	1478472	5882	0	0
T10	6169272	5774	0	0
T11	56520	556	0	0
T12	320568	498	0	0
T13	249624	445	0	0
T14	0	1406	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	974616	972696	0	0
T2	7836912	7835616	0	0
T3	2953728	2952720	0	0
T7	5501496	5501448	0	0
T8	4134792	4134648	0	0
T9	1478472	1477752	0	0
T10	6169272	6169104	0	0
T11	56520	55680	0	0
T12	320568	319200	0	0
T13	249624	249072	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	974616	972696	0	0
T2	7836912	7835616	0	0
T3	2953728	2952720	0	0
T7	5501496	5501448	0	0
T8	4134792	4134648	0	0
T9	1478472	1477752	0	0
T10	6169272	6169104	0	0
T11	56520	55680	0	0
T12	320568	319200	0	0
T13	249624	249072	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7785978	0	0
T1	974616	20649	0	0
T2	7836912	454	0	0
T3	2953728	6810	0	0
T7	5501496	8230	0	0
T8	4134792	4272	0	0
T9	1478472	5882	0	0
T10	6169272	5774	0	0
T11	56520	556	0	0
T12	320568	498	0	0
T13	249624	445	0	0
T14	0	1406	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	480047679	0	0
T1	974616	24518	0	0
T2	7836912	274332	0	0
T3	2953728	155665	0	0
T7	5501496	221250	0	0
T8	4134792	159289	0	0
T9	1478472	94879	0	0
T10	6169272	2031300	0	0
T11	56520	686	0	0
T12	320568	16167	0	0
T13	249624	12666	0	0
T14	0	5168	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7785978	0	0
T1	974616	20649	0	0
T2	7836912	454	0	0
T3	2953728	6810	0	0
T7	5501496	8230	0	0
T8	4134792	4272	0	0
T9	1478472	5882	0	0
T10	6169272	5774	0	0
T11	56520	556	0	0
T12	320568	498	0	0
T13	249624	445	0	0
T14	0	1406	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7785978	0	0
T1	974616	20649	0	0
T2	7836912	454	0	0
T3	2953728	6810	0	0
T7	5501496	8230	0	0
T8	4134792	4272	0	0
T9	1478472	5882	0	0
T10	6169272	5774	0	0
T11	56520	556	0	0
T12	320568	498	0	0
T13	249624	445	0	0
T14	0	1406	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35876447	0	0
T1	974616	28338	0	0
T2	7836912	780	0	0
T3	2953728	12458	0	0
T7	5501496	13486	0	0
T8	4134792	10046	0	0
T9	1478472	13981	0	0
T10	6169272	399106	0	0
T11	56520	632	0	0
T12	320568	1003	0	0
T13	249624	859	0	0
T14	0	1998	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46772	0	21600
T1	81218	228	0	2
T2	653076	0	0	2
T3	246144	0	0	2
T7	458458	0	0	2
T8	344566	0	0	2
T9	123206	2	0	2
T10	514106	0	0	2
T11	4710	0	0	2
T12	26714	0	0	2
T13	20802	0	0	2
T14	0	1	0	0
T15	0	9	0	0
T16	0	7	0	0
T17	0	1	0	0
T18	0	16	0	0
T19	0	431	0	0
T20	0	3	0	0
T21	0	12	0	0
T22	0	1018	0	0
T23	0	9	0	0
T24	0	3	0	0
T25	0	8	0	0
T26	0	34	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	974616	972696	0	0
T2	7836912	7835616	0	0
T3	2953728	2952720	0	0
T7	5501496	5501448	0	0
T8	4134792	4134648	0	0
T9	1478472	1477752	0	0
T10	6169272	6169104	0	0
T11	56520	55680	0	0
T12	320568	319200	0	0
T13	249624	249072	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7785978	0	0
T1	974616	20649	0	0
T2	7836912	454	0	0
T3	2953728	6810	0	0
T7	5501496	8230	0	0
T8	4134792	4272	0	0
T9	1478472	5882	0	0
T10	6169272	5774	0	0
T11	56520	556	0	0
T12	320568	498	0	0
T13	249624	445	0	0
T14	0	1406	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	862090	0	0
GntImpliesValid_A	435308823	862090	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	862090	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	13283356	0	0
ReadyAndValidImplyGrant_A	435308823	862090	0	0
ReqAndReadyImplyGrant_A	435308823	862090	0	0
ReqImpliesValid_A	435308823	2510698	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	862090	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	862090	0	0
T1	40609	2040	0	0
T2	326538	48	0	0
T3	123072	741	0	0
T7	229229	930	0	0
T8	172283	335	0	0
T9	61603	672	0	0
T10	257053	645	0	0
T11	2355	67	0	0
T12	13357	50	0	0
T13	10401	60	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	862090	0	0
T1	40609	2040	0	0
T2	326538	48	0	0
T3	123072	741	0	0
T7	229229	930	0	0
T8	172283	335	0	0
T9	61603	672	0	0
T10	257053	645	0	0
T11	2355	67	0	0
T12	13357	50	0	0
T13	10401	60	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	862090	0	0
T1	40609	2040	0	0
T2	326538	48	0	0
T3	123072	741	0	0
T7	229229	930	0	0
T8	172283	335	0	0
T9	61603	672	0	0
T10	257053	645	0	0
T11	2355	67	0	0
T12	13357	50	0	0
T13	10401	60	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	13283356	0	0
T1	40609	1596	0	0
T2	326538	208	0	0
T3	123072	5355	0	0
T7	229229	3746	0	0
T8	172283	1454	0	0
T9	61603	5166	0	0
T10	257053	215667	0	0
T11	2355	54	0	0
T12	13357	361	0	0
T13	10401	490	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	862090	0	0
T1	40609	2040	0	0
T2	326538	48	0	0
T3	123072	741	0	0
T7	229229	930	0	0
T8	172283	335	0	0
T9	61603	672	0	0
T10	257053	645	0	0
T11	2355	67	0	0
T12	13357	50	0	0
T13	10401	60	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	862090	0	0
T1	40609	2040	0	0
T2	326538	48	0	0
T3	123072	741	0	0
T7	229229	930	0	0
T8	172283	335	0	0
T9	61603	672	0	0
T10	257053	645	0	0
T11	2355	67	0	0
T12	13357	50	0	0
T13	10401	60	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	2510698	0	0
T1	40609	2487	0	0
T2	326538	74	0	0
T3	123072	829	0	0
T7	229229	1274	0	0
T8	172283	460	0	0
T9	61603	1199	0	0
T10	257053	24319	0	0
T11	2355	81	0	0
T12	13357	62	0	0
T13	10401	101	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	862090	0	0
T1	40609	2040	0	0
T2	326538	48	0	0
T3	123072	741	0	0
T7	229229	930	0	0
T8	172283	335	0	0
T9	61603	672	0	0
T10	257053	645	0	0
T11	2355	67	0	0
T12	13357	50	0	0
T13	10401	60	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	865587	0	0
GntImpliesValid_A	435308823	865587	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	865587	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	13184862	0	0
ReadyAndValidImplyGrant_A	435308823	865587	0	0
ReqAndReadyImplyGrant_A	435308823	865587	0	0
ReqImpliesValid_A	435308823	2574983	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	865587	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	865587	0	0
T1	40609	1959	0	0
T2	326538	62	0	0
T3	123072	755	0	0
T7	229229	909	0	0
T8	172283	351	0	0
T9	61603	680	0	0
T10	257053	631	0	0
T11	2355	71	0	0
T12	13357	54	0	0
T13	10401	42	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	865587	0	0
T1	40609	1959	0	0
T2	326538	62	0	0
T3	123072	755	0	0
T7	229229	909	0	0
T8	172283	351	0	0
T9	61603	680	0	0
T10	257053	631	0	0
T11	2355	71	0	0
T12	13357	54	0	0
T13	10401	42	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	865587	0	0
T1	40609	1959	0	0
T2	326538	62	0	0
T3	123072	755	0	0
T7	229229	909	0	0
T8	172283	351	0	0
T9	61603	680	0	0
T10	257053	631	0	0
T11	2355	71	0	0
T12	13357	54	0	0
T13	10401	42	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	13184862	0	0
T1	40609	1568	0	0
T2	326538	271	0	0
T3	123072	5803	0	0
T7	229229	3653	0	0
T8	172283	1462	0	0
T9	61603	4602	0	0
T10	257053	168904	0	0
T11	2355	54	0	0
T12	13357	473	0	0
T13	10401	348	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	865587	0	0
T1	40609	1959	0	0
T2	326538	62	0	0
T3	123072	755	0	0
T7	229229	909	0	0
T8	172283	351	0	0
T9	61603	680	0	0
T10	257053	631	0	0
T11	2355	71	0	0
T12	13357	54	0	0
T13	10401	42	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	865587	0	0
T1	40609	1959	0	0
T2	326538	62	0	0
T3	123072	755	0	0
T7	229229	909	0	0
T8	172283	351	0	0
T9	61603	680	0	0
T10	257053	631	0	0
T11	2355	71	0	0
T12	13357	54	0	0
T13	10401	42	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	2574983	0	0
T1	40609	2353	0	0
T2	326538	89	0	0
T3	123072	878	0	0
T7	229229	1238	0	0
T8	172283	469	0	0
T9	61603	1188	0	0
T10	257053	23172	0	0
T11	2355	89	0	0
T12	13357	103	0	0
T13	10401	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	865587	0	0
T1	40609	1959	0	0
T2	326538	62	0	0
T3	123072	755	0	0
T7	229229	909	0	0
T8	172283	351	0	0
T9	61603	680	0	0
T10	257053	631	0	0
T11	2355	71	0	0
T12	13357	54	0	0
T13	10401	42	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	232858	0	0
GntImpliesValid_A	435308823	232858	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	232858	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	3320969	0	0
ReadyAndValidImplyGrant_A	435308823	232858	0	0
ReqAndReadyImplyGrant_A	435308823	232858	0	0
ReqImpliesValid_A	435308823	604083	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	232858	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	232858	0	0
T1	40609	368	0	0
T2	326538	12	0	0
T3	123072	185	0	0
T7	229229	217	0	0
T8	172283	0	0	0
T9	61603	186	0	0
T10	257053	166	0	0
T11	2355	18	0	0
T12	13357	10	0	0
T13	10401	12	0	0
T14	0	103	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	232858	0	0
T1	40609	368	0	0
T2	326538	12	0	0
T3	123072	185	0	0
T7	229229	217	0	0
T8	172283	0	0	0
T9	61603	186	0	0
T10	257053	166	0	0
T11	2355	18	0	0
T12	13357	10	0	0
T13	10401	12	0	0
T14	0	103	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	232858	0	0
T1	40609	368	0	0
T2	326538	12	0	0
T3	123072	185	0	0
T7	229229	217	0	0
T8	172283	0	0	0
T9	61603	186	0	0
T10	257053	166	0	0
T11	2355	18	0	0
T12	13357	10	0	0
T13	10401	12	0	0
T14	0	103	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	3320969	0	0
T1	40609	365	0	0
T2	326538	53	0	0
T3	123072	1446	0	0
T7	229229	901	0	0
T8	172283	1	0	0
T9	61603	1448	0	0
T10	257053	53613	0	0
T11	2355	18	0	0
T12	13357	72	0	0
T13	10401	117	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	232858	0	0
T1	40609	368	0	0
T2	326538	12	0	0
T3	123072	185	0	0
T7	229229	217	0	0
T8	172283	0	0	0
T9	61603	186	0	0
T10	257053	166	0	0
T11	2355	18	0	0
T12	13357	10	0	0
T13	10401	12	0	0
T14	0	103	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	232858	0	0
T1	40609	368	0	0
T2	326538	12	0	0
T3	123072	185	0	0
T7	229229	217	0	0
T8	172283	0	0	0
T9	61603	186	0	0
T10	257053	166	0	0
T11	2355	18	0	0
T12	13357	10	0	0
T13	10401	12	0	0
T14	0	103	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	604083	0	0
T1	40609	374	0	0
T2	326538	15	0	0
T3	123072	194	0	0
T7	229229	253	0	0
T8	172283	0	0	0
T9	61603	297	0	0
T10	257053	5132	0	0
T11	2355	19	0	0
T12	13357	10	0	0
T13	10401	12	0	0
T14	0	136	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	232858	0	0
T1	40609	368	0	0
T2	326538	12	0	0
T3	123072	185	0	0
T7	229229	217	0	0
T8	172283	0	0	0
T9	61603	186	0	0
T10	257053	166	0	0
T11	2355	18	0	0
T12	13357	10	0	0
T13	10401	12	0	0
T14	0	103	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	217948	0	0
GntImpliesValid_A	435308823	217948	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	217948	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	3286198	0	0
ReadyAndValidImplyGrant_A	435308823	217948	0	0
ReqAndReadyImplyGrant_A	435308823	217948	0	0
ReqImpliesValid_A	435308823	594296	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	217948	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	217948	0	0
T1	40609	357	0	0
T2	326538	9	0	0
T3	123072	228	0	0
T7	229229	224	0	0
T8	172283	453	0	0
T9	61603	169	0	0
T10	257053	169	0	0
T11	2355	13	0	0
T12	13357	11	0	0
T13	10401	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	217948	0	0
T1	40609	357	0	0
T2	326538	9	0	0
T3	123072	228	0	0
T7	229229	224	0	0
T8	172283	453	0	0
T9	61603	169	0	0
T10	257053	169	0	0
T11	2355	13	0	0
T12	13357	11	0	0
T13	10401	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	217948	0	0
T1	40609	357	0	0
T2	326538	9	0	0
T3	123072	228	0	0
T7	229229	224	0	0
T8	172283	453	0	0
T9	61603	169	0	0
T10	257053	169	0	0
T11	2355	13	0	0
T12	13357	11	0	0
T13	10401	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	3286198	0	0
T1	40609	356	0	0
T2	326538	47	0	0
T3	123072	1672	0	0
T7	229229	1016	0	0
T8	172283	1538	0	0
T9	61603	1237	0	0
T10	257053	57744	0	0
T11	2355	14	0	0
T12	13357	98	0	0
T13	10401	121	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	217948	0	0
T1	40609	357	0	0
T2	326538	9	0	0
T3	123072	228	0	0
T7	229229	224	0	0
T8	172283	453	0	0
T9	61603	169	0	0
T10	257053	169	0	0
T11	2355	13	0	0
T12	13357	11	0	0
T13	10401	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	217948	0	0
T1	40609	357	0	0
T2	326538	9	0	0
T3	123072	228	0	0
T7	229229	224	0	0
T8	172283	453	0	0
T9	61603	169	0	0
T10	257053	169	0	0
T11	2355	13	0	0
T12	13357	11	0	0
T13	10401	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	594296	0	0
T1	40609	361	0	0
T2	326538	16	0	0
T3	123072	234	0	0
T7	229229	269	0	0
T8	172283	1036	0	0
T9	61603	235	0	0
T10	257053	3056	0	0
T11	2355	13	0	0
T12	13357	13	0	0
T13	10401	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	217948	0	0
T1	40609	357	0	0
T2	326538	9	0	0
T3	123072	228	0	0
T7	229229	224	0	0
T8	172283	453	0	0
T9	61603	169	0	0
T10	257053	169	0	0
T11	2355	13	0	0
T12	13357	11	0	0
T13	10401	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	209409	0	0
GntImpliesValid_A	435308823	209409	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	209409	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	5443074	0	0
ReadyAndValidImplyGrant_A	435308823	209409	0	0
ReqAndReadyImplyGrant_A	435308823	209409	0	0
ReqImpliesValid_A	435308823	1270625	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	209409	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	209409	0	0
T1	40609	341	0	0
T2	326538	15	0	0
T3	123072	168	0	0
T7	229229	217	0	0
T8	172283	418	0	0
T9	61603	148	0	0
T10	257053	165	0	0
T11	2355	14	0	0
T12	13357	15	0	0
T13	10401	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	209409	0	0
T1	40609	341	0	0
T2	326538	15	0	0
T3	123072	168	0	0
T7	229229	217	0	0
T8	172283	418	0	0
T9	61603	148	0	0
T10	257053	165	0	0
T11	2355	14	0	0
T12	13357	15	0	0
T13	10401	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	209409	0	0
T1	40609	341	0	0
T2	326538	15	0	0
T3	123072	168	0	0
T7	229229	217	0	0
T8	172283	418	0	0
T9	61603	148	0	0
T10	257053	165	0	0
T11	2355	14	0	0
T12	13357	15	0	0
T13	10401	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	5443074	0	0
T1	40609	1346	0	0
T2	326538	97	0	0
T3	123072	2403	0	0
T7	229229	1067	0	0
T8	172283	3355	0	0
T9	61603	1320	0	0
T10	257053	95711	0	0
T11	2355	49	0	0
T12	13357	243	0	0
T13	10401	162	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	209409	0	0
T1	40609	341	0	0
T2	326538	15	0	0
T3	123072	168	0	0
T7	229229	217	0	0
T8	172283	418	0	0
T9	61603	148	0	0
T10	257053	165	0	0
T11	2355	14	0	0
T12	13357	15	0	0
T13	10401	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	209409	0	0
T1	40609	341	0	0
T2	326538	15	0	0
T3	123072	168	0	0
T7	229229	217	0	0
T8	172283	418	0	0
T9	61603	148	0	0
T10	257053	165	0	0
T11	2355	14	0	0
T12	13357	15	0	0
T13	10401	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	1270625	0	0
T1	40609	380	0	0
T2	326538	31	0	0
T3	123072	179	0	0
T7	229229	252	0	0
T8	172283	1827	0	0
T9	61603	163	0	0
T10	257053	6997	0	0
T11	2355	18	0	0
T12	13357	17	0	0
T13	10401	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	209409	0	0
T1	40609	341	0	0
T2	326538	15	0	0
T3	123072	168	0	0
T7	229229	217	0	0
T8	172283	418	0	0
T9	61603	148	0	0
T10	257053	165	0	0
T11	2355	14	0	0
T12	13357	15	0	0
T13	10401	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	203517	0	0
GntImpliesValid_A	435308823	203517	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	203517	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	5972648	0	0
ReadyAndValidImplyGrant_A	435308823	203517	0	0
ReqAndReadyImplyGrant_A	435308823	203517	0	0
ReqImpliesValid_A	435308823	1148481	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	203517	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	203517	0	0
T1	40609	317	0	0
T2	326538	10	0	0
T3	123072	159	0	0
T7	229229	240	0	0
T8	172283	0	0	0
T9	61603	156	0	0
T10	257053	169	0	0
T11	2355	18	0	0
T12	13357	16	0	0
T13	10401	9	0	0
T14	0	96	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	203517	0	0
T1	40609	317	0	0
T2	326538	10	0	0
T3	123072	159	0	0
T7	229229	240	0	0
T8	172283	0	0	0
T9	61603	156	0	0
T10	257053	169	0	0
T11	2355	18	0	0
T12	13357	16	0	0
T13	10401	9	0	0
T14	0	96	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	203517	0	0
T1	40609	317	0	0
T2	326538	10	0	0
T3	123072	159	0	0
T7	229229	240	0	0
T8	172283	0	0	0
T9	61603	156	0	0
T10	257053	169	0	0
T11	2355	18	0	0
T12	13357	16	0	0
T13	10401	9	0	0
T14	0	96	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	5972648	0	0
T1	40609	1384	0	0
T2	326538	282	0	0
T3	123072	3028	0	0
T7	229229	1297	0	0
T8	172283	0	0	0
T9	61603	1509	0	0
T10	257053	60640	0	0
T11	2355	92	0	0
T12	13357	284	0	0
T13	10401	72	0	0
T14	0	2513	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	203517	0	0
T1	40609	317	0	0
T2	326538	10	0	0
T3	123072	159	0	0
T7	229229	240	0	0
T8	172283	0	0	0
T9	61603	156	0	0
T10	257053	169	0	0
T11	2355	18	0	0
T12	13357	16	0	0
T13	10401	9	0	0
T14	0	96	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	203517	0	0
T1	40609	317	0	0
T2	326538	10	0	0
T3	123072	159	0	0
T7	229229	240	0	0
T8	172283	0	0	0
T9	61603	156	0	0
T10	257053	169	0	0
T11	2355	18	0	0
T12	13357	16	0	0
T13	10401	9	0	0
T14	0	96	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	1148481	0	0
T1	40609	376	0	0
T2	326538	79	0	0
T3	123072	170	0	0
T7	229229	294	0	0
T8	172283	0	0	0
T9	61603	209	0	0
T10	257053	4639	0	0
T11	2355	29	0	0
T12	13357	26	0	0
T13	10401	9	0	0
T14	0	179	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	203517	0	0
T1	40609	317	0	0
T2	326538	10	0	0
T3	123072	159	0	0
T7	229229	240	0	0
T8	172283	0	0	0
T9	61603	156	0	0
T10	257053	169	0	0
T11	2355	18	0	0
T12	13357	16	0	0
T13	10401	9	0	0
T14	0	96	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	217816	0	0
GntImpliesValid_A	435308823	217816	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	217816	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	5204703	0	0
ReadyAndValidImplyGrant_A	435308823	217816	0	0
ReqAndReadyImplyGrant_A	435308823	217816	0	0
ReqImpliesValid_A	435308823	1167577	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	217816	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	217816	0	0
T1	40609	1272	0	0
T2	326538	16	0	0
T3	123072	186	0	0
T7	229229	241	0	0
T8	172283	0	0	0
T9	61603	150	0	0
T10	257053	177	0	0
T11	2355	20	0	0
T12	13357	12	0	0
T13	10401	17	0	0
T14	0	85	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	217816	0	0
T1	40609	1272	0	0
T2	326538	16	0	0
T3	123072	186	0	0
T7	229229	241	0	0
T8	172283	0	0	0
T9	61603	150	0	0
T10	257053	177	0	0
T11	2355	20	0	0
T12	13357	12	0	0
T13	10401	17	0	0
T14	0	85	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	217816	0	0
T1	40609	1272	0	0
T2	326538	16	0	0
T3	123072	186	0	0
T7	229229	241	0	0
T8	172283	0	0	0
T9	61603	150	0	0
T10	257053	177	0	0
T11	2355	20	0	0
T12	13357	12	0	0
T13	10401	17	0	0
T14	0	85	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	5204703	0	0
T1	40609	7497	0	0
T2	326538	193	0	0
T3	123072	3771	0	0
T7	229229	1464	0	0
T8	172283	0	0	0
T9	61603	2269	0	0
T10	257053	148119	0	0
T11	2355	107	0	0
T12	13357	102	0	0
T13	10401	558	0	0
T14	0	2040	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	217816	0	0
T1	40609	1272	0	0
T2	326538	16	0	0
T3	123072	186	0	0
T7	229229	241	0	0
T8	172283	0	0	0
T9	61603	150	0	0
T10	257053	177	0	0
T11	2355	20	0	0
T12	13357	12	0	0
T13	10401	17	0	0
T14	0	85	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	217816	0	0
T1	40609	1272	0	0
T2	326538	16	0	0
T3	123072	186	0	0
T7	229229	241	0	0
T8	172283	0	0	0
T9	61603	150	0	0
T10	257053	177	0	0
T11	2355	20	0	0
T12	13357	12	0	0
T13	10401	17	0	0
T14	0	85	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	1167577	0	0
T1	40609	5097	0	0
T2	326538	41	0	0
T3	123072	267	0	0
T7	229229	320	0	0
T8	172283	0	0	0
T9	61603	304	0	0
T10	257053	16124	0	0
T11	2355	29	0	0
T12	13357	31	0	0
T13	10401	35	0	0
T14	0	207	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	217816	0	0
T1	40609	1272	0	0
T2	326538	16	0	0
T3	123072	186	0	0
T7	229229	241	0	0
T8	172283	0	0	0
T9	61603	150	0	0
T10	257053	177	0	0
T11	2355	20	0	0
T12	13357	12	0	0
T13	10401	17	0	0
T14	0	85	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	209075	0	0
GntImpliesValid_A	435308823	209075	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	209075	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	5428704	0	0
ReadyAndValidImplyGrant_A	435308823	209075	0	0
ReqAndReadyImplyGrant_A	435308823	209075	0	0
ReqImpliesValid_A	435308823	1115746	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	209075	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	209075	0	0
T1	40609	900	0	0
T2	326538	16	0	0
T3	123072	174	0	0
T7	229229	237	0	0
T8	172283	0	0	0
T9	61603	157	0	0
T10	257053	157	0	0
T11	2355	16	0	0
T12	13357	14	0	0
T13	10401	7	0	0
T14	0	85	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	209075	0	0
T1	40609	900	0	0
T2	326538	16	0	0
T3	123072	174	0	0
T7	229229	237	0	0
T8	172283	0	0	0
T9	61603	157	0	0
T10	257053	157	0	0
T11	2355	16	0	0
T12	13357	14	0	0
T13	10401	7	0	0
T14	0	85	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	209075	0	0
T1	40609	900	0	0
T2	326538	16	0	0
T3	123072	174	0	0
T7	229229	237	0	0
T8	172283	0	0	0
T9	61603	157	0	0
T10	257053	157	0	0
T11	2355	16	0	0
T12	13357	14	0	0
T13	10401	7	0	0
T14	0	85	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	5428704	0	0
T1	40609	3151	0	0
T2	326538	131	0	0
T3	123072	2289	0	0
T7	229229	1150	0	0
T8	172283	0	0	0
T9	61603	6748	0	0
T10	257053	75350	0	0
T11	2355	70	0	0
T12	13357	832	0	0
T13	10401	39	0	0
T14	0	615	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	209075	0	0
T1	40609	900	0	0
T2	326538	16	0	0
T3	123072	174	0	0
T7	229229	237	0	0
T8	172283	0	0	0
T9	61603	157	0	0
T10	257053	157	0	0
T11	2355	16	0	0
T12	13357	14	0	0
T13	10401	7	0	0
T14	0	85	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	209075	0	0
T1	40609	900	0	0
T2	326538	16	0	0
T3	123072	174	0	0
T7	229229	237	0	0
T8	172283	0	0	0
T9	61603	157	0	0
T10	257053	157	0	0
T11	2355	16	0	0
T12	13357	14	0	0
T13	10401	7	0	0
T14	0	85	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	1115746	0	0
T1	40609	2739	0	0
T2	326538	16	0	0
T3	123072	192	0	0
T7	229229	302	0	0
T8	172283	0	0	0
T9	61603	818	0	0
T10	257053	6384	0	0
T11	2355	25	0	0
T12	13357	14	0	0
T13	10401	13	0	0
T14	0	136	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	209075	0	0
T1	40609	900	0	0
T2	326538	16	0	0
T3	123072	174	0	0
T7	229229	237	0	0
T8	172283	0	0	0
T9	61603	157	0	0
T10	257053	157	0	0
T11	2355	16	0	0
T12	13357	14	0	0
T13	10401	7	0	0
T14	0	85	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	217577	0	0
GntImpliesValid_A	435308823	217577	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	217577	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	3282323	0	0
ReadyAndValidImplyGrant_A	435308823	217577	0	0
ReqAndReadyImplyGrant_A	435308823	217577	0	0
ReqImpliesValid_A	435308823	590917	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	217577	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	217577	0	0
T1	40609	804	0	0
T2	326538	14	0	0
T3	123072	204	0	0
T7	229229	206	0	0
T8	172283	0	0	0
T9	61603	155	0	0
T10	257053	163	0	0
T11	2355	13	0	0
T12	13357	13	0	0
T13	10401	15	0	0
T14	0	98	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	217577	0	0
T1	40609	804	0	0
T2	326538	14	0	0
T3	123072	204	0	0
T7	229229	206	0	0
T8	172283	0	0	0
T9	61603	155	0	0
T10	257053	163	0	0
T11	2355	13	0	0
T12	13357	13	0	0
T13	10401	15	0	0
T14	0	98	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	217577	0	0
T1	40609	804	0	0
T2	326538	14	0	0
T3	123072	204	0	0
T7	229229	206	0	0
T8	172283	0	0	0
T9	61603	155	0	0
T10	257053	163	0	0
T11	2355	13	0	0
T12	13357	13	0	0
T13	10401	15	0	0
T14	0	98	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	3282323	0	0
T1	40609	647	0	0
T2	326538	51	0	0
T3	123072	1658	0	0
T7	229229	829	0	0
T8	172283	1	0	0
T9	61603	1187	0	0
T10	257053	54425	0	0
T11	2355	13	0	0
T12	13357	74	0	0
T13	10401	106	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	217577	0	0
T1	40609	804	0	0
T2	326538	14	0	0
T3	123072	204	0	0
T7	229229	206	0	0
T8	172283	0	0	0
T9	61603	155	0	0
T10	257053	163	0	0
T11	2355	13	0	0
T12	13357	13	0	0
T13	10401	15	0	0
T14	0	98	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	217577	0	0
T1	40609	804	0	0
T2	326538	14	0	0
T3	123072	204	0	0
T7	229229	206	0	0
T8	172283	0	0	0
T9	61603	155	0	0
T10	257053	163	0	0
T11	2355	13	0	0
T12	13357	13	0	0
T13	10401	15	0	0
T14	0	98	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	590917	0	0
T1	40609	964	0	0
T2	326538	14	0	0
T3	123072	204	0	0
T7	229229	231	0	0
T8	172283	0	0	0
T9	61603	247	0	0
T10	257053	4923	0	0
T11	2355	14	0	0
T12	13357	13	0	0
T13	10401	22	0	0
T14	0	135	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	217577	0	0
T1	40609	804	0	0
T2	326538	14	0	0
T3	123072	204	0	0
T7	229229	206	0	0
T8	172283	0	0	0
T9	61603	155	0	0
T10	257053	163	0	0
T11	2355	13	0	0
T12	13357	13	0	0
T13	10401	15	0	0
T14	0	98	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	222889	0	0
GntImpliesValid_A	435308823	222889	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	222889	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	3300874	0	0
ReadyAndValidImplyGrant_A	435308823	222889	0	0
ReqAndReadyImplyGrant_A	435308823	222889	0	0
ReqImpliesValid_A	435308823	568747	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	222889	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	222889	0	0
T1	40609	790	0	0
T2	326538	17	0	0
T3	123072	186	0	0
T7	229229	248	0	0
T8	172283	516	0	0
T9	61603	153	0	0
T10	257053	159	0	0
T11	2355	15	0	0
T12	13357	13	0	0
T13	10401	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	222889	0	0
T1	40609	790	0	0
T2	326538	17	0	0
T3	123072	186	0	0
T7	229229	248	0	0
T8	172283	516	0	0
T9	61603	153	0	0
T10	257053	159	0	0
T11	2355	15	0	0
T12	13357	13	0	0
T13	10401	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	222889	0	0
T1	40609	790	0	0
T2	326538	17	0	0
T3	123072	186	0	0
T7	229229	248	0	0
T8	172283	516	0	0
T9	61603	153	0	0
T10	257053	159	0	0
T11	2355	15	0	0
T12	13357	13	0	0
T13	10401	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	3300874	0	0
T1	40609	626	0	0
T2	326538	89	0	0
T3	123072	1515	0	0
T7	229229	1056	0	0
T8	172283	1958	0	0
T9	61603	1178	0	0
T10	257053	55154	0	0
T11	2355	15	0	0
T12	13357	121	0	0
T13	10401	55	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	222889	0	0
T1	40609	790	0	0
T2	326538	17	0	0
T3	123072	186	0	0
T7	229229	248	0	0
T8	172283	516	0	0
T9	61603	153	0	0
T10	257053	159	0	0
T11	2355	15	0	0
T12	13357	13	0	0
T13	10401	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	222889	0	0
T1	40609	790	0	0
T2	326538	17	0	0
T3	123072	186	0	0
T7	229229	248	0	0
T8	172283	516	0	0
T9	61603	153	0	0
T10	257053	159	0	0
T11	2355	15	0	0
T12	13357	13	0	0
T13	10401	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	568747	0	0
T1	40609	957	0	0
T2	326538	17	0	0
T3	123072	192	0	0
T7	229229	305	0	0
T8	172283	818	0	0
T9	61603	196	0	0
T10	257053	5101	0	0
T11	2355	16	0	0
T12	13357	13	0	0
T13	10401	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	222889	0	0
T1	40609	790	0	0
T2	326538	17	0	0
T3	123072	186	0	0
T7	229229	248	0	0
T8	172283	516	0	0
T9	61603	153	0	0
T10	257053	159	0	0
T11	2355	15	0	0
T12	13357	13	0	0
T13	10401	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	228666	0	0
GntImpliesValid_A	435308823	228666	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	228666	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	3332453	0	0
ReadyAndValidImplyGrant_A	435308823	228666	0	0
ReqAndReadyImplyGrant_A	435308823	228666	0	0
ReqImpliesValid_A	435308823	631928	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	228666	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	228666	0	0
T1	40609	316	0	0
T2	326538	18	0	0
T3	123072	193	0	0
T7	229229	246	0	0
T8	172283	492	0	0
T9	61603	174	0	0
T10	257053	151	0	0
T11	2355	17	0	0
T12	13357	10	0	0
T13	10401	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	228666	0	0
T1	40609	316	0	0
T2	326538	18	0	0
T3	123072	193	0	0
T7	229229	246	0	0
T8	172283	492	0	0
T9	61603	174	0	0
T10	257053	151	0	0
T11	2355	17	0	0
T12	13357	10	0	0
T13	10401	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	228666	0	0
T1	40609	316	0	0
T2	326538	18	0	0
T3	123072	193	0	0
T7	229229	246	0	0
T8	172283	492	0	0
T9	61603	174	0	0
T10	257053	151	0	0
T11	2355	17	0	0
T12	13357	10	0	0
T13	10401	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	3332453	0	0
T1	40609	317	0	0
T2	326538	60	0	0
T3	123072	1568	0	0
T7	229229	1033	0	0
T8	172283	1675	0	0
T9	61603	1372	0	0
T10	257053	44536	0	0
T11	2355	16	0	0
T12	13357	73	0	0
T13	10401	56	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	228666	0	0
T1	40609	316	0	0
T2	326538	18	0	0
T3	123072	193	0	0
T7	229229	246	0	0
T8	172283	492	0	0
T9	61603	174	0	0
T10	257053	151	0	0
T11	2355	17	0	0
T12	13357	10	0	0
T13	10401	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	228666	0	0
T1	40609	316	0	0
T2	326538	18	0	0
T3	123072	193	0	0
T7	229229	246	0	0
T8	172283	492	0	0
T9	61603	174	0	0
T10	257053	151	0	0
T11	2355	17	0	0
T12	13357	10	0	0
T13	10401	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	631928	0	0
T1	40609	318	0	0
T2	326538	22	0	0
T3	123072	195	0	0
T7	229229	304	0	0
T8	172283	1128	0	0
T9	61603	248	0	0
T10	257053	1592	0	0
T11	2355	19	0	0
T12	13357	10	0	0
T13	10401	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	228666	0	0
T1	40609	316	0	0
T2	326538	18	0	0
T3	123072	193	0	0
T7	229229	246	0	0
T8	172283	492	0	0
T9	61603	174	0	0
T10	257053	151	0	0
T11	2355	17	0	0
T12	13357	10	0	0
T13	10401	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	223495	0	0
GntImpliesValid_A	435308823	223495	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	223495	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	3246941	0	0
ReadyAndValidImplyGrant_A	435308823	223495	0	0
ReqAndReadyImplyGrant_A	435308823	223495	0	0
ReqImpliesValid_A	435308823	594285	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	223495	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	223495	0	0
T1	40609	319	0	0
T2	326538	19	0	0
T3	123072	192	0	0
T7	229229	211	0	0
T8	172283	0	0	0
T9	61603	179	0	0
T10	257053	158	0	0
T11	2355	19	0	0
T12	13357	14	0	0
T13	10401	18	0	0
T14	0	87	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	223495	0	0
T1	40609	319	0	0
T2	326538	19	0	0
T3	123072	192	0	0
T7	229229	211	0	0
T8	172283	0	0	0
T9	61603	179	0	0
T10	257053	158	0	0
T11	2355	19	0	0
T12	13357	14	0	0
T13	10401	18	0	0
T14	0	87	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	223495	0	0
T1	40609	319	0	0
T2	326538	19	0	0
T3	123072	192	0	0
T7	229229	211	0	0
T8	172283	0	0	0
T9	61603	179	0	0
T10	257053	158	0	0
T11	2355	19	0	0
T12	13357	14	0	0
T13	10401	18	0	0
T14	0	87	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	3246941	0	0
T1	40609	316	0	0
T2	326538	85	0	0
T3	123072	1561	0	0
T7	229229	917	0	0
T8	172283	1	0	0
T9	61603	1377	0	0
T10	257053	50421	0	0
T11	2355	19	0	0
T12	13357	94	0	0
T13	10401	89	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	223495	0	0
T1	40609	319	0	0
T2	326538	19	0	0
T3	123072	192	0	0
T7	229229	211	0	0
T8	172283	0	0	0
T9	61603	179	0	0
T10	257053	158	0	0
T11	2355	19	0	0
T12	13357	14	0	0
T13	10401	18	0	0
T14	0	87	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	223495	0	0
T1	40609	319	0	0
T2	326538	19	0	0
T3	123072	192	0	0
T7	229229	211	0	0
T8	172283	0	0	0
T9	61603	179	0	0
T10	257053	158	0	0
T11	2355	19	0	0
T12	13357	14	0	0
T13	10401	18	0	0
T14	0	87	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	594285	0	0
T1	40609	325	0	0
T2	326538	32	0	0
T3	123072	197	0	0
T7	229229	284	0	0
T8	172283	0	0	0
T9	61603	249	0	0
T10	257053	838	0	0
T11	2355	20	0	0
T12	13357	32	0	0
T13	10401	18	0	0
T14	0	114	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	223495	0	0
T1	40609	319	0	0
T2	326538	19	0	0
T3	123072	192	0	0
T7	229229	211	0	0
T8	172283	0	0	0
T9	61603	179	0	0
T10	257053	158	0	0
T11	2355	19	0	0
T12	13357	14	0	0
T13	10401	18	0	0
T14	0	87	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	216407	0	0
GntImpliesValid_A	435308823	216407	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	216407	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	3267071	0	0
ReadyAndValidImplyGrant_A	435308823	216407	0	0
ReqAndReadyImplyGrant_A	435308823	216407	0	0
ReqImpliesValid_A	435308823	606486	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	216407	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	216407	0	0
T1	40609	377	0	0
T2	326538	10	0	0
T3	123072	194	0	0
T7	229229	257	0	0
T8	172283	464	0	0
T9	61603	152	0	0
T10	257053	169	0	0
T11	2355	18	0	0
T12	13357	15	0	0
T13	10401	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	216407	0	0
T1	40609	377	0	0
T2	326538	10	0	0
T3	123072	194	0	0
T7	229229	257	0	0
T8	172283	464	0	0
T9	61603	152	0	0
T10	257053	169	0	0
T11	2355	18	0	0
T12	13357	15	0	0
T13	10401	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	216407	0	0
T1	40609	377	0	0
T2	326538	10	0	0
T3	123072	194	0	0
T7	229229	257	0	0
T8	172283	464	0	0
T9	61603	152	0	0
T10	257053	169	0	0
T11	2355	18	0	0
T12	13357	15	0	0
T13	10401	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	3267071	0	0
T1	40609	371	0	0
T2	326538	49	0	0
T3	123072	1554	0	0
T7	229229	1020	0	0
T8	172283	1523	0	0
T9	61603	1138	0	0
T10	257053	58087	0	0
T11	2355	18	0	0
T12	13357	90	0	0
T13	10401	116	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	216407	0	0
T1	40609	377	0	0
T2	326538	10	0	0
T3	123072	194	0	0
T7	229229	257	0	0
T8	172283	464	0	0
T9	61603	152	0	0
T10	257053	169	0	0
T11	2355	18	0	0
T12	13357	15	0	0
T13	10401	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	216407	0	0
T1	40609	377	0	0
T2	326538	10	0	0
T3	123072	194	0	0
T7	229229	257	0	0
T8	172283	464	0	0
T9	61603	152	0	0
T10	257053	169	0	0
T11	2355	18	0	0
T12	13357	15	0	0
T13	10401	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	606486	0	0
T1	40609	386	0	0
T2	326538	10	0	0
T3	123072	196	0	0
T7	229229	363	0	0
T8	172283	1069	0	0
T9	61603	203	0	0
T10	257053	5418	0	0
T11	2355	19	0	0
T12	13357	15	0	0
T13	10401	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	216407	0	0
T1	40609	377	0	0
T2	326538	10	0	0
T3	123072	194	0	0
T7	229229	257	0	0
T8	172283	464	0	0
T9	61603	152	0	0
T10	257053	169	0	0
T11	2355	18	0	0
T12	13357	15	0	0
T13	10401	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	213630	0	0
GntImpliesValid_A	435308823	213630	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	213630	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	3336797	0	0
ReadyAndValidImplyGrant_A	435308823	213630	0	0
ReqAndReadyImplyGrant_A	435308823	213630	0	0
ReqImpliesValid_A	435308823	611297	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	213630	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	213630	0	0
T1	40609	350	0	0
T2	326538	8	0	0
T3	123072	212	0	0
T7	229229	230	0	0
T8	172283	0	0	0
T9	61603	142	0	0
T10	257053	163	0	0
T11	2355	15	0	0
T12	13357	16	0	0
T13	10401	12	0	0
T14	0	96	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	213630	0	0
T1	40609	350	0	0
T2	326538	8	0	0
T3	123072	212	0	0
T7	229229	230	0	0
T8	172283	0	0	0
T9	61603	142	0	0
T10	257053	163	0	0
T11	2355	15	0	0
T12	13357	16	0	0
T13	10401	12	0	0
T14	0	96	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	213630	0	0
T1	40609	350	0	0
T2	326538	8	0	0
T3	123072	212	0	0
T7	229229	230	0	0
T8	172283	0	0	0
T9	61603	142	0	0
T10	257053	163	0	0
T11	2355	15	0	0
T12	13357	16	0	0
T13	10401	12	0	0
T14	0	96	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	3336797	0	0
T1	40609	347	0	0
T2	326538	20	0	0
T3	123072	1694	0	0
T7	229229	937	0	0
T8	172283	1	0	0
T9	61603	1041	0	0
T10	257053	51175	0	0
T11	2355	16	0	0
T12	13357	112	0	0
T13	10401	105	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	213630	0	0
T1	40609	350	0	0
T2	326538	8	0	0
T3	123072	212	0	0
T7	229229	230	0	0
T8	172283	0	0	0
T9	61603	142	0	0
T10	257053	163	0	0
T11	2355	15	0	0
T12	13357	16	0	0
T13	10401	12	0	0
T14	0	96	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	213630	0	0
T1	40609	350	0	0
T2	326538	8	0	0
T3	123072	212	0	0
T7	229229	230	0	0
T8	172283	0	0	0
T9	61603	142	0	0
T10	257053	163	0	0
T11	2355	15	0	0
T12	13357	16	0	0
T13	10401	12	0	0
T14	0	96	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	611297	0	0
T1	40609	356	0	0
T2	326538	8	0	0
T3	123072	216	0	0
T7	229229	281	0	0
T8	172283	0	0	0
T9	61603	167	0	0
T10	257053	3918	0	0
T11	2355	15	0	0
T12	13357	16	0	0
T13	10401	12	0	0
T14	0	132	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	213630	0	0
T1	40609	350	0	0
T2	326538	8	0	0
T3	123072	212	0	0
T7	229229	230	0	0
T8	172283	0	0	0
T9	61603	142	0	0
T10	257053	163	0	0
T11	2355	15	0	0
T12	13357	16	0	0
T13	10401	12	0	0
T14	0	96	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	212686	0	0
GntImpliesValid_A	435308823	212686	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	212686	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	3272813	0	0
ReadyAndValidImplyGrant_A	435308823	212686	0	0
ReqAndReadyImplyGrant_A	435308823	212686	0	0
ReqImpliesValid_A	435308823	563586	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	212686	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	212686	0	0
T1	40609	363	0	0
T2	326538	12	0	0
T3	123072	171	0	0
T7	229229	228	0	0
T8	172283	0	0	0
T9	61603	164	0	0
T10	257053	146	0	0
T11	2355	9	0	0
T12	13357	13	0	0
T13	10401	12	0	0
T14	0	92	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	212686	0	0
T1	40609	363	0	0
T2	326538	12	0	0
T3	123072	171	0	0
T7	229229	228	0	0
T8	172283	0	0	0
T9	61603	164	0	0
T10	257053	146	0	0
T11	2355	9	0	0
T12	13357	13	0	0
T13	10401	12	0	0
T14	0	92	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	212686	0	0
T1	40609	363	0	0
T2	326538	12	0	0
T3	123072	171	0	0
T7	229229	228	0	0
T8	172283	0	0	0
T9	61603	164	0	0
T10	257053	146	0	0
T11	2355	9	0	0
T12	13357	13	0	0
T13	10401	12	0	0
T14	0	92	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	3272813	0	0
T1	40609	360	0	0
T2	326538	40	0	0
T3	123072	1349	0	0
T7	229229	995	0	0
T8	172283	1	0	0
T9	61603	1121	0	0
T10	257053	47783	0	0
T11	2355	9	0	0
T12	13357	151	0	0
T13	10401	110	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	212686	0	0
T1	40609	363	0	0
T2	326538	12	0	0
T3	123072	171	0	0
T7	229229	228	0	0
T8	172283	0	0	0
T9	61603	164	0	0
T10	257053	146	0	0
T11	2355	9	0	0
T12	13357	13	0	0
T13	10401	12	0	0
T14	0	92	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	212686	0	0
T1	40609	363	0	0
T2	326538	12	0	0
T3	123072	171	0	0
T7	229229	228	0	0
T8	172283	0	0	0
T9	61603	164	0	0
T10	257053	146	0	0
T11	2355	9	0	0
T12	13357	13	0	0
T13	10401	12	0	0
T14	0	92	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	563586	0	0
T1	40609	369	0	0
T2	326538	14	0	0
T3	123072	228	0	0
T7	229229	253	0	0
T8	172283	0	0	0
T9	61603	231	0	0
T10	257053	1830	0	0
T11	2355	10	0	0
T12	13357	13	0	0
T13	10401	20	0	0
T14	0	120	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	212686	0	0
T1	40609	363	0	0
T2	326538	12	0	0
T3	123072	171	0	0
T7	229229	228	0	0
T8	172283	0	0	0
T9	61603	164	0	0
T10	257053	146	0	0
T11	2355	9	0	0
T12	13357	13	0	0
T13	10401	12	0	0
T14	0	92	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	207548	0	0
GntImpliesValid_A	435308823	207548	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	207548	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	3295452	0	0
ReadyAndValidImplyGrant_A	435308823	207548	0	0
ReqAndReadyImplyGrant_A	435308823	207548	0	0
ReqImpliesValid_A	435308823	554411	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	207548	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	207548	0	0
T1	40609	839	0	0
T2	326538	12	0	0
T3	123072	183	0	0
T7	229229	231	0	0
T8	172283	0	0	0
T9	61603	158	0	0
T10	257053	153	0	0
T11	2355	13	0	0
T12	13357	10	0	0
T13	10401	5	0	0
T14	0	120	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	207548	0	0
T1	40609	839	0	0
T2	326538	12	0	0
T3	123072	183	0	0
T7	229229	231	0	0
T8	172283	0	0	0
T9	61603	158	0	0
T10	257053	153	0	0
T11	2355	13	0	0
T12	13357	10	0	0
T13	10401	5	0	0
T14	0	120	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	207548	0	0
T1	40609	839	0	0
T2	326538	12	0	0
T3	123072	183	0	0
T7	229229	231	0	0
T8	172283	0	0	0
T9	61603	158	0	0
T10	257053	153	0	0
T11	2355	13	0	0
T12	13357	10	0	0
T13	10401	5	0	0
T14	0	120	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	3295452	0	0
T1	40609	672	0	0
T2	326538	62	0	0
T3	123072	1345	0	0
T7	229229	1003	0	0
T8	172283	1	0	0
T9	61603	1072	0	0
T10	257053	47016	0	0
T11	2355	13	0	0
T12	13357	75	0	0
T13	10401	49	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	207548	0	0
T1	40609	839	0	0
T2	326538	12	0	0
T3	123072	183	0	0
T7	229229	231	0	0
T8	172283	0	0	0
T9	61603	158	0	0
T10	257053	153	0	0
T11	2355	13	0	0
T12	13357	10	0	0
T13	10401	5	0	0
T14	0	120	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	207548	0	0
T1	40609	839	0	0
T2	326538	12	0	0
T3	123072	183	0	0
T7	229229	231	0	0
T8	172283	0	0	0
T9	61603	158	0	0
T10	257053	153	0	0
T11	2355	13	0	0
T12	13357	10	0	0
T13	10401	5	0	0
T14	0	120	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	554411	0	0
T1	40609	1009	0	0
T2	326538	18	0	0
T3	123072	190	0	0
T7	229229	316	0	0
T8	172283	0	0	0
T9	61603	201	0	0
T10	257053	2919	0	0
T11	2355	14	0	0
T12	13357	10	0	0
T13	10401	5	0	0
T14	0	166	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	207548	0	0
T1	40609	839	0	0
T2	326538	12	0	0
T3	123072	183	0	0
T7	229229	231	0	0
T8	172283	0	0	0
T9	61603	158	0	0
T10	257053	153	0	0
T11	2355	13	0	0
T12	13357	10	0	0
T13	10401	5	0	0
T14	0	120	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	233634	0	0
GntImpliesValid_A	435308823	233634	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	233634	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	3385955	0	0
ReadyAndValidImplyGrant_A	435308823	233634	0	0
ReqAndReadyImplyGrant_A	435308823	233634	0	0
ReqImpliesValid_A	435308823	573030	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	233634	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	233634	0	0
T1	40609	385	0	0
T2	326538	21	0	0
T3	123072	173	0	0
T7	229229	221	0	0
T8	172283	0	0	0
T9	61603	161	0	0
T10	257053	154	0	0
T11	2355	15	0	0
T12	13357	18	0	0
T13	10401	17	0	0
T14	0	169	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	233634	0	0
T1	40609	385	0	0
T2	326538	21	0	0
T3	123072	173	0	0
T7	229229	221	0	0
T8	172283	0	0	0
T9	61603	161	0	0
T10	257053	154	0	0
T11	2355	15	0	0
T12	13357	18	0	0
T13	10401	17	0	0
T14	0	169	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	233634	0	0
T1	40609	385	0	0
T2	326538	21	0	0
T3	123072	173	0	0
T7	229229	221	0	0
T8	172283	0	0	0
T9	61603	161	0	0
T10	257053	154	0	0
T11	2355	15	0	0
T12	13357	18	0	0
T13	10401	17	0	0
T14	0	169	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	3385955	0	0
T1	40609	385	0	0
T2	326538	72	0	0
T3	123072	1385	0	0
T7	229229	920	0	0
T8	172283	1	0	0
T9	61603	1193	0	0
T10	257053	55813	0	0
T11	2355	16	0	0
T12	13357	136	0	0
T13	10401	143	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	233634	0	0
T1	40609	385	0	0
T2	326538	21	0	0
T3	123072	173	0	0
T7	229229	221	0	0
T8	172283	0	0	0
T9	61603	161	0	0
T10	257053	154	0	0
T11	2355	15	0	0
T12	13357	18	0	0
T13	10401	17	0	0
T14	0	169	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	233634	0	0
T1	40609	385	0	0
T2	326538	21	0	0
T3	123072	173	0	0
T7	229229	221	0	0
T8	172283	0	0	0
T9	61603	161	0	0
T10	257053	154	0	0
T11	2355	15	0	0
T12	13357	18	0	0
T13	10401	17	0	0
T14	0	169	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	573030	0	0
T1	40609	388	0	0
T2	326538	25	0	0
T3	123072	173	0	0
T7	229229	272	0	0
T8	172283	0	0	0
T9	61603	201	0	0
T10	257053	1412	0	0
T11	2355	15	0	0
T12	13357	27	0	0
T13	10401	17	0	0
T14	0	202	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	233634	0	0
T1	40609	385	0	0
T2	326538	21	0	0
T3	123072	173	0	0
T7	229229	221	0	0
T8	172283	0	0	0
T9	61603	161	0	0
T10	257053	154	0	0
T11	2355	15	0	0
T12	13357	18	0	0
T13	10401	17	0	0
T14	0	169	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	206721	0	0
GntImpliesValid_A	435308823	206721	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	206721	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	3240941	0	0
ReadyAndValidImplyGrant_A	435308823	206721	0	0
ReqAndReadyImplyGrant_A	435308823	206721	0	0
ReqImpliesValid_A	435308823	543995	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	206721	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	206721	0	0
T1	40609	1368	0	0
T2	326538	15	0	0
T3	123072	175	0	0
T7	229229	219	0	0
T8	172283	0	0	0
T9	61603	190	0	0
T10	257053	152	0	0
T11	2355	17	0	0
T12	13357	10	0	0
T13	10401	15	0	0
T14	0	109	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	206721	0	0
T1	40609	1368	0	0
T2	326538	15	0	0
T3	123072	175	0	0
T7	229229	219	0	0
T8	172283	0	0	0
T9	61603	190	0	0
T10	257053	152	0	0
T11	2355	17	0	0
T12	13357	10	0	0
T13	10401	15	0	0
T14	0	109	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	206721	0	0
T1	40609	1368	0	0
T2	326538	15	0	0
T3	123072	175	0	0
T7	229229	219	0	0
T8	172283	0	0	0
T9	61603	190	0	0
T10	257053	152	0	0
T11	2355	17	0	0
T12	13357	10	0	0
T13	10401	15	0	0
T14	0	109	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	3240941	0	0
T1	40609	1100	0	0
T2	326538	59	0	0
T3	123072	1245	0	0
T7	229229	879	0	0
T8	172283	1	0	0
T9	61603	1395	0	0
T10	257053	45566	0	0
T11	2355	17	0	0
T12	13357	90	0	0
T13	10401	130	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	206721	0	0
T1	40609	1368	0	0
T2	326538	15	0	0
T3	123072	175	0	0
T7	229229	219	0	0
T8	172283	0	0	0
T9	61603	190	0	0
T10	257053	152	0	0
T11	2355	17	0	0
T12	13357	10	0	0
T13	10401	15	0	0
T14	0	109	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	206721	0	0
T1	40609	1368	0	0
T2	326538	15	0	0
T3	123072	175	0	0
T7	229229	219	0	0
T8	172283	0	0	0
T9	61603	190	0	0
T10	257053	152	0	0
T11	2355	17	0	0
T12	13357	10	0	0
T13	10401	15	0	0
T14	0	109	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	543995	0	0
T1	40609	1639	0	0
T2	326538	28	0	0
T3	123072	178	0	0
T7	229229	254	0	0
T8	172283	0	0	0
T9	61603	332	0	0
T10	257053	4331	0	0
T11	2355	18	0	0
T12	13357	10	0	0
T13	10401	30	0	0
T14	0	139	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	206721	0	0
T1	40609	1368	0	0
T2	326538	15	0	0
T3	123072	175	0	0
T7	229229	219	0	0
T8	172283	0	0	0
T9	61603	190	0	0
T10	257053	152	0	0
T11	2355	17	0	0
T12	13357	10	0	0
T13	10401	15	0	0
T14	0	109	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	210612	0	0
GntImpliesValid_A	435308823	210612	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	210612	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	3325381	0	0
ReadyAndValidImplyGrant_A	435308823	210612	0	0
ReqAndReadyImplyGrant_A	435308823	210612	0	0
ReqImpliesValid_A	435308823	532138	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	210612	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	210612	0	0
T1	40609	863	0	0
T2	326538	19	0	0
T3	123072	202	0	0
T7	229229	214	0	0
T8	172283	0	0	0
T9	61603	153	0	0
T10	257053	170	0	0
T11	2355	17	0	0
T12	13357	22	0	0
T13	10401	20	0	0
T14	0	89	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	210612	0	0
T1	40609	863	0	0
T2	326538	19	0	0
T3	123072	202	0	0
T7	229229	214	0	0
T8	172283	0	0	0
T9	61603	153	0	0
T10	257053	170	0	0
T11	2355	17	0	0
T12	13357	22	0	0
T13	10401	20	0	0
T14	0	89	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	210612	0	0
T1	40609	863	0	0
T2	326538	19	0	0
T3	123072	202	0	0
T7	229229	214	0	0
T8	172283	0	0	0
T9	61603	153	0	0
T10	257053	170	0	0
T11	2355	17	0	0
T12	13357	22	0	0
T13	10401	20	0	0
T14	0	89	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	3325381	0	0
T1	40609	775	0	0
T2	326538	93	0	0
T3	123072	1406	0	0
T7	229229	991	0	0
T8	172283	1	0	0
T9	61603	1146	0	0
T10	257053	54174	0	0
T11	2355	18	0	0
T12	13357	168	0	0
T13	10401	125	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	210612	0	0
T1	40609	863	0	0
T2	326538	19	0	0
T3	123072	202	0	0
T7	229229	214	0	0
T8	172283	0	0	0
T9	61603	153	0	0
T10	257053	170	0	0
T11	2355	17	0	0
T12	13357	22	0	0
T13	10401	20	0	0
T14	0	89	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	210612	0	0
T1	40609	863	0	0
T2	326538	19	0	0
T3	123072	202	0	0
T7	229229	214	0	0
T8	172283	0	0	0
T9	61603	153	0	0
T10	257053	170	0	0
T11	2355	17	0	0
T12	13357	22	0	0
T13	10401	20	0	0
T14	0	89	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	532138	0	0
T1	40609	954	0	0
T2	326538	19	0	0
T3	123072	202	0	0
T7	229229	219	0	0
T8	172283	0	0	0
T9	61603	204	0	0
T10	257053	1941	0	0
T11	2355	17	0	0
T12	13357	29	0	0
T13	10401	43	0	0
T14	0	128	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	210612	0	0
T1	40609	863	0	0
T2	326538	19	0	0
T3	123072	202	0	0
T7	229229	214	0	0
T8	172283	0	0	0
T9	61603	153	0	0
T10	257053	170	0	0
T11	2355	17	0	0
T12	13357	22	0	0
T13	10401	20	0	0
T14	0	89	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	215227	0	0
GntImpliesValid_A	435308823	215227	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	215227	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	3286095	0	0
ReadyAndValidImplyGrant_A	435308823	215227	0	0
ReqAndReadyImplyGrant_A	435308823	215227	0	0
ReqImpliesValid_A	435308823	568824	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	215227	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	215227	0	0
T1	40609	847	0	0
T2	326538	7	0	0
T3	123072	209	0	0
T7	229229	199	0	0
T8	172283	0	0	0
T9	61603	170	0	0
T10	257053	141	0	0
T11	2355	17	0	0
T12	13357	15	0	0
T13	10401	13	0	0
T14	0	82	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	215227	0	0
T1	40609	847	0	0
T2	326538	7	0	0
T3	123072	209	0	0
T7	229229	199	0	0
T8	172283	0	0	0
T9	61603	170	0	0
T10	257053	141	0	0
T11	2355	17	0	0
T12	13357	15	0	0
T13	10401	13	0	0
T14	0	82	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	215227	0	0
T1	40609	847	0	0
T2	326538	7	0	0
T3	123072	209	0	0
T7	229229	199	0	0
T8	172283	0	0	0
T9	61603	170	0	0
T10	257053	141	0	0
T11	2355	17	0	0
T12	13357	15	0	0
T13	10401	13	0	0
T14	0	82	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	3286095	0	0
T1	40609	675	0	0
T2	326538	32	0	0
T3	123072	1762	0	0
T7	229229	915	0	0
T8	172283	1	0	0
T9	61603	1332	0	0
T10	257053	47651	0	0
T11	2355	18	0	0
T12	13357	112	0	0
T13	10401	79	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	215227	0	0
T1	40609	847	0	0
T2	326538	7	0	0
T3	123072	209	0	0
T7	229229	199	0	0
T8	172283	0	0	0
T9	61603	170	0	0
T10	257053	141	0	0
T11	2355	17	0	0
T12	13357	15	0	0
T13	10401	13	0	0
T14	0	82	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	215227	0	0
T1	40609	847	0	0
T2	326538	7	0	0
T3	123072	209	0	0
T7	229229	199	0	0
T8	172283	0	0	0
T9	61603	170	0	0
T10	257053	141	0	0
T11	2355	17	0	0
T12	13357	15	0	0
T13	10401	13	0	0
T14	0	82	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	568824	0	0
T1	40609	1022	0	0
T2	326538	7	0	0
T3	123072	218	0	0
T7	229229	252	0	0
T8	172283	0	0	0
T9	61603	254	0	0
T10	257053	2955	0	0
T11	2355	17	0	0
T12	13357	17	0	0
T13	10401	13	0	0
T14	0	85	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	215227	0	0
T1	40609	847	0	0
T2	326538	7	0	0
T3	123072	209	0	0
T7	229229	199	0	0
T8	172283	0	0	0
T9	61603	170	0	0
T10	257053	141	0	0
T11	2355	17	0	0
T12	13357	15	0	0
T13	10401	13	0	0
T14	0	82	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	212684	0	0
GntImpliesValid_A	435308823	212684	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	212684	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	3259058	0	0
ReadyAndValidImplyGrant_A	435308823	212684	0	0
ReqAndReadyImplyGrant_A	435308823	212684	0	0
ReqImpliesValid_A	435308823	571974	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	212684	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	212684	0	0
T1	40609	335	0	0
T2	326538	14	0	0
T3	123072	187	0	0
T7	229229	225	0	0
T8	172283	562	0	0
T9	61603	161	0	0
T10	257053	164	0	0
T11	2355	17	0	0
T12	13357	22	0	0
T13	10401	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	212684	0	0
T1	40609	335	0	0
T2	326538	14	0	0
T3	123072	187	0	0
T7	229229	225	0	0
T8	172283	562	0	0
T9	61603	161	0	0
T10	257053	164	0	0
T11	2355	17	0	0
T12	13357	22	0	0
T13	10401	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	212684	0	0
T1	40609	335	0	0
T2	326538	14	0	0
T3	123072	187	0	0
T7	229229	225	0	0
T8	172283	562	0	0
T9	61603	161	0	0
T10	257053	164	0	0
T11	2355	17	0	0
T12	13357	22	0	0
T13	10401	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	3259058	0	0
T1	40609	334	0	0
T2	326538	42	0	0
T3	123072	1435	0	0
T7	229229	946	0	0
T8	172283	1829	0	0
T9	61603	1219	0	0
T10	257053	55876	0	0
T11	2355	18	0	0
T12	13357	172	0	0
T13	10401	118	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	212684	0	0
T1	40609	335	0	0
T2	326538	14	0	0
T3	123072	187	0	0
T7	229229	225	0	0
T8	172283	562	0	0
T9	61603	161	0	0
T10	257053	164	0	0
T11	2355	17	0	0
T12	13357	22	0	0
T13	10401	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	212684	0	0
T1	40609	335	0	0
T2	326538	14	0	0
T3	123072	187	0	0
T7	229229	225	0	0
T8	172283	562	0	0
T9	61603	161	0	0
T10	257053	164	0	0
T11	2355	17	0	0
T12	13357	22	0	0
T13	10401	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	571974	0	0
T1	40609	339	0	0
T2	326538	16	0	0
T3	123072	198	0	0
T7	229229	291	0	0
T8	172283	1265	0	0
T9	61603	245	0	0
T10	257053	2039	0	0
T11	2355	17	0	0
T12	13357	22	0	0
T13	10401	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	212684	0	0
T1	40609	335	0	0
T2	326538	14	0	0
T3	123072	187	0	0
T7	229229	225	0	0
T8	172283	562	0	0
T9	61603	161	0	0
T10	257053	164	0	0
T11	2355	17	0	0
T12	13357	22	0	0
T13	10401	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	209166	0	0
GntImpliesValid_A	435308823	209166	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	209166	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	3271752	0	0
ReadyAndValidImplyGrant_A	435308823	209166	0	0
ReqAndReadyImplyGrant_A	435308823	209166	0	0
ReqImpliesValid_A	435308823	566581	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	0	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	209166	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	209166	0	0
T1	40609	329	0	0
T2	326538	8	0	0
T3	123072	184	0	0
T7	229229	207	0	0
T8	172283	0	0	0
T9	61603	159	0	0
T10	257053	177	0	0
T11	2355	20	0	0
T12	13357	17	0	0
T13	10401	10	0	0
T14	0	95	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	209166	0	0
T1	40609	329	0	0
T2	326538	8	0	0
T3	123072	184	0	0
T7	229229	207	0	0
T8	172283	0	0	0
T9	61603	159	0	0
T10	257053	177	0	0
T11	2355	20	0	0
T12	13357	17	0	0
T13	10401	10	0	0
T14	0	95	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	209166	0	0
T1	40609	329	0	0
T2	326538	8	0	0
T3	123072	184	0	0
T7	229229	207	0	0
T8	172283	0	0	0
T9	61603	159	0	0
T10	257053	177	0	0
T11	2355	20	0	0
T12	13357	17	0	0
T13	10401	10	0	0
T14	0	95	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	3271752	0	0
T1	40609	326	0	0
T2	326538	32	0	0
T3	123072	1409	0	0
T7	229229	838	0	0
T8	172283	1	0	0
T9	61603	1076	0	0
T10	257053	53119	0	0
T11	2355	20	0	0
T12	13357	96	0	0
T13	10401	46	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	209166	0	0
T1	40609	329	0	0
T2	326538	8	0	0
T3	123072	184	0	0
T7	229229	207	0	0
T8	172283	0	0	0
T9	61603	159	0	0
T10	257053	177	0	0
T11	2355	20	0	0
T12	13357	17	0	0
T13	10401	10	0	0
T14	0	95	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	209166	0	0
T1	40609	329	0	0
T2	326538	8	0	0
T3	123072	184	0	0
T7	229229	207	0	0
T8	172283	0	0	0
T9	61603	159	0	0
T10	257053	177	0	0
T11	2355	20	0	0
T12	13357	17	0	0
T13	10401	10	0	0
T14	0	95	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	566581	0	0
T1	40609	335	0	0
T2	326538	16	0	0
T3	123072	192	0	0
T7	229229	287	0	0
T8	172283	0	0	0
T9	61603	223	0	0
T10	257053	5543	0	0
T11	2355	21	0	0
T12	13357	17	0	0
T13	10401	10	0	0
T14	0	119	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	209166	0	0
T1	40609	329	0	0
T2	326538	8	0	0
T3	123072	184	0	0
T7	229229	207	0	0
T8	172283	0	0	0
T9	61603	159	0	0
T10	257053	177	0	0
T11	2355	20	0	0
T12	13357	17	0	0
T13	10401	10	0	0
T14	0	95	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	871878	0	0
GntImpliesValid_A	435308823	871878	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	871878	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	12643493	0	0
ReadyAndValidImplyGrant_A	435308823	871878	0	0
ReqAndReadyImplyGrant_A	435308823	871878	0	0
ReqImpliesValid_A	435308823	2410302	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	16438	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	871878	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	871878	0	0
T1	40609	1998	0	0
T2	326538	39	0	0
T3	123072	754	0	0
T7	229229	936	0	0
T8	172283	341	0	0
T9	61603	640	0	0
T10	257053	621	0	0
T11	2355	51	0	0
T12	13357	57	0	0
T13	10401	47	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	871878	0	0
T1	40609	1998	0	0
T2	326538	39	0	0
T3	123072	754	0	0
T7	229229	936	0	0
T8	172283	341	0	0
T9	61603	640	0	0
T10	257053	621	0	0
T11	2355	51	0	0
T12	13357	57	0	0
T13	10401	47	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	871878	0	0
T1	40609	1998	0	0
T2	326538	39	0	0
T3	123072	754	0	0
T7	229229	936	0	0
T8	172283	341	0	0
T9	61603	640	0	0
T10	257053	621	0	0
T11	2355	51	0	0
T12	13357	57	0	0
T13	10401	47	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	12643493	0	0
T1	40609	3	0	0
T2	326538	140	0	0
T3	123072	4792	0	0
T7	229229	3024	0	0
T8	172283	1072	0	0
T9	61603	4326	0	0
T10	257053	201987	0	0
T11	2355	1	0	0
T12	13357	386	0	0
T13	10401	352	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	871878	0	0
T1	40609	1998	0	0
T2	326538	39	0	0
T3	123072	754	0	0
T7	229229	936	0	0
T8	172283	341	0	0
T9	61603	640	0	0
T10	257053	621	0	0
T11	2355	51	0	0
T12	13357	57	0	0
T13	10401	47	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	871878	0	0
T1	40609	1998	0	0
T2	326538	39	0	0
T3	123072	754	0	0
T7	229229	936	0	0
T8	172283	341	0	0
T9	61603	640	0	0
T10	257053	621	0	0
T11	2355	51	0	0
T12	13357	57	0	0
T13	10401	47	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	2410302	0	0
T1	40609	1998	0	0
T2	326538	49	0	0
T3	123072	823	0	0
T7	229229	1243	0	0
T8	172283	461	0	0
T9	61603	1106	0	0
T10	257053	26232	0	0
T11	2355	51	0	0
T12	13357	68	0	0
T13	10401	67	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	16438	0	900
T1	40609	20	0	1
T2	326538	0	0	1
T3	123072	0	0	1
T7	229229	0	0	1
T8	172283	0	0	1
T9	61603	0	0	1
T10	257053	0	0	1
T11	2355	0	0	1
T12	13357	0	0	1
T13	10401	0	0	1
T15	0	9	0	0
T16	0	5	0	0
T18	0	9	0	0
T21	0	6	0	0
T22	0	509	0	0
T23	0	9	0	0
T24	0	3	0	0
T25	0	8	0	0
T26	0	34	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	871878	0	0
T1	40609	1998	0	0
T2	326538	39	0	0
T3	123072	754	0	0
T7	229229	936	0	0
T8	172283	341	0	0
T9	61603	640	0	0
T10	257053	621	0	0
T11	2355	51	0	0
T12	13357	57	0	0
T13	10401	47	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435308823	435182042	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	435308823	864858	0	0
GntImpliesValid_A	435308823	864858	0	0
GrantKnown_A	435308823	435182042	0	0
IdxKnown_A	435308823	435182042	0	0
IndexIsCorrect_A	435308823	864858	0	0
LockArbDecision_A	435308823	0	0	0
NoReadyValidNoGrant_A	435308823	366175766	0	0
ReadyAndValidImplyGrant_A	435308823	864858	0	0
ReqAndReadyImplyGrant_A	435308823	864858	0	0
ReqImpliesValid_A	435308823	14401457	0	0
ReqStaysHighUntilGranted0_M	435308823	0	0	0
RoundRobin_A	435308823	30334	0	900
ValidKnown_A	435308823	435182042	0	0
gen_data_port_assertion.DataFlow_A	435308823	864858	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	864858	0	0
T1	40609	2812	0	0
T2	326538	33	0	0
T3	123072	795	0	0
T7	229229	937	0	0
T8	172283	340	0	0
T9	61603	653	0	0
T10	257053	654	0	0
T11	2355	46	0	0
T12	13357	51	0	0
T13	10401	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	864858	0	0
T1	40609	2812	0	0
T2	326538	33	0	0
T3	123072	795	0	0
T7	229229	937	0	0
T8	172283	340	0	0
T9	61603	653	0	0
T10	257053	654	0	0
T11	2355	46	0	0
T12	13357	51	0	0
T13	10401	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	864858	0	0
T1	40609	2812	0	0
T2	326538	33	0	0
T3	123072	795	0	0
T7	229229	937	0	0
T8	172283	340	0	0
T9	61603	653	0	0
T10	257053	654	0	0
T11	2355	46	0	0
T12	13357	51	0	0
T13	10401	38	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	366175766	0	0
T1	40609	1	0	0
T2	326538	272124	0	0
T3	123072	104220	0	0
T7	229229	190653	0	0
T8	172283	143412	0	0
T9	61603	49407	0	0
T10	257053	232769	0	0
T11	2355	1	0	0
T12	13357	11752	0	0
T13	10401	9080	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	864858	0	0
T1	40609	2812	0	0
T2	326538	33	0	0
T3	123072	795	0	0
T7	229229	937	0	0
T8	172283	340	0	0
T9	61603	653	0	0
T10	257053	654	0	0
T11	2355	46	0	0
T12	13357	51	0	0
T13	10401	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	864858	0	0
T1	40609	2812	0	0
T2	326538	33	0	0
T3	123072	795	0	0
T7	229229	937	0	0
T8	172283	340	0	0
T9	61603	653	0	0
T10	257053	654	0	0
T11	2355	46	0	0
T12	13357	51	0	0
T13	10401	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	14401457	0	0
T1	40609	2812	0	0
T2	326538	124	0	0
T3	123072	5913	0	0
T7	229229	4129	0	0
T8	172283	1513	0	0
T9	61603	5261	0	0
T10	257053	238291	0	0
T11	2355	46	0	0
T12	13357	415	0	0
T13	10401	281	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	30334	0	900
T1	40609	208	0	1
T2	326538	0	0	1
T3	123072	0	0	1
T7	229229	0	0	1
T8	172283	0	0	1
T9	61603	2	0	1
T10	257053	0	0	1
T11	2355	0	0	1
T12	13357	0	0	1
T13	10401	0	0	1
T14	0	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T18	0	7	0	0
T19	0	431	0	0
T20	0	3	0	0
T21	0	6	0	0
T22	0	509	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	435182042	0	0
T1	40609	40529	0	0
T2	326538	326484	0	0
T3	123072	123030	0	0
T7	229229	229227	0	0
T8	172283	172277	0	0
T9	61603	61573	0	0
T10	257053	257046	0	0
T11	2355	2320	0	0
T12	13357	13300	0	0
T13	10401	10378	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435308823	864858	0	0
T1	40609	2812	0	0
T2	326538	33	0	0
T3	123072	795	0	0
T7	229229	937	0	0
T8	172283	340	0	0
T9	61603	653	0	0
T10	257053	654	0	0
T11	2355	46	0	0
T12	13357	51	0	0
T13	10401	38	0	0