Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1520581	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

241258

1

T1

6

T2

15

T3

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	598395	1			T1	49		T2	41		T3	54
values[0x0]	564025	1			T1	9		T2	26		T3	46
values[0x1]	599419	1			T1	57		T2	47		T3	49

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1174893	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

586946

1

T1

37

T2

47

T3

43

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26793	1			T1	2		T2	25		T3	3
valid_sources[0x01]	27155	1			T1	2		T3	3		T7	63
valid_sources[0x02]	28174	1			T1	1		T3	4		T7	40
valid_sources[0x03]	27843	1			T7	33		T8	2		T9	7
valid_sources[0x04]	27613	1			T7	47		T8	4		T9	10
valid_sources[0x05]	27956	1			T1	1		T3	1		T7	83
valid_sources[0x06]	27766	1			T1	3		T3	1		T7	63
valid_sources[0x07]	28177	1			T1	4		T7	72		T9	12
valid_sources[0x08]	26956	1			T3	2		T7	17		T9	15
valid_sources[0x09]	27887	1			T1	3		T7	17		T8	3
valid_sources[0x0a]	26420	1			T7	47		T8	1		T9	7
valid_sources[0x0b]	27606	1			T1	4		T3	6		T7	28
valid_sources[0x0c]	27812	1			T1	2		T3	4		T7	39
valid_sources[0x0d]	27585	1			T3	4		T7	88		T8	3
valid_sources[0x0e]	27604	1			T2	2		T7	22		T8	2
valid_sources[0x0f]	27326	1			T1	7		T7	13		T9	11
valid_sources[0x10]	28068	1			T1	5		T3	2		T7	12
valid_sources[0x11]	27457	1			T1	4		T3	3		T7	59
valid_sources[0x12]	27316	1			T3	2		T7	26		T9	8
valid_sources[0x13]	27027	1			T1	3		T2	7		T3	1
valid_sources[0x14]	27757	1			T2	24		T3	1		T7	51
valid_sources[0x15]	27412	1			T3	6		T7	48		T8	2
valid_sources[0x16]	28434	1			T3	4		T7	51		T9	9
valid_sources[0x17]	26905	1			T1	2		T7	29		T9	5
valid_sources[0x18]	27494	1			T3	4		T7	21		T8	3
valid_sources[0x19]	26568	1			T1	11		T7	42		T9	5
valid_sources[0x1a]	27785	1			T7	8		T8	3		T9	12
valid_sources[0x1b]	28863	1			T1	5		T3	6		T7	10
valid_sources[0x1c]	27852	1			T1	2		T3	3		T7	60
valid_sources[0x1d]	26698	1			T1	2		T3	1		T7	18
valid_sources[0x1e]	26705	1			T1	1		T2	12		T3	5
valid_sources[0x1f]	28025	1			T7	51		T8	2		T9	7
valid_sources[0x20]	26645	1			T7	23		T9	10		T10	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25726

1

T1

2

T2

3

T3

4

values[0x0]

all_enables

biggest_size

190028

1

T1

3

T2

11

T3

10

values[0x1]

all_enables

biggest_size

25504

1

T1

1

T2

1

T3

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1531974	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

248323

1

T1

8

T2

16

T3

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	609889	1			T1	52		T2	43		T3	77
values[0x0]	561034	1			T1	10		T2	33		T3	63
values[0x1]	609374	1			T1	59		T2	31		T3	46

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1175811	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

604486

1

T1

47

T2

33

T3

55

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28002	1			T1	3		T3	6		T7	33
valid_sources[0x01]	28297	1			T1	4		T3	2		T7	43
valid_sources[0x02]	28054	1			T1	1		T3	2		T7	63
valid_sources[0x03]	27695	1			T2	3		T3	4		T7	49
valid_sources[0x04]	27909	1			T1	3		T2	4		T3	2
valid_sources[0x05]	27506	1			T1	4		T2	2		T3	2
valid_sources[0x06]	27631	1			T1	1		T2	1		T3	1
valid_sources[0x07]	28749	1			T2	3		T3	3		T7	50
valid_sources[0x08]	27777	1			T2	2		T3	1		T7	39
valid_sources[0x09]	27643	1			T2	1		T3	2		T7	53
valid_sources[0x0a]	28223	1			T1	2		T3	5		T7	58
valid_sources[0x0b]	27772	1			T1	1		T2	2		T3	5
valid_sources[0x0c]	28141	1			T1	4		T3	5		T7	43
valid_sources[0x0d]	28223	1			T1	1		T2	3		T3	4
valid_sources[0x0e]	28180	1			T1	4		T3	5		T7	55
valid_sources[0x0f]	27529	1			T1	3		T2	3		T3	1
valid_sources[0x10]	28454	1			T1	3		T2	2		T3	5
valid_sources[0x11]	28158	1			T1	2		T3	1		T7	39
valid_sources[0x12]	27530	1			T1	1		T2	2		T3	2
valid_sources[0x13]	27968	1			T1	2		T2	2		T3	1
valid_sources[0x14]	27853	1			T1	5		T2	3		T3	4
valid_sources[0x15]	27710	1			T1	1		T2	1		T7	50
valid_sources[0x16]	27970	1			T1	1		T2	2		T3	3
valid_sources[0x17]	27437	1			T1	2		T2	6		T3	2
valid_sources[0x18]	28044	1			T1	1		T2	3		T3	2
valid_sources[0x19]	28052	1			T1	4		T2	4		T3	5
valid_sources[0x1a]	28159	1			T1	2		T3	1		T7	36
valid_sources[0x1b]	27612	1			T1	3		T7	48		T9	9
valid_sources[0x1c]	28174	1			T1	2		T2	4		T3	2
valid_sources[0x1d]	27345	1			T1	2		T3	4		T7	52
valid_sources[0x1e]	27835	1			T1	2		T2	1		T3	4
valid_sources[0x1f]	27708	1			T1	2		T2	2		T3	6
valid_sources[0x20]	27914	1			T1	2		T3	3		T7	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26210

1

T1

5

T2

3

T3

2

values[0x0]

all_enables

biggest_size

196085

1

T1

1

T2

12

T3

24

values[0x1]

all_enables

biggest_size

26028

1

T1

2

T2

1

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1530542	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

243319

1

T1

9

T2

18

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	603875	1			T1	64		T2	46		T3	55
values[0x0]	569085	1			T1	3		T2	38		T3	48
values[0x1]	600901	1			T1	60		T2	52		T3	55

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1182573	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

591288

1

T1

53

T2

56

T3

54

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27970	1			T1	4		T2	2		T3	1
valid_sources[0x01]	27524	1			T1	1		T3	6		T7	43
valid_sources[0x02]	27900	1			T2	1		T3	2		T7	41
valid_sources[0x03]	27591	1			T1	5		T2	1		T3	2
valid_sources[0x04]	27269	1			T1	2		T2	2		T3	2
valid_sources[0x05]	26943	1			T1	2		T2	1		T7	44
valid_sources[0x06]	27306	1			T1	1		T2	1		T3	3
valid_sources[0x07]	27928	1			T1	3		T2	2		T3	2
valid_sources[0x08]	27195	1			T2	3		T3	3		T7	44
valid_sources[0x09]	27261	1			T1	2		T2	4		T7	50
valid_sources[0x0a]	27875	1			T1	1		T2	1		T3	1
valid_sources[0x0b]	27414	1			T1	1		T2	4		T3	1
valid_sources[0x0c]	26940	1			T1	1		T2	2		T3	1
valid_sources[0x0d]	27881	1			T1	4		T2	2		T3	2
valid_sources[0x0e]	28333	1			T1	1		T3	2		T7	49
valid_sources[0x0f]	27505	1			T1	2		T3	5		T7	43
valid_sources[0x10]	28181	1			T2	1		T3	1		T7	43
valid_sources[0x11]	27028	1			T1	3		T2	1		T3	2
valid_sources[0x12]	26903	1			T1	1		T2	3		T3	2
valid_sources[0x13]	28063	1			T1	4		T2	5		T3	5
valid_sources[0x14]	27401	1			T1	1		T2	6		T3	3
valid_sources[0x15]	28073	1			T1	1		T2	3		T3	2
valid_sources[0x16]	27790	1			T1	3		T2	6		T3	1
valid_sources[0x17]	27668	1			T1	1		T2	2		T7	49
valid_sources[0x18]	27146	1			T1	1		T2	3		T3	2
valid_sources[0x19]	27778	1			T1	2		T2	1		T3	3
valid_sources[0x1a]	28230	1			T1	6		T2	1		T7	43
valid_sources[0x1b]	28096	1			T1	1		T2	2		T3	10
valid_sources[0x1c]	27675	1			T1	6		T2	2		T3	5
valid_sources[0x1d]	27325	1			T1	1		T2	3		T3	5
valid_sources[0x1e]	27731	1			T1	3		T2	2		T3	2
valid_sources[0x1f]	27511	1			T1	1		T2	1		T3	5
valid_sources[0x20]	27696	1			T1	1		T3	2		T7	60

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26009

1

T1

4

T2

1

T3

6

values[0x0]

all_enables

biggest_size

191357

1

T1

1

T2

15

T3

18

values[0x1]

all_enables

biggest_size

25953

1

T1

4

T2

2

T3

2