Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8112147	0	0
GntImpliesValid_A	2147483647	8112147	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8112147	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	482301056	0	0
ReadyAndValidImplyGrant_A	2147483647	8112147	0	0
ReqAndReadyImplyGrant_A	2147483647	8112147	0	0
ReqImpliesValid_A	2147483647	36356879	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	45714	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8112147	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1319136	1317240	0	0
T2	217104	215712	0	0
T3	6265944	6264360	0	0
T7	6011232	6011088	0	0
T8	11694552	11692824	0	0
T9	6949152	6907008	0	0
T10	16288536	16283520	0	0
T11	325584	323928	0	0
T12	342768	313896	0	0
T13	51312	50112	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8112147	0	0
T1	1319136	3627	0	0
T2	217104	357	0	0
T3	6265944	493	0	0
T7	6011232	8310	0	0
T8	11694552	465	0	0
T9	6949152	30030	0	0
T10	16288536	63809	0	0
T11	325584	529	0	0
T12	342768	1434	0	0
T13	51312	444	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8112147	0	0
T1	1319136	3627	0	0
T2	217104	357	0	0
T3	6265944	493	0	0
T7	6011232	8310	0	0
T8	11694552	465	0	0
T9	6949152	30030	0	0
T10	16288536	63809	0	0
T11	325584	529	0	0
T12	342768	1434	0	0
T13	51312	444	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1319136	1317240	0	0
T2	217104	215712	0	0
T3	6265944	6264360	0	0
T7	6011232	6011088	0	0
T8	11694552	11692824	0	0
T9	6949152	6907008	0	0
T10	16288536	16283520	0	0
T11	325584	323928	0	0
T12	342768	313896	0	0
T13	51312	50112	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1319136	1317240	0	0
T2	217104	215712	0	0
T3	6265944	6264360	0	0
T7	6011232	6011088	0	0
T8	11694552	11692824	0	0
T9	6949152	6907008	0	0
T10	16288536	16283520	0	0
T11	325584	323928	0	0
T12	342768	313896	0	0
T13	51312	50112	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8112147	0	0
T1	1319136	3627	0	0
T2	217104	357	0	0
T3	6265944	493	0	0
T7	6011232	8310	0	0
T8	11694552	465	0	0
T9	6949152	30030	0	0
T10	16288536	63809	0	0
T11	325584	529	0	0
T12	342768	1434	0	0
T13	51312	444	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	482301056	0	0
T1	1319136	79333	0	0
T2	217104	10797	0	0
T3	6265944	219250	0	0
T7	6011232	247344	0	0
T8	11694552	617228	0	0
T9	6949152	445858	0	0
T10	16288536	912533	0	0
T11	325584	16097	0	0
T12	342768	15960	0	0
T13	51312	608	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8112147	0	0
T1	1319136	3627	0	0
T2	217104	357	0	0
T3	6265944	493	0	0
T7	6011232	8310	0	0
T8	11694552	465	0	0
T9	6949152	30030	0	0
T10	16288536	63809	0	0
T11	325584	529	0	0
T12	342768	1434	0	0
T13	51312	444	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8112147	0	0
T1	1319136	3627	0	0
T2	217104	357	0	0
T3	6265944	493	0	0
T7	6011232	8310	0	0
T8	11694552	465	0	0
T9	6949152	30030	0	0
T10	16288536	63809	0	0
T11	325584	529	0	0
T12	342768	1434	0	0
T13	51312	444	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36356879	0	0
T1	1319136	8024	0	0
T2	217104	716	0	0
T3	6265944	863	0	0
T7	6011232	14402	0	0
T8	11694552	34478	0	0
T9	6949152	104530	0	0
T10	16288536	263547	0	0
T11	325584	1089	0	0
T12	342768	9193	0	0
T13	51312	498	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	45714	0	21600
T9	579096	3	0	2
T10	1357378	74	0	2
T11	27132	0	0	2
T12	28564	0	0	2
T13	4276	0	0	2
T14	956150	27	0	2
T15	907030	1	0	2
T16	41592	561	0	2
T17	0	13	0	0
T18	0	211	0	0
T19	0	26	0	0
T20	0	7	0	0
T21	0	2	0	0
T22	0	12	0	0
T23	0	12	0	0
T24	0	175	0	0
T25	0	39	0	0
T26	294498	0	0	2
T27	431208	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1319136	1317240	0	0
T2	217104	215712	0	0
T3	6265944	6264360	0	0
T7	6011232	6011088	0	0
T8	11694552	11692824	0	0
T9	6949152	6907008	0	0
T10	16288536	16283520	0	0
T11	325584	323928	0	0
T12	342768	313896	0	0
T13	51312	50112	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8112147	0	0
T1	1319136	3627	0	0
T2	217104	357	0	0
T3	6265944	493	0	0
T7	6011232	8310	0	0
T8	11694552	465	0	0
T9	6949152	30030	0	0
T10	16288536	63809	0	0
T11	325584	529	0	0
T12	342768	1434	0	0
T13	51312	444	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	917782	0	0
GntImpliesValid_A	443037396	917782	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	917782	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	12554858	0	0
ReadyAndValidImplyGrant_A	443037396	917782	0	0
ReqAndReadyImplyGrant_A	443037396	917782	0	0
ReqImpliesValid_A	443037396	2672446	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	917782	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	917782	0	0
T1	54964	423	0	0
T2	9046	33	0	0
T3	261081	49	0	0
T7	250468	946	0	0
T8	487273	65	0	0
T9	289548	3062	0	0
T10	678689	8590	0	0
T11	13566	58	0	0
T12	14282	122	0	0
T13	2138	60	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	917782	0	0
T1	54964	423	0	0
T2	9046	33	0	0
T3	261081	49	0	0
T7	250468	946	0	0
T8	487273	65	0	0
T9	289548	3062	0	0
T10	678689	8590	0	0
T11	13566	58	0	0
T12	14282	122	0	0
T13	2138	60	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	917782	0	0
T1	54964	423	0	0
T2	9046	33	0	0
T3	261081	49	0	0
T7	250468	946	0	0
T8	487273	65	0	0
T9	289548	3062	0	0
T10	678689	8590	0	0
T11	13566	58	0	0
T12	14282	122	0	0
T13	2138	60	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	12554858	0	0
T1	54964	3013	0	0
T2	9046	242	0	0
T3	261081	201	0	0
T7	250468	3874	0	0
T8	487273	19090	0	0
T9	289548	22472	0	0
T10	678689	49620	0	0
T11	13566	380	0	0
T12	14282	816	0	0
T13	2138	44	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	917782	0	0
T1	54964	423	0	0
T2	9046	33	0	0
T3	261081	49	0	0
T7	250468	946	0	0
T8	487273	65	0	0
T9	289548	3062	0	0
T10	678689	8590	0	0
T11	13566	58	0	0
T12	14282	122	0	0
T13	2138	60	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	917782	0	0
T1	54964	423	0	0
T2	9046	33	0	0
T3	261081	49	0	0
T7	250468	946	0	0
T8	487273	65	0	0
T9	289548	3062	0	0
T10	678689	8590	0	0
T11	13566	58	0	0
T12	14282	122	0	0
T13	2138	60	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	2672446	0	0
T1	54964	655	0	0
T2	9046	70	0	0
T3	261081	67	0	0
T7	250468	1263	0	0
T8	487273	2219	0	0
T9	289548	4802	0	0
T10	678689	33210	0	0
T11	13566	88	0	0
T12	14282	220	0	0
T13	2138	77	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	917782	0	0
T1	54964	423	0	0
T2	9046	33	0	0
T3	261081	49	0	0
T7	250468	946	0	0
T8	487273	65	0	0
T9	289548	3062	0	0
T10	678689	8590	0	0
T11	13566	58	0	0
T12	14282	122	0	0
T13	2138	60	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	897961	0	0
GntImpliesValid_A	443037396	897961	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	897961	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	12611956	0	0
ReadyAndValidImplyGrant_A	443037396	897961	0	0
ReqAndReadyImplyGrant_A	443037396	897961	0	0
ReqImpliesValid_A	443037396	2616032	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	897961	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	897961	0	0
T1	54964	376	0	0
T2	9046	36	0	0
T3	261081	54	0	0
T7	250468	895	0	0
T8	487273	67	0	0
T9	289548	3060	0	0
T10	678689	5765	0	0
T11	13566	55	0	0
T12	14282	132	0	0
T13	2138	54	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	897961	0	0
T1	54964	376	0	0
T2	9046	36	0	0
T3	261081	54	0	0
T7	250468	895	0	0
T8	487273	67	0	0
T9	289548	3060	0	0
T10	678689	5765	0	0
T11	13566	55	0	0
T12	14282	132	0	0
T13	2138	54	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	897961	0	0
T1	54964	376	0	0
T2	9046	36	0	0
T3	261081	54	0	0
T7	250468	895	0	0
T8	487273	67	0	0
T9	289548	3060	0	0
T10	678689	5765	0	0
T11	13566	55	0	0
T12	14282	132	0	0
T13	2138	54	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	12611956	0	0
T1	54964	2785	0	0
T2	9046	291	0	0
T3	261081	210	0	0
T7	250468	3626	0	0
T8	487273	20578	0	0
T9	289548	21254	0	0
T10	678689	42821	0	0
T11	13566	397	0	0
T12	14282	821	0	0
T13	2138	46	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	897961	0	0
T1	54964	376	0	0
T2	9046	36	0	0
T3	261081	54	0	0
T7	250468	895	0	0
T8	487273	67	0	0
T9	289548	3060	0	0
T10	678689	5765	0	0
T11	13566	55	0	0
T12	14282	132	0	0
T13	2138	54	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	897961	0	0
T1	54964	376	0	0
T2	9046	36	0	0
T3	261081	54	0	0
T7	250468	895	0	0
T8	487273	67	0	0
T9	289548	3060	0	0
T10	678689	5765	0	0
T11	13566	55	0	0
T12	14282	132	0	0
T13	2138	54	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	2616032	0	0
T1	54964	548	0	0
T2	9046	38	0	0
T3	261081	80	0	0
T7	250468	1251	0	0
T8	487273	1750	0	0
T9	289548	4817	0	0
T10	678689	9237	0	0
T11	13566	74	0	0
T12	14282	235	0	0
T13	2138	63	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	897961	0	0
T1	54964	376	0	0
T2	9046	36	0	0
T3	261081	54	0	0
T7	250468	895	0	0
T8	487273	67	0	0
T9	289548	3060	0	0
T10	678689	5765	0	0
T11	13566	55	0	0
T12	14282	132	0	0
T13	2138	54	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	236757	0	0
GntImpliesValid_A	443037396	236757	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	236757	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	3196696	0	0
ReadyAndValidImplyGrant_A	443037396	236757	0	0
ReqAndReadyImplyGrant_A	443037396	236757	0	0
ReqImpliesValid_A	443037396	672959	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	236757	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	236757	0	0
T1	54964	98	0	0
T2	9046	14	0	0
T3	261081	14	0	0
T7	250468	230	0	0
T8	487273	9	0	0
T9	289548	1051	0	0
T10	678689	1677	0	0
T11	13566	7	0	0
T12	14282	5	0	0
T13	2138	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	236757	0	0
T1	54964	98	0	0
T2	9046	14	0	0
T3	261081	14	0	0
T7	250468	230	0	0
T8	487273	9	0	0
T9	289548	1051	0	0
T10	678689	1677	0	0
T11	13566	7	0	0
T12	14282	5	0	0
T13	2138	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	236757	0	0
T1	54964	98	0	0
T2	9046	14	0	0
T3	261081	14	0	0
T7	250468	230	0	0
T8	487273	9	0	0
T9	289548	1051	0	0
T10	678689	1677	0	0
T11	13566	7	0	0
T12	14282	5	0	0
T13	2138	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	3196696	0	0
T1	54964	708	0	0
T2	9046	116	0	0
T3	261081	66	0	0
T7	250468	974	0	0
T8	487273	2439	0	0
T9	289548	6918	0	0
T10	678689	8598	0	0
T11	13566	74	0	0
T12	14282	49	0	0
T13	2138	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	236757	0	0
T1	54964	98	0	0
T2	9046	14	0	0
T3	261081	14	0	0
T7	250468	230	0	0
T8	487273	9	0	0
T9	289548	1051	0	0
T10	678689	1677	0	0
T11	13566	7	0	0
T12	14282	5	0	0
T13	2138	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	236757	0	0
T1	54964	98	0	0
T2	9046	14	0	0
T3	261081	14	0	0
T7	250468	230	0	0
T8	487273	9	0	0
T9	289548	1051	0	0
T10	678689	1677	0	0
T11	13566	7	0	0
T12	14282	5	0	0
T13	2138	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	672959	0	0
T1	54964	129	0	0
T2	9046	14	0	0
T3	261081	14	0	0
T7	250468	270	0	0
T8	487273	9	0	0
T9	289548	2635	0	0
T10	678689	4212	0	0
T11	13566	16	0	0
T12	14282	5	0	0
T13	2138	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	236757	0	0
T1	54964	98	0	0
T2	9046	14	0	0
T3	261081	14	0	0
T7	250468	230	0	0
T8	487273	9	0	0
T9	289548	1051	0	0
T10	678689	1677	0	0
T11	13566	7	0	0
T12	14282	5	0	0
T13	2138	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	226751	0	0
GntImpliesValid_A	443037396	226751	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	226751	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	3111753	0	0
ReadyAndValidImplyGrant_A	443037396	226751	0	0
ReqAndReadyImplyGrant_A	443037396	226751	0	0
ReqImpliesValid_A	443037396	581822	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	226751	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	226751	0	0
T1	54964	91	0	0
T2	9046	10	0	0
T3	261081	13	0	0
T7	250468	223	0	0
T8	487273	4	0	0
T9	289548	1041	0	0
T10	678689	2216	0	0
T11	13566	9	0	0
T12	14282	4	0	0
T13	2138	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	226751	0	0
T1	54964	91	0	0
T2	9046	10	0	0
T3	261081	13	0	0
T7	250468	223	0	0
T8	487273	4	0	0
T9	289548	1041	0	0
T10	678689	2216	0	0
T11	13566	9	0	0
T12	14282	4	0	0
T13	2138	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	226751	0	0
T1	54964	91	0	0
T2	9046	10	0	0
T3	261081	13	0	0
T7	250468	223	0	0
T8	487273	4	0	0
T9	289548	1041	0	0
T10	678689	2216	0	0
T11	13566	9	0	0
T12	14282	4	0	0
T13	2138	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	3111753	0	0
T1	54964	720	0	0
T2	9046	85	0	0
T3	261081	49	0	0
T7	250468	929	0	0
T8	487273	1133	0	0
T9	289548	6516	0	0
T10	678689	10039	0	0
T11	13566	77	0	0
T12	14282	42	0	0
T13	2138	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	226751	0	0
T1	54964	91	0	0
T2	9046	10	0	0
T3	261081	13	0	0
T7	250468	223	0	0
T8	487273	4	0	0
T9	289548	1041	0	0
T10	678689	2216	0	0
T11	13566	9	0	0
T12	14282	4	0	0
T13	2138	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	226751	0	0
T1	54964	91	0	0
T2	9046	10	0	0
T3	261081	13	0	0
T7	250468	223	0	0
T8	487273	4	0	0
T9	289548	1041	0	0
T10	678689	2216	0	0
T11	13566	9	0	0
T12	14282	4	0	0
T13	2138	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	581822	0	0
T1	54964	111	0	0
T2	9046	14	0	0
T3	261081	19	0	0
T7	250468	260	0	0
T8	487273	4	0	0
T9	289548	3345	0	0
T10	678689	12299	0	0
T11	13566	9	0	0
T12	14282	4	0	0
T13	2138	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	226751	0	0
T1	54964	91	0	0
T2	9046	10	0	0
T3	261081	13	0	0
T7	250468	223	0	0
T8	487273	4	0	0
T9	289548	1041	0	0
T10	678689	2216	0	0
T11	13566	9	0	0
T12	14282	4	0	0
T13	2138	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	213539	0	0
GntImpliesValid_A	443037396	213539	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	213539	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	4912740	0	0
ReadyAndValidImplyGrant_A	443037396	213539	0	0
ReqAndReadyImplyGrant_A	443037396	213539	0	0
ReqImpliesValid_A	443037396	1085999	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	213539	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	213539	0	0
T1	54964	88	0	0
T2	9046	7	0	0
T3	261081	7	0	0
T7	250468	220	0	0
T8	487273	6	0	0
T9	289548	1022	0	0
T10	678689	774	0	0
T11	13566	18	0	0
T12	14282	7	0	0
T13	2138	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	213539	0	0
T1	54964	88	0	0
T2	9046	7	0	0
T3	261081	7	0	0
T7	250468	220	0	0
T8	487273	6	0	0
T9	289548	1022	0	0
T10	678689	774	0	0
T11	13566	18	0	0
T12	14282	7	0	0
T13	2138	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	213539	0	0
T1	54964	88	0	0
T2	9046	7	0	0
T3	261081	7	0	0
T7	250468	220	0	0
T8	487273	6	0	0
T9	289548	1022	0	0
T10	678689	774	0	0
T11	13566	18	0	0
T12	14282	7	0	0
T13	2138	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	4912740	0	0
T1	54964	1826	0	0
T2	9046	73	0	0
T3	261081	57	0	0
T7	250468	3869	0	0
T8	487273	2919	0	0
T9	289548	10450	0	0
T10	678689	19421	0	0
T11	13566	194	0	0
T12	14282	188	0	0
T13	2138	47	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	213539	0	0
T1	54964	88	0	0
T2	9046	7	0	0
T3	261081	7	0	0
T7	250468	220	0	0
T8	487273	6	0	0
T9	289548	1022	0	0
T10	678689	774	0	0
T11	13566	18	0	0
T12	14282	7	0	0
T13	2138	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	213539	0	0
T1	54964	88	0	0
T2	9046	7	0	0
T3	261081	7	0	0
T7	250468	220	0	0
T8	487273	6	0	0
T9	289548	1022	0	0
T10	678689	774	0	0
T11	13566	18	0	0
T12	14282	7	0	0
T13	2138	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	1085999	0	0
T1	54964	178	0	0
T2	9046	13	0	0
T3	261081	7	0	0
T7	250468	568	0	0
T8	487273	602	0	0
T9	289548	5757	0	0
T10	678689	1430	0	0
T11	13566	18	0	0
T12	14282	91	0	0
T13	2138	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	213539	0	0
T1	54964	88	0	0
T2	9046	7	0	0
T3	261081	7	0	0
T7	250468	220	0	0
T8	487273	6	0	0
T9	289548	1022	0	0
T10	678689	774	0	0
T11	13566	18	0	0
T12	14282	7	0	0
T13	2138	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	217024	0	0
GntImpliesValid_A	443037396	217024	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	217024	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	6005555	0	0
ReadyAndValidImplyGrant_A	443037396	217024	0	0
ReqAndReadyImplyGrant_A	443037396	217024	0	0
ReqImpliesValid_A	443037396	1377430	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	217024	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	217024	0	0
T1	54964	106	0	0
T2	9046	7	0	0
T3	261081	14	0	0
T7	250468	212	0	0
T8	487273	15	0	0
T9	289548	1047	0	0
T10	678689	2361	0	0
T11	13566	19	0	0
T12	14282	5	0	0
T13	2138	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	217024	0	0
T1	54964	106	0	0
T2	9046	7	0	0
T3	261081	14	0	0
T7	250468	212	0	0
T8	487273	15	0	0
T9	289548	1047	0	0
T10	678689	2361	0	0
T11	13566	19	0	0
T12	14282	5	0	0
T13	2138	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	217024	0	0
T1	54964	106	0	0
T2	9046	7	0	0
T3	261081	14	0	0
T7	250468	212	0	0
T8	487273	15	0	0
T9	289548	1047	0	0
T10	678689	2361	0	0
T11	13566	19	0	0
T12	14282	5	0	0
T13	2138	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	6005555	0	0
T1	54964	4052	0	0
T2	9046	95	0	0
T3	261081	170	0	0
T7	250468	2919	0	0
T8	487273	4991	0	0
T9	289548	20036	0	0
T10	678689	23010	0	0
T11	13566	389	0	0
T12	14282	50	0	0
T13	2138	136	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	217024	0	0
T1	54964	106	0	0
T2	9046	7	0	0
T3	261081	14	0	0
T7	250468	212	0	0
T8	487273	15	0	0
T9	289548	1047	0	0
T10	678689	2361	0	0
T11	13566	19	0	0
T12	14282	5	0	0
T13	2138	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	217024	0	0
T1	54964	106	0	0
T2	9046	7	0	0
T3	261081	14	0	0
T7	250468	212	0	0
T8	487273	15	0	0
T9	289548	1047	0	0
T10	678689	2361	0	0
T11	13566	19	0	0
T12	14282	5	0	0
T13	2138	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	1377430	0	0
T1	54964	416	0	0
T2	9046	7	0	0
T3	261081	20	0	0
T7	250468	413	0	0
T8	487273	103	0	0
T9	289548	4054	0	0
T10	678689	19847	0	0
T11	13566	50	0	0
T12	14282	5	0	0
T13	2138	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	217024	0	0
T1	54964	106	0	0
T2	9046	7	0	0
T3	261081	14	0	0
T7	250468	212	0	0
T8	487273	15	0	0
T9	289548	1047	0	0
T10	678689	2361	0	0
T11	13566	19	0	0
T12	14282	5	0	0
T13	2138	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	218788	0	0
GntImpliesValid_A	443037396	218788	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	218788	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	5518313	0	0
ReadyAndValidImplyGrant_A	443037396	218788	0	0
ReqAndReadyImplyGrant_A	443037396	218788	0	0
ReqImpliesValid_A	443037396	1250626	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	218788	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	218788	0	0
T1	54964	96	0	0
T2	9046	11	0	0
T3	261081	7	0	0
T7	250468	251	0	0
T8	487273	14	0	0
T9	289548	1079	0	0
T10	678689	2039	0	0
T11	13566	14	0	0
T12	14282	3	0	0
T13	2138	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	218788	0	0
T1	54964	96	0	0
T2	9046	11	0	0
T3	261081	7	0	0
T7	250468	251	0	0
T8	487273	14	0	0
T9	289548	1079	0	0
T10	678689	2039	0	0
T11	13566	14	0	0
T12	14282	3	0	0
T13	2138	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	218788	0	0
T1	54964	96	0	0
T2	9046	11	0	0
T3	261081	7	0	0
T7	250468	251	0	0
T8	487273	14	0	0
T9	289548	1079	0	0
T10	678689	2039	0	0
T11	13566	14	0	0
T12	14282	3	0	0
T13	2138	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	5518313	0	0
T1	54964	1455	0	0
T2	9046	337	0	0
T3	261081	54	0	0
T7	250468	4101	0	0
T8	487273	18773	0	0
T9	289548	9936	0	0
T10	678689	15641	0	0
T11	13566	248	0	0
T12	14282	42	0	0
T13	2138	97	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	218788	0	0
T1	54964	96	0	0
T2	9046	11	0	0
T3	261081	7	0	0
T7	250468	251	0	0
T8	487273	14	0	0
T9	289548	1079	0	0
T10	678689	2039	0	0
T11	13566	14	0	0
T12	14282	3	0	0
T13	2138	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	218788	0	0
T1	54964	96	0	0
T2	9046	11	0	0
T3	261081	7	0	0
T7	250468	251	0	0
T8	487273	14	0	0
T9	289548	1079	0	0
T10	678689	2039	0	0
T11	13566	14	0	0
T12	14282	3	0	0
T13	2138	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	1250626	0	0
T1	54964	171	0	0
T2	9046	62	0	0
T3	261081	12	0	0
T7	250468	746	0	0
T8	487273	2628	0	0
T9	289548	12937	0	0
T10	678689	10727	0	0
T11	13566	14	0	0
T12	14282	3	0	0
T13	2138	23	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	218788	0	0
T1	54964	96	0	0
T2	9046	11	0	0
T3	261081	7	0	0
T7	250468	251	0	0
T8	487273	14	0	0
T9	289548	1079	0	0
T10	678689	2039	0	0
T11	13566	14	0	0
T12	14282	3	0	0
T13	2138	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	208810	0	0
GntImpliesValid_A	443037396	208810	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	208810	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	6449982	0	0
ReadyAndValidImplyGrant_A	443037396	208810	0	0
ReqAndReadyImplyGrant_A	443037396	208810	0	0
ReqImpliesValid_A	443037396	1409615	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	208810	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	208810	0	0
T1	54964	95	0	0
T2	9046	8	0	0
T3	261081	10	0	0
T7	250468	226	0	0
T8	487273	21	0	0
T9	289548	1005	0	0
T10	678689	1295	0	0
T11	13566	13	0	0
T12	14282	6	0	0
T13	2138	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	208810	0	0
T1	54964	95	0	0
T2	9046	8	0	0
T3	261081	10	0	0
T7	250468	226	0	0
T8	487273	21	0	0
T9	289548	1005	0	0
T10	678689	1295	0	0
T11	13566	13	0	0
T12	14282	6	0	0
T13	2138	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	208810	0	0
T1	54964	95	0	0
T2	9046	8	0	0
T3	261081	10	0	0
T7	250468	226	0	0
T8	487273	21	0	0
T9	289548	1005	0	0
T10	678689	1295	0	0
T11	13566	13	0	0
T12	14282	6	0	0
T13	2138	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	6449982	0	0
T1	54964	4865	0	0
T2	9046	108	0	0
T3	261081	222	0	0
T7	250468	2077	0	0
T8	487273	17751	0	0
T9	289548	9019	0	0
T10	678689	11332	0	0
T11	13566	585	0	0
T12	14282	313	0	0
T13	2138	54	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	208810	0	0
T1	54964	95	0	0
T2	9046	8	0	0
T3	261081	10	0	0
T7	250468	226	0	0
T8	487273	21	0	0
T9	289548	1005	0	0
T10	678689	1295	0	0
T11	13566	13	0	0
T12	14282	6	0	0
T13	2138	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	208810	0	0
T1	54964	95	0	0
T2	9046	8	0	0
T3	261081	10	0	0
T7	250468	226	0	0
T8	487273	21	0	0
T9	289548	1005	0	0
T10	678689	1295	0	0
T11	13566	13	0	0
T12	14282	6	0	0
T13	2138	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	1409615	0	0
T1	54964	474	0	0
T2	9046	8	0	0
T3	261081	11	0	0
T7	250468	377	0	0
T8	487273	3165	0	0
T9	289548	9209	0	0
T10	678689	7720	0	0
T11	13566	24	0	0
T12	14282	27	0	0
T13	2138	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	208810	0	0
T1	54964	95	0	0
T2	9046	8	0	0
T3	261081	10	0	0
T7	250468	226	0	0
T8	487273	21	0	0
T9	289548	1005	0	0
T10	678689	1295	0	0
T11	13566	13	0	0
T12	14282	6	0	0
T13	2138	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	223018	0	0
GntImpliesValid_A	443037396	223018	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	223018	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	3176868	0	0
ReadyAndValidImplyGrant_A	443037396	223018	0	0
ReqAndReadyImplyGrant_A	443037396	223018	0	0
ReqImpliesValid_A	443037396	605877	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	223018	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	223018	0	0
T1	54964	118	0	0
T2	9046	15	0	0
T3	261081	10	0	0
T7	250468	218	0	0
T8	487273	12	0	0
T9	289548	532	0	0
T10	678689	2932	0	0
T11	13566	15	0	0
T12	14282	7	0	0
T13	2138	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	223018	0	0
T1	54964	118	0	0
T2	9046	15	0	0
T3	261081	10	0	0
T7	250468	218	0	0
T8	487273	12	0	0
T9	289548	532	0	0
T10	678689	2932	0	0
T11	13566	15	0	0
T12	14282	7	0	0
T13	2138	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	223018	0	0
T1	54964	118	0	0
T2	9046	15	0	0
T3	261081	10	0	0
T7	250468	218	0	0
T8	487273	12	0	0
T9	289548	532	0	0
T10	678689	2932	0	0
T11	13566	15	0	0
T12	14282	7	0	0
T13	2138	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	3176868	0	0
T1	54964	980	0	0
T2	9046	110	0	0
T3	261081	37	0	0
T7	250468	926	0	0
T8	487273	3477	0	0
T9	289548	4155	0	0
T10	678689	12425	0	0
T11	13566	113	0	0
T12	14282	45	0	0
T13	2138	7	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	223018	0	0
T1	54964	118	0	0
T2	9046	15	0	0
T3	261081	10	0	0
T7	250468	218	0	0
T8	487273	12	0	0
T9	289548	532	0	0
T10	678689	2932	0	0
T11	13566	15	0	0
T12	14282	7	0	0
T13	2138	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	223018	0	0
T1	54964	118	0	0
T2	9046	15	0	0
T3	261081	10	0	0
T7	250468	218	0	0
T8	487273	12	0	0
T9	289548	532	0	0
T10	678689	2932	0	0
T11	13566	15	0	0
T12	14282	7	0	0
T13	2138	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	605877	0	0
T1	54964	169	0	0
T2	9046	15	0	0
T3	261081	10	0	0
T7	250468	284	0	0
T8	487273	12	0	0
T9	289548	630	0	0
T10	678689	8708	0	0
T11	13566	19	0	0
T12	14282	11	0	0
T13	2138	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	223018	0	0
T1	54964	118	0	0
T2	9046	15	0	0
T3	261081	10	0	0
T7	250468	218	0	0
T8	487273	12	0	0
T9	289548	532	0	0
T10	678689	2932	0	0
T11	13566	15	0	0
T12	14282	7	0	0
T13	2138	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	227019	0	0
GntImpliesValid_A	443037396	227019	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	227019	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	3098001	0	0
ReadyAndValidImplyGrant_A	443037396	227019	0	0
ReqAndReadyImplyGrant_A	443037396	227019	0	0
ReqImpliesValid_A	443037396	624193	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	227019	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	227019	0	0
T1	54964	101	0	0
T2	9046	13	0	0
T3	261081	11	0	0
T7	250468	247	0	0
T8	487273	7	0	0
T9	289548	1107	0	0
T10	678689	2350	0	0
T11	13566	23	0	0
T12	14282	7	0	0
T13	2138	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	227019	0	0
T1	54964	101	0	0
T2	9046	13	0	0
T3	261081	11	0	0
T7	250468	247	0	0
T8	487273	7	0	0
T9	289548	1107	0	0
T10	678689	2350	0	0
T11	13566	23	0	0
T12	14282	7	0	0
T13	2138	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	227019	0	0
T1	54964	101	0	0
T2	9046	13	0	0
T3	261081	11	0	0
T7	250468	247	0	0
T8	487273	7	0	0
T9	289548	1107	0	0
T10	678689	2350	0	0
T11	13566	23	0	0
T12	14282	7	0	0
T13	2138	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	3098001	0	0
T1	54964	733	0	0
T2	9046	106	0	0
T3	261081	58	0	0
T7	250468	1023	0	0
T8	487273	1880	0	0
T9	289548	7501	0	0
T10	678689	10337	0	0
T11	13566	209	0	0
T12	14282	63	0	0
T13	2138	7	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	227019	0	0
T1	54964	101	0	0
T2	9046	13	0	0
T3	261081	11	0	0
T7	250468	247	0	0
T8	487273	7	0	0
T9	289548	1107	0	0
T10	678689	2350	0	0
T11	13566	23	0	0
T12	14282	7	0	0
T13	2138	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	227019	0	0
T1	54964	101	0	0
T2	9046	13	0	0
T3	261081	11	0	0
T7	250468	247	0	0
T8	487273	7	0	0
T9	289548	1107	0	0
T10	678689	2350	0	0
T11	13566	23	0	0
T12	14282	7	0	0
T13	2138	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	624193	0	0
T1	54964	132	0	0
T2	9046	22	0	0
T3	261081	11	0	0
T7	250468	292	0	0
T8	487273	7	0	0
T9	289548	2696	0	0
T10	678689	6571	0	0
T11	13566	32	0	0
T12	14282	7	0	0
T13	2138	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	227019	0	0
T1	54964	101	0	0
T2	9046	13	0	0
T3	261081	11	0	0
T7	250468	247	0	0
T8	487273	7	0	0
T9	289548	1107	0	0
T10	678689	2350	0	0
T11	13566	23	0	0
T12	14282	7	0	0
T13	2138	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	237408	0	0
GntImpliesValid_A	443037396	237408	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	237408	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	3135932	0	0
ReadyAndValidImplyGrant_A	443037396	237408	0	0
ReqAndReadyImplyGrant_A	443037396	237408	0	0
ReqImpliesValid_A	443037396	651230	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	237408	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	237408	0	0
T1	54964	107	0	0
T2	9046	7	0	0
T3	261081	10	0	0
T7	250468	245	0	0
T8	487273	7	0	0
T9	289548	936	0	0
T10	678689	1732	0	0
T11	13566	19	0	0
T12	14282	6	0	0
T13	2138	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	237408	0	0
T1	54964	107	0	0
T2	9046	7	0	0
T3	261081	10	0	0
T7	250468	245	0	0
T8	487273	7	0	0
T9	289548	936	0	0
T10	678689	1732	0	0
T11	13566	19	0	0
T12	14282	6	0	0
T13	2138	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	237408	0	0
T1	54964	107	0	0
T2	9046	7	0	0
T3	261081	10	0	0
T7	250468	245	0	0
T8	487273	7	0	0
T9	289548	936	0	0
T10	678689	1732	0	0
T11	13566	19	0	0
T12	14282	6	0	0
T13	2138	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	3135932	0	0
T1	54964	717	0	0
T2	9046	56	0	0
T3	261081	38	0	0
T7	250468	1040	0	0
T8	487273	1544	0	0
T9	289548	4356	0	0
T10	678689	8816	0	0
T11	13566	165	0	0
T12	14282	33	0	0
T13	2138	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	237408	0	0
T1	54964	107	0	0
T2	9046	7	0	0
T3	261081	10	0	0
T7	250468	245	0	0
T8	487273	7	0	0
T9	289548	936	0	0
T10	678689	1732	0	0
T11	13566	19	0	0
T12	14282	6	0	0
T13	2138	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	237408	0	0
T1	54964	107	0	0
T2	9046	7	0	0
T3	261081	10	0	0
T7	250468	245	0	0
T8	487273	7	0	0
T9	289548	936	0	0
T10	678689	1732	0	0
T11	13566	19	0	0
T12	14282	6	0	0
T13	2138	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	651230	0	0
T1	54964	178	0	0
T2	9046	7	0	0
T3	261081	10	0	0
T7	250468	273	0	0
T8	487273	7	0	0
T9	289548	5061	0	0
T10	678689	4236	0	0
T11	13566	30	0	0
T12	14282	6	0	0
T13	2138	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	237408	0	0
T1	54964	107	0	0
T2	9046	7	0	0
T3	261081	10	0	0
T7	250468	245	0	0
T8	487273	7	0	0
T9	289548	936	0	0
T10	678689	1732	0	0
T11	13566	19	0	0
T12	14282	6	0	0
T13	2138	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	218659	0	0
GntImpliesValid_A	443037396	218659	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	218659	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	3099619	0	0
ReadyAndValidImplyGrant_A	443037396	218659	0	0
ReqAndReadyImplyGrant_A	443037396	218659	0	0
ReqImpliesValid_A	443037396	593011	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	218659	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	218659	0	0
T1	54964	109	0	0
T2	9046	12	0	0
T3	261081	13	0	0
T7	250468	262	0	0
T8	487273	11	0	0
T9	289548	505	0	0
T10	678689	2210	0	0
T11	13566	9	0	0
T12	14282	3	0	0
T13	2138	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	218659	0	0
T1	54964	109	0	0
T2	9046	12	0	0
T3	261081	13	0	0
T7	250468	262	0	0
T8	487273	11	0	0
T9	289548	505	0	0
T10	678689	2210	0	0
T11	13566	9	0	0
T12	14282	3	0	0
T13	2138	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	218659	0	0
T1	54964	109	0	0
T2	9046	12	0	0
T3	261081	13	0	0
T7	250468	262	0	0
T8	487273	11	0	0
T9	289548	505	0	0
T10	678689	2210	0	0
T11	13566	9	0	0
T12	14282	3	0	0
T13	2138	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	3099619	0	0
T1	54964	880	0	0
T2	9046	85	0	0
T3	261081	68	0	0
T7	250468	1026	0	0
T8	487273	3919	0	0
T9	289548	3758	0	0
T10	678689	10355	0	0
T11	13566	54	0	0
T12	14282	26	0	0
T13	2138	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	218659	0	0
T1	54964	109	0	0
T2	9046	12	0	0
T3	261081	13	0	0
T7	250468	262	0	0
T8	487273	11	0	0
T9	289548	505	0	0
T10	678689	2210	0	0
T11	13566	9	0	0
T12	14282	3	0	0
T13	2138	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	218659	0	0
T1	54964	109	0	0
T2	9046	12	0	0
T3	261081	13	0	0
T7	250468	262	0	0
T8	487273	11	0	0
T9	289548	505	0	0
T10	678689	2210	0	0
T11	13566	9	0	0
T12	14282	3	0	0
T13	2138	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	593011	0	0
T1	54964	126	0	0
T2	9046	23	0	0
T3	261081	15	0	0
T7	250468	337	0	0
T8	487273	148	0	0
T9	289548	628	0	0
T10	678689	6067	0	0
T11	13566	9	0	0
T12	14282	3	0	0
T13	2138	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	218659	0	0
T1	54964	109	0	0
T2	9046	12	0	0
T3	261081	13	0	0
T7	250468	262	0	0
T8	487273	11	0	0
T9	289548	505	0	0
T10	678689	2210	0	0
T11	13566	9	0	0
T12	14282	3	0	0
T13	2138	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	222850	0	0
GntImpliesValid_A	443037396	222850	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	222850	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	3066058	0	0
ReadyAndValidImplyGrant_A	443037396	222850	0	0
ReqAndReadyImplyGrant_A	443037396	222850	0	0
ReqImpliesValid_A	443037396	588470	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	222850	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	222850	0	0
T1	54964	103	0	0
T2	9046	13	0	0
T3	261081	13	0	0
T7	250468	223	0	0
T8	487273	12	0	0
T9	289548	1103	0	0
T10	678689	2671	0	0
T11	13566	14	0	0
T12	14282	214	0	0
T13	2138	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	222850	0	0
T1	54964	103	0	0
T2	9046	13	0	0
T3	261081	13	0	0
T7	250468	223	0	0
T8	487273	12	0	0
T9	289548	1103	0	0
T10	678689	2671	0	0
T11	13566	14	0	0
T12	14282	214	0	0
T13	2138	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	222850	0	0
T1	54964	103	0	0
T2	9046	13	0	0
T3	261081	13	0	0
T7	250468	223	0	0
T8	487273	12	0	0
T9	289548	1103	0	0
T10	678689	2671	0	0
T11	13566	14	0	0
T12	14282	214	0	0
T13	2138	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	3066058	0	0
T1	54964	774	0	0
T2	9046	126	0	0
T3	261081	59	0	0
T7	250468	942	0	0
T8	487273	4209	0	0
T9	289548	7927	0	0
T10	678689	12269	0	0
T11	13566	92	0	0
T12	14282	212	0	0
T13	2138	8	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	222850	0	0
T1	54964	103	0	0
T2	9046	13	0	0
T3	261081	13	0	0
T7	250468	223	0	0
T8	487273	12	0	0
T9	289548	1103	0	0
T10	678689	2671	0	0
T11	13566	14	0	0
T12	14282	214	0	0
T13	2138	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	222850	0	0
T1	54964	103	0	0
T2	9046	13	0	0
T3	261081	13	0	0
T7	250468	223	0	0
T8	487273	12	0	0
T9	289548	1103	0	0
T10	678689	2671	0	0
T11	13566	14	0	0
T12	14282	214	0	0
T13	2138	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	588470	0	0
T1	54964	113	0	0
T2	9046	14	0	0
T3	261081	13	0	0
T7	250468	289	0	0
T8	487273	626	0	0
T9	289548	2259	0	0
T10	678689	15066	0	0
T11	13566	14	0	0
T12	14282	2115	0	0
T13	2138	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	222850	0	0
T1	54964	103	0	0
T2	9046	13	0	0
T3	261081	13	0	0
T7	250468	223	0	0
T8	487273	12	0	0
T9	289548	1103	0	0
T10	678689	2671	0	0
T11	13566	14	0	0
T12	14282	214	0	0
T13	2138	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	228125	0	0
GntImpliesValid_A	443037396	228125	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	228125	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	3131907	0	0
ReadyAndValidImplyGrant_A	443037396	228125	0	0
ReqAndReadyImplyGrant_A	443037396	228125	0	0
ReqImpliesValid_A	443037396	626092	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	228125	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	228125	0	0
T1	54964	82	0	0
T2	9046	9	0	0
T3	261081	16	0	0
T7	250468	257	0	0
T8	487273	14	0	0
T9	289548	785	0	0
T10	678689	1283	0	0
T11	13566	19	0	0
T12	14282	7	0	0
T13	2138	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	228125	0	0
T1	54964	82	0	0
T2	9046	9	0	0
T3	261081	16	0	0
T7	250468	257	0	0
T8	487273	14	0	0
T9	289548	785	0	0
T10	678689	1283	0	0
T11	13566	19	0	0
T12	14282	7	0	0
T13	2138	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	228125	0	0
T1	54964	82	0	0
T2	9046	9	0	0
T3	261081	16	0	0
T7	250468	257	0	0
T8	487273	14	0	0
T9	289548	785	0	0
T10	678689	1283	0	0
T11	13566	19	0	0
T12	14282	7	0	0
T13	2138	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	3131907	0	0
T1	54964	663	0	0
T2	9046	66	0	0
T3	261081	75	0	0
T7	250468	1030	0	0
T8	487273	5557	0	0
T9	289548	5931	0	0
T10	678689	8625	0	0
T11	13566	127	0	0
T12	14282	60	0	0
T13	2138	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	228125	0	0
T1	54964	82	0	0
T2	9046	9	0	0
T3	261081	16	0	0
T7	250468	257	0	0
T8	487273	14	0	0
T9	289548	785	0	0
T10	678689	1283	0	0
T11	13566	19	0	0
T12	14282	7	0	0
T13	2138	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	228125	0	0
T1	54964	82	0	0
T2	9046	9	0	0
T3	261081	16	0	0
T7	250468	257	0	0
T8	487273	14	0	0
T9	289548	785	0	0
T10	678689	1283	0	0
T11	13566	19	0	0
T12	14282	7	0	0
T13	2138	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	626092	0	0
T1	54964	127	0	0
T2	9046	9	0	0
T3	261081	18	0	0
T7	250468	282	0	0
T8	487273	1275	0	0
T9	289548	1167	0	0
T10	678689	3370	0	0
T11	13566	37	0	0
T12	14282	7	0	0
T13	2138	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	228125	0	0
T1	54964	82	0	0
T2	9046	9	0	0
T3	261081	16	0	0
T7	250468	257	0	0
T8	487273	14	0	0
T9	289548	785	0	0
T10	678689	1283	0	0
T11	13566	19	0	0
T12	14282	7	0	0
T13	2138	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	229357	0	0
GntImpliesValid_A	443037396	229357	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	229357	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	3147475	0	0
ReadyAndValidImplyGrant_A	443037396	229357	0	0
ReqAndReadyImplyGrant_A	443037396	229357	0	0
ReqImpliesValid_A	443037396	620314	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	229357	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	229357	0	0
T1	54964	109	0	0
T2	9046	10	0	0
T3	261081	19	0	0
T7	250468	198	0	0
T8	487273	11	0	0
T9	289548	533	0	0
T10	678689	2209	0	0
T11	13566	16	0	0
T12	14282	54	0	0
T13	2138	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	229357	0	0
T1	54964	109	0	0
T2	9046	10	0	0
T3	261081	19	0	0
T7	250468	198	0	0
T8	487273	11	0	0
T9	289548	533	0	0
T10	678689	2209	0	0
T11	13566	16	0	0
T12	14282	54	0	0
T13	2138	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	229357	0	0
T1	54964	109	0	0
T2	9046	10	0	0
T3	261081	19	0	0
T7	250468	198	0	0
T8	487273	11	0	0
T9	289548	533	0	0
T10	678689	2209	0	0
T11	13566	16	0	0
T12	14282	54	0	0
T13	2138	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	3147475	0	0
T1	54964	814	0	0
T2	9046	71	0	0
T3	261081	82	0	0
T7	250468	880	0	0
T8	487273	3299	0	0
T9	289548	3818	0	0
T10	678689	11817	0	0
T11	13566	94	0	0
T12	14282	265	0	0
T13	2138	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	229357	0	0
T1	54964	109	0	0
T2	9046	10	0	0
T3	261081	19	0	0
T7	250468	198	0	0
T8	487273	11	0	0
T9	289548	533	0	0
T10	678689	2209	0	0
T11	13566	16	0	0
T12	14282	54	0	0
T13	2138	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	229357	0	0
T1	54964	109	0	0
T2	9046	10	0	0
T3	261081	19	0	0
T7	250468	198	0	0
T8	487273	11	0	0
T9	289548	533	0	0
T10	678689	2209	0	0
T11	13566	16	0	0
T12	14282	54	0	0
T13	2138	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	620314	0	0
T1	54964	121	0	0
T2	9046	10	0	0
T3	261081	26	0	0
T7	250468	241	0	0
T8	487273	800	0	0
T9	289548	638	0	0
T10	678689	10015	0	0
T11	13566	16	0	0
T12	14282	135	0	0
T13	2138	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	229357	0	0
T1	54964	109	0	0
T2	9046	10	0	0
T3	261081	19	0	0
T7	250468	198	0	0
T8	487273	11	0	0
T9	289548	533	0	0
T10	678689	2209	0	0
T11	13566	16	0	0
T12	14282	54	0	0
T13	2138	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	233871	0	0
GntImpliesValid_A	443037396	233871	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	233871	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	3185328	0	0
ReadyAndValidImplyGrant_A	443037396	233871	0	0
ReqAndReadyImplyGrant_A	443037396	233871	0	0
ReqImpliesValid_A	443037396	654246	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	233871	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	233871	0	0
T1	54964	98	0	0
T2	9046	9	0	0
T3	261081	14	0	0
T7	250468	224	0	0
T8	487273	11	0	0
T9	289548	1317	0	0
T10	678689	1979	0	0
T11	13566	14	0	0
T12	14282	11	0	0
T13	2138	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	233871	0	0
T1	54964	98	0	0
T2	9046	9	0	0
T3	261081	14	0	0
T7	250468	224	0	0
T8	487273	11	0	0
T9	289548	1317	0	0
T10	678689	1979	0	0
T11	13566	14	0	0
T12	14282	11	0	0
T13	2138	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	233871	0	0
T1	54964	98	0	0
T2	9046	9	0	0
T3	261081	14	0	0
T7	250468	224	0	0
T8	487273	11	0	0
T9	289548	1317	0	0
T10	678689	1979	0	0
T11	13566	14	0	0
T12	14282	11	0	0
T13	2138	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	3185328	0	0
T1	54964	679	0	0
T2	9046	39	0	0
T3	261081	65	0	0
T7	250468	933	0	0
T8	487273	3905	0	0
T9	289548	6824	0	0
T10	678689	9247	0	0
T11	13566	134	0	0
T12	14282	75	0	0
T13	2138	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	233871	0	0
T1	54964	98	0	0
T2	9046	9	0	0
T3	261081	14	0	0
T7	250468	224	0	0
T8	487273	11	0	0
T9	289548	1317	0	0
T10	678689	1979	0	0
T11	13566	14	0	0
T12	14282	11	0	0
T13	2138	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	233871	0	0
T1	54964	98	0	0
T2	9046	9	0	0
T3	261081	14	0	0
T7	250468	224	0	0
T8	487273	11	0	0
T9	289548	1317	0	0
T10	678689	1979	0	0
T11	13566	14	0	0
T12	14282	11	0	0
T13	2138	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	654246	0	0
T1	54964	175	0	0
T2	9046	9	0	0
T3	261081	15	0	0
T7	250468	278	0	0
T8	487273	434	0	0
T9	289548	6125	0	0
T10	678689	10636	0	0
T11	13566	16	0	0
T12	14282	11	0	0
T13	2138	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	233871	0	0
T1	54964	98	0	0
T2	9046	9	0	0
T3	261081	14	0	0
T7	250468	224	0	0
T8	487273	11	0	0
T9	289548	1317	0	0
T10	678689	1979	0	0
T11	13566	14	0	0
T12	14282	11	0	0
T13	2138	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	237872	0	0
GntImpliesValid_A	443037396	237872	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	237872	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	3210233	0	0
ReadyAndValidImplyGrant_A	443037396	237872	0	0
ReqAndReadyImplyGrant_A	443037396	237872	0	0
ReqImpliesValid_A	443037396	634293	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	237872	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	237872	0	0
T1	54964	189	0	0
T2	9046	10	0	0
T3	261081	8	0	0
T7	250468	221	0	0
T8	487273	14	0	0
T9	289548	664	0	0
T10	678689	1275	0	0
T11	13566	15	0	0
T12	14282	513	0	0
T13	2138	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	237872	0	0
T1	54964	189	0	0
T2	9046	10	0	0
T3	261081	8	0	0
T7	250468	221	0	0
T8	487273	14	0	0
T9	289548	664	0	0
T10	678689	1275	0	0
T11	13566	15	0	0
T12	14282	513	0	0
T13	2138	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	237872	0	0
T1	54964	189	0	0
T2	9046	10	0	0
T3	261081	8	0	0
T7	250468	221	0	0
T8	487273	14	0	0
T9	289548	664	0	0
T10	678689	1275	0	0
T11	13566	15	0	0
T12	14282	513	0	0
T13	2138	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	3210233	0	0
T1	54964	1400	0	0
T2	9046	58	0	0
T3	261081	37	0	0
T7	250468	925	0	0
T8	487273	4332	0	0
T9	289548	5172	0	0
T10	678689	7098	0	0
T11	13566	118	0	0
T12	14282	816	0	0
T13	2138	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	237872	0	0
T1	54964	189	0	0
T2	9046	10	0	0
T3	261081	8	0	0
T7	250468	221	0	0
T8	487273	14	0	0
T9	289548	664	0	0
T10	678689	1275	0	0
T11	13566	15	0	0
T12	14282	513	0	0
T13	2138	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	237872	0	0
T1	54964	189	0	0
T2	9046	10	0	0
T3	261081	8	0	0
T7	250468	221	0	0
T8	487273	14	0	0
T9	289548	664	0	0
T10	678689	1275	0	0
T11	13566	15	0	0
T12	14282	513	0	0
T13	2138	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	634293	0	0
T1	54964	266	0	0
T2	9046	18	0	0
T3	261081	8	0	0
T7	250468	254	0	0
T8	487273	14	0	0
T9	289548	829	0	0
T10	678689	5230	0	0
T11	13566	16	0	0
T12	14282	5049	0	0
T13	2138	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	237872	0	0
T1	54964	189	0	0
T2	9046	10	0	0
T3	261081	8	0	0
T7	250468	221	0	0
T8	487273	14	0	0
T9	289548	664	0	0
T10	678689	1275	0	0
T11	13566	15	0	0
T12	14282	513	0	0
T13	2138	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	208515	0	0
GntImpliesValid_A	443037396	208515	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	208515	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	3108043	0	0
ReadyAndValidImplyGrant_A	443037396	208515	0	0
ReqAndReadyImplyGrant_A	443037396	208515	0	0
ReqImpliesValid_A	443037396	517910	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	208515	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	208515	0	0
T1	54964	103	0	0
T2	9046	9	0	0
T3	261081	17	0	0
T7	250468	225	0	0
T8	487273	12	0	0
T9	289548	1056	0	0
T10	678689	1696	0	0
T11	13566	15	0	0
T12	14282	5	0	0
T13	2138	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	208515	0	0
T1	54964	103	0	0
T2	9046	9	0	0
T3	261081	17	0	0
T7	250468	225	0	0
T8	487273	12	0	0
T9	289548	1056	0	0
T10	678689	1696	0	0
T11	13566	15	0	0
T12	14282	5	0	0
T13	2138	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	208515	0	0
T1	54964	103	0	0
T2	9046	9	0	0
T3	261081	17	0	0
T7	250468	225	0	0
T8	487273	12	0	0
T9	289548	1056	0	0
T10	678689	1696	0	0
T11	13566	15	0	0
T12	14282	5	0	0
T13	2138	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	3108043	0	0
T1	54964	812	0	0
T2	9046	54	0	0
T3	261081	63	0	0
T7	250468	973	0	0
T8	487273	2904	0	0
T9	289548	7060	0	0
T10	678689	10028	0	0
T11	13566	118	0	0
T12	14282	37	0	0
T13	2138	17	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	208515	0	0
T1	54964	103	0	0
T2	9046	9	0	0
T3	261081	17	0	0
T7	250468	225	0	0
T8	487273	12	0	0
T9	289548	1056	0	0
T10	678689	1696	0	0
T11	13566	15	0	0
T12	14282	5	0	0
T13	2138	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	208515	0	0
T1	54964	103	0	0
T2	9046	9	0	0
T3	261081	17	0	0
T7	250468	225	0	0
T8	487273	12	0	0
T9	289548	1056	0	0
T10	678689	1696	0	0
T11	13566	15	0	0
T12	14282	5	0	0
T13	2138	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	517910	0	0
T1	54964	129	0	0
T2	9046	9	0	0
T3	261081	25	0	0
T7	250468	269	0	0
T8	487273	12	0	0
T9	289548	1909	0	0
T10	678689	6313	0	0
T11	13566	15	0	0
T12	14282	5	0	0
T13	2138	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	208515	0	0
T1	54964	103	0	0
T2	9046	9	0	0
T3	261081	17	0	0
T7	250468	225	0	0
T8	487273	12	0	0
T9	289548	1056	0	0
T10	678689	1696	0	0
T11	13566	15	0	0
T12	14282	5	0	0
T13	2138	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	228010	0	0
GntImpliesValid_A	443037396	228010	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	228010	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	3106161	0	0
ReadyAndValidImplyGrant_A	443037396	228010	0	0
ReqAndReadyImplyGrant_A	443037396	228010	0	0
ReqImpliesValid_A	443037396	628411	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	228010	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	228010	0	0
T1	54964	93	0	0
T2	9046	14	0	0
T3	261081	11	0	0
T7	250468	221	0	0
T8	487273	14	0	0
T9	289548	806	0	0
T10	678689	1226	0	0
T11	13566	19	0	0
T12	14282	5	0	0
T13	2138	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	228010	0	0
T1	54964	93	0	0
T2	9046	14	0	0
T3	261081	11	0	0
T7	250468	221	0	0
T8	487273	14	0	0
T9	289548	806	0	0
T10	678689	1226	0	0
T11	13566	19	0	0
T12	14282	5	0	0
T13	2138	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	228010	0	0
T1	54964	93	0	0
T2	9046	14	0	0
T3	261081	11	0	0
T7	250468	221	0	0
T8	487273	14	0	0
T9	289548	806	0	0
T10	678689	1226	0	0
T11	13566	19	0	0
T12	14282	5	0	0
T13	2138	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	3106161	0	0
T1	54964	646	0	0
T2	9046	82	0	0
T3	261081	47	0	0
T7	250468	909	0	0
T8	487273	4344	0	0
T9	289548	5776	0	0
T10	678689	6424	0	0
T11	13566	167	0	0
T12	14282	60	0	0
T13	2138	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	228010	0	0
T1	54964	93	0	0
T2	9046	14	0	0
T3	261081	11	0	0
T7	250468	221	0	0
T8	487273	14	0	0
T9	289548	806	0	0
T10	678689	1226	0	0
T11	13566	19	0	0
T12	14282	5	0	0
T13	2138	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	228010	0	0
T1	54964	93	0	0
T2	9046	14	0	0
T3	261081	11	0	0
T7	250468	221	0	0
T8	487273	14	0	0
T9	289548	806	0	0
T10	678689	1226	0	0
T11	13566	19	0	0
T12	14282	5	0	0
T13	2138	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	628411	0	0
T1	54964	116	0	0
T2	9046	14	0	0
T3	261081	11	0	0
T7	250468	288	0	0
T8	487273	14	0	0
T9	289548	1493	0	0
T10	678689	5308	0	0
T11	13566	19	0	0
T12	14282	5	0	0
T13	2138	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	228010	0	0
T1	54964	93	0	0
T2	9046	14	0	0
T3	261081	11	0	0
T7	250468	221	0	0
T8	487273	14	0	0
T9	289548	806	0	0
T10	678689	1226	0	0
T11	13566	19	0	0
T12	14282	5	0	0
T13	2138	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	226455	0	0
GntImpliesValid_A	443037396	226455	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	226455	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	3100090	0	0
ReadyAndValidImplyGrant_A	443037396	226455	0	0
ReqAndReadyImplyGrant_A	443037396	226455	0	0
ReqImpliesValid_A	443037396	569391	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	226455	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	226455	0	0
T1	54964	99	0	0
T2	9046	22	0	0
T3	261081	21	0	0
T7	250468	208	0	0
T8	487273	10	0	0
T9	289548	487	0	0
T10	678689	1252	0	0
T11	13566	22	0	0
T12	14282	46	0	0
T13	2138	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	226455	0	0
T1	54964	99	0	0
T2	9046	22	0	0
T3	261081	21	0	0
T7	250468	208	0	0
T8	487273	10	0	0
T9	289548	487	0	0
T10	678689	1252	0	0
T11	13566	22	0	0
T12	14282	46	0	0
T13	2138	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	226455	0	0
T1	54964	99	0	0
T2	9046	22	0	0
T3	261081	21	0	0
T7	250468	208	0	0
T8	487273	10	0	0
T9	289548	487	0	0
T10	678689	1252	0	0
T11	13566	22	0	0
T12	14282	46	0	0
T13	2138	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	3100090	0	0
T1	54964	735	0	0
T2	9046	154	0	0
T3	261081	79	0	0
T7	250468	874	0	0
T8	487273	4019	0	0
T9	289548	3909	0	0
T10	678689	6964	0	0
T11	13566	158	0	0
T12	14282	316	0	0
T13	2138	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	226455	0	0
T1	54964	99	0	0
T2	9046	22	0	0
T3	261081	21	0	0
T7	250468	208	0	0
T8	487273	10	0	0
T9	289548	487	0	0
T10	678689	1252	0	0
T11	13566	22	0	0
T12	14282	46	0	0
T13	2138	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	226455	0	0
T1	54964	99	0	0
T2	9046	22	0	0
T3	261081	21	0	0
T7	250468	208	0	0
T8	487273	10	0	0
T9	289548	487	0	0
T10	678689	1252	0	0
T11	13566	22	0	0
T12	14282	46	0	0
T13	2138	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	569391	0	0
T1	54964	110	0	0
T2	9046	27	0	0
T3	261081	38	0	0
T7	250468	222	0	0
T8	487273	204	0	0
T9	289548	544	0	0
T10	678689	2773	0	0
T11	13566	39	0	0
T12	14282	120	0	0
T13	2138	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	226455	0	0
T1	54964	99	0	0
T2	9046	22	0	0
T3	261081	21	0	0
T7	250468	208	0	0
T8	487273	10	0	0
T9	289548	487	0	0
T10	678689	1252	0	0
T11	13566	22	0	0
T12	14282	46	0	0
T13	2138	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	210982	0	0
GntImpliesValid_A	443037396	210982	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	210982	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	3020463	0	0
ReadyAndValidImplyGrant_A	443037396	210982	0	0
ReqAndReadyImplyGrant_A	443037396	210982	0	0
ReqImpliesValid_A	443037396	523116	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	210982	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	210982	0	0
T1	54964	101	0	0
T2	9046	6	0	0
T3	261081	12	0	0
T7	250468	220	0	0
T8	487273	18	0	0
T9	289548	539	0	0
T10	678689	1753	0	0
T11	13566	19	0	0
T12	14282	6	0	0
T13	2138	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	210982	0	0
T1	54964	101	0	0
T2	9046	6	0	0
T3	261081	12	0	0
T7	250468	220	0	0
T8	487273	18	0	0
T9	289548	539	0	0
T10	678689	1753	0	0
T11	13566	19	0	0
T12	14282	6	0	0
T13	2138	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	210982	0	0
T1	54964	101	0	0
T2	9046	6	0	0
T3	261081	12	0	0
T7	250468	220	0	0
T8	487273	18	0	0
T9	289548	539	0	0
T10	678689	1753	0	0
T11	13566	19	0	0
T12	14282	6	0	0
T13	2138	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	3020463	0	0
T1	54964	783	0	0
T2	9046	53	0	0
T3	261081	61	0	0
T7	250468	931	0	0
T8	487273	6787	0	0
T9	289548	4217	0	0
T10	678689	9479	0	0
T11	13566	110	0	0
T12	14282	50	0	0
T13	2138	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	210982	0	0
T1	54964	101	0	0
T2	9046	6	0	0
T3	261081	12	0	0
T7	250468	220	0	0
T8	487273	18	0	0
T9	289548	539	0	0
T10	678689	1753	0	0
T11	13566	19	0	0
T12	14282	6	0	0
T13	2138	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	210982	0	0
T1	54964	101	0	0
T2	9046	6	0	0
T3	261081	12	0	0
T7	250468	220	0	0
T8	487273	18	0	0
T9	289548	539	0	0
T10	678689	1753	0	0
T11	13566	19	0	0
T12	14282	6	0	0
T13	2138	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	523116	0	0
T1	54964	134	0	0
T2	9046	13	0	0
T3	261081	13	0	0
T7	250468	269	0	0
T8	487273	18	0	0
T9	289548	655	0	0
T10	678689	8119	0	0
T11	13566	50	0	0
T12	14282	6	0	0
T13	2138	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	210982	0	0
T1	54964	101	0	0
T2	9046	6	0	0
T3	261081	12	0	0
T7	250468	220	0	0
T8	487273	18	0	0
T9	289548	539	0	0
T10	678689	1753	0	0
T11	13566	19	0	0
T12	14282	6	0	0
T13	2138	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	227314	0	0
GntImpliesValid_A	443037396	227314	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	227314	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	3096644	0	0
ReadyAndValidImplyGrant_A	443037396	227314	0	0
ReqAndReadyImplyGrant_A	443037396	227314	0	0
ReqImpliesValid_A	443037396	620875	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	0	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	227314	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	227314	0	0
T1	54964	92	0	0
T2	9046	14	0	0
T3	261081	13	0	0
T7	250468	236	0	0
T8	487273	14	0	0
T9	289548	943	0	0
T10	678689	1277	0	0
T11	13566	12	0	0
T12	14282	6	0	0
T13	2138	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	227314	0	0
T1	54964	92	0	0
T2	9046	14	0	0
T3	261081	13	0	0
T7	250468	236	0	0
T8	487273	14	0	0
T9	289548	943	0	0
T10	678689	1277	0	0
T11	13566	12	0	0
T12	14282	6	0	0
T13	2138	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	227314	0	0
T1	54964	92	0	0
T2	9046	14	0	0
T3	261081	13	0	0
T7	250468	236	0	0
T8	487273	14	0	0
T9	289548	943	0	0
T10	678689	1277	0	0
T11	13566	12	0	0
T12	14282	6	0	0
T13	2138	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	3096644	0	0
T1	54964	683	0	0
T2	9046	92	0	0
T3	261081	61	0	0
T7	250468	972	0	0
T8	487273	3366	0	0
T9	289548	6350	0	0
T10	678689	8181	0	0
T11	13566	78	0	0
T12	14282	58	0	0
T13	2138	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	227314	0	0
T1	54964	92	0	0
T2	9046	14	0	0
T3	261081	13	0	0
T7	250468	236	0	0
T8	487273	14	0	0
T9	289548	943	0	0
T10	678689	1277	0	0
T11	13566	12	0	0
T12	14282	6	0	0
T13	2138	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	227314	0	0
T1	54964	92	0	0
T2	9046	14	0	0
T3	261081	13	0	0
T7	250468	236	0	0
T8	487273	14	0	0
T9	289548	943	0	0
T10	678689	1277	0	0
T11	13566	12	0	0
T12	14282	6	0	0
T13	2138	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	620875	0	0
T1	54964	118	0	0
T2	9046	16	0	0
T3	261081	13	0	0
T7	250468	288	0	0
T8	487273	14	0	0
T9	289548	2465	0	0
T10	678689	2259	0	0
T11	13566	14	0	0
T12	14282	10	0	0
T13	2138	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	227314	0	0
T1	54964	92	0	0
T2	9046	14	0	0
T3	261081	13	0	0
T7	250468	236	0	0
T8	487273	14	0	0
T9	289548	943	0	0
T10	678689	1277	0	0
T11	13566	12	0	0
T12	14282	6	0	0
T13	2138	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	920266	0	0
GntImpliesValid_A	443037396	920266	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	920266	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	11903038	0	0
ReadyAndValidImplyGrant_A	443037396	920266	0	0
ReqAndReadyImplyGrant_A	443037396	920266	0	0
ReqImpliesValid_A	443037396	2452467	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	20128	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	920266	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	920266	0	0
T1	54964	363	0	0
T2	9046	35	0	0
T3	261081	60	0	0
T7	250468	955	0	0
T8	487273	45	0	0
T9	289548	3313	0	0
T10	678689	6299	0	0
T11	13566	47	0	0
T12	14282	132	0	0
T13	2138	60	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	920266	0	0
T1	54964	363	0	0
T2	9046	35	0	0
T3	261081	60	0	0
T7	250468	955	0	0
T8	487273	45	0	0
T9	289548	3313	0	0
T10	678689	6299	0	0
T11	13566	47	0	0
T12	14282	132	0	0
T13	2138	60	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	920266	0	0
T1	54964	363	0	0
T2	9046	35	0	0
T3	261081	60	0	0
T7	250468	955	0	0
T8	487273	45	0	0
T9	289548	3313	0	0
T10	678689	6299	0	0
T11	13566	47	0	0
T12	14282	132	0	0
T13	2138	60	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	11903038	0	0
T1	54964	2443	0	0
T2	9046	307	0	0
T3	261081	191	0	0
T7	250468	3202	0	0
T8	487273	13612	0	0
T9	289548	21607	0	0
T10	678689	35735	0	0
T11	13566	308	0	0
T12	14282	808	0	0
T13	2138	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	920266	0	0
T1	54964	363	0	0
T2	9046	35	0	0
T3	261081	60	0	0
T7	250468	955	0	0
T8	487273	45	0	0
T9	289548	3313	0	0
T10	678689	6299	0	0
T11	13566	47	0	0
T12	14282	132	0	0
T13	2138	60	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	920266	0	0
T1	54964	363	0	0
T2	9046	35	0	0
T3	261081	60	0	0
T7	250468	955	0	0
T8	487273	45	0	0
T9	289548	3313	0	0
T10	678689	6299	0	0
T11	13566	47	0	0
T12	14282	132	0	0
T13	2138	60	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	2452467	0	0
T1	54964	431	0	0
T2	9046	59	0	0
T3	261081	74	0	0
T7	250468	1294	0	0
T8	487273	1300	0	0
T9	289548	6171	0	0
T10	678689	10492	0	0
T11	13566	53	0	0
T12	14282	199	0	0
T13	2138	60	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	20128	0	900
T9	289548	1	0	1
T10	678689	45	0	1
T11	13566	0	0	1
T12	14282	0	0	1
T13	2138	0	0	1
T14	478075	0	0	1
T15	453515	0	0	1
T16	20796	0	0	1
T17	0	13	0	0
T18	0	34	0	0
T19	0	13	0	0
T20	0	2	0	0
T22	0	4	0	0
T23	0	12	0	0
T24	0	175	0	0
T25	0	39	0	0
T26	147249	0	0	1
T27	215604	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	920266	0	0
T1	54964	363	0	0
T2	9046	35	0	0
T3	261081	60	0	0
T7	250468	955	0	0
T8	487273	45	0	0
T9	289548	3313	0	0
T10	678689	6299	0	0
T11	13566	47	0	0
T12	14282	132	0	0
T13	2138	60	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443037396	442912357	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	443037396	895014	0	0
GntImpliesValid_A	443037396	895014	0	0
GrantKnown_A	443037396	442912357	0	0
IdxKnown_A	443037396	442912357	0	0
IndexIsCorrect_A	443037396	895014	0	0
LockArbDecision_A	443037396	0	0	0
NoReadyValidNoGrant_A	443037396	372353343	0	0
ReadyAndValidImplyGrant_A	443037396	895014	0	0
ReqAndReadyImplyGrant_A	443037396	895014	0	0
ReqImpliesValid_A	443037396	13780054	0	0
ReqStaysHighUntilGranted0_M	443037396	0	0	0
RoundRobin_A	443037396	25586	0	900
ValidKnown_A	443037396	442912357	0	0
gen_data_port_assertion.DataFlow_A	443037396	895014	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	895014	0	0
T1	54964	387	0	0
T2	9046	33	0	0
T3	261081	77	0	0
T7	250468	947	0	0
T8	487273	52	0	0
T9	289548	3037	0	0
T10	678689	6948	0	0
T11	13566	58	0	0
T12	14282	128	0	0
T13	2138	51	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	895014	0	0
T1	54964	387	0	0
T2	9046	33	0	0
T3	261081	77	0	0
T7	250468	947	0	0
T8	487273	52	0	0
T9	289548	3037	0	0
T10	678689	6948	0	0
T11	13566	58	0	0
T12	14282	128	0	0
T13	2138	51	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	895014	0	0
T1	54964	387	0	0
T2	9046	33	0	0
T3	261081	77	0	0
T7	250468	947	0	0
T8	487273	52	0	0
T9	289548	3037	0	0
T10	678689	6948	0	0
T11	13566	58	0	0
T12	14282	128	0	0
T13	2138	51	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	372353343	0	0
T1	54964	46167	0	0
T2	9046	7991	0	0
T3	261081	217200	0	0
T7	250468	208389	0	0
T8	487273	462400	0	0
T9	289548	240896	0	0
T10	678689	564251	0	0
T11	13566	11708	0	0
T12	14282	10715	0	0
T13	2138	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	895014	0	0
T1	54964	387	0	0
T2	9046	33	0	0
T3	261081	77	0	0
T7	250468	947	0	0
T8	487273	52	0	0
T9	289548	3037	0	0
T10	678689	6948	0	0
T11	13566	58	0	0
T12	14282	128	0	0
T13	2138	51	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	895014	0	0
T1	54964	387	0	0
T2	9046	33	0	0
T3	261081	77	0	0
T7	250468	947	0	0
T8	487273	52	0	0
T9	289548	3037	0	0
T10	678689	6948	0	0
T11	13566	58	0	0
T12	14282	128	0	0
T13	2138	51	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	13780054	0	0
T1	54964	2897	0	0
T2	9046	225	0	0
T3	261081	333	0	0
T7	250468	4094	0	0
T8	487273	19113	0	0
T9	289548	23704	0	0
T10	678689	59702	0	0
T11	13566	417	0	0
T12	14282	914	0	0
T13	2138	51	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	25586	0	900
T9	289548	2	0	1
T10	678689	29	0	1
T11	13566	0	0	1
T12	14282	0	0	1
T13	2138	0	0	1
T14	478075	27	0	1
T15	453515	1	0	1
T16	20796	561	0	1
T18	0	177	0	0
T19	0	13	0	0
T20	0	5	0	0
T21	0	2	0	0
T22	0	8	0	0
T26	147249	0	0	1
T27	215604	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	442912357	0	0
T1	54964	54885	0	0
T2	9046	8988	0	0
T3	261081	261015	0	0
T7	250468	250462	0	0
T8	487273	487201	0	0
T9	289548	287792	0	0
T10	678689	678480	0	0
T11	13566	13497	0	0
T12	14282	13079	0	0
T13	2138	2088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443037396	895014	0	0
T1	54964	387	0	0
T2	9046	33	0	0
T3	261081	77	0	0
T7	250468	947	0	0
T8	487273	52	0	0
T9	289548	3037	0	0
T10	678689	6948	0	0
T11	13566	58	0	0
T12	14282	128	0	0
T13	2138	51	0	0