Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1597199	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

253893

1

T1

13

T2

7

T3

161

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	628438	1			T1	46		T2	18		T3	429
values[0x0]	594045	1			T1	7		T2	3		T3	375
values[0x1]	628609	1			T1	46		T2	18		T3	436

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1234928	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

616164

1

T1

39

T2

12

T3

385

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28567	1			T3	15		T7	100		T8	10
valid_sources[0x01]	29591	1			T1	1		T7	205		T8	2
valid_sources[0x02]	28912	1			T1	1		T3	27		T7	162
valid_sources[0x03]	28019	1			T1	2		T2	1		T3	12
valid_sources[0x04]	28281	1			T1	2		T2	1		T3	17
valid_sources[0x05]	29559	1			T1	1		T2	1		T3	5
valid_sources[0x06]	28459	1			T1	1		T3	41		T7	94
valid_sources[0x07]	28838	1			T2	1		T7	120		T8	11
valid_sources[0x08]	28853	1			T1	2		T3	18		T7	173
valid_sources[0x09]	29196	1			T2	2		T3	10		T7	129
valid_sources[0x0a]	28361	1			T1	1		T3	16		T7	150
valid_sources[0x0b]	29312	1			T3	33		T7	177		T8	6
valid_sources[0x0c]	29153	1			T3	32		T7	92		T8	5
valid_sources[0x0d]	29474	1			T1	4		T2	3		T7	203
valid_sources[0x0e]	29490	1			T1	1		T2	2		T7	167
valid_sources[0x0f]	28300	1			T1	2		T2	3		T3	14
valid_sources[0x10]	27735	1			T1	3		T7	92		T8	3
valid_sources[0x11]	29050	1			T1	3		T2	2		T3	15
valid_sources[0x12]	28669	1			T1	1		T2	1		T7	178
valid_sources[0x13]	28534	1			T1	3		T3	43		T7	117
valid_sources[0x14]	28821	1			T1	2		T3	14		T7	100
valid_sources[0x15]	29916	1			T1	2		T2	2		T3	26
valid_sources[0x16]	29138	1			T1	3		T3	43		T7	142
valid_sources[0x17]	28521	1			T1	2		T3	25		T7	148
valid_sources[0x18]	29122	1			T1	3		T2	1		T3	44
valid_sources[0x19]	29364	1			T1	3		T2	2		T3	35
valid_sources[0x1a]	29039	1			T7	142		T8	6		T9	10
valid_sources[0x1b]	28896	1			T1	1		T7	98		T8	3
valid_sources[0x1c]	29516	1			T1	6		T7	150		T8	3
valid_sources[0x1d]	28618	1			T3	40		T7	152		T8	4
valid_sources[0x1e]	28629	1			T1	1		T3	27		T7	216
valid_sources[0x1f]	28996	1			T1	2		T3	35		T7	158
valid_sources[0x20]	28777	1			T1	1		T3	12		T7	184

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27030

1

T1

4

T2

2

T3

24

values[0x0]

all_enables

biggest_size

200030

1

T1

4

T2

2

T3

120

values[0x1]

all_enables

biggest_size

26833

1

T1

5

T2

3

T3

17

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1610685	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

262801

1

T1

9

T2

7

T3

175

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	641326	1			T1	36		T2	27		T3	414
values[0x0]	591465	1			T1	7		T2	4		T3	410
values[0x1]	640695	1			T1	48		T2	26		T3	410

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1236661	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

636825

1

T1

40

T2

18

T3

401

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28987	1			T1	2		T3	12		T7	96
valid_sources[0x01]	29218	1			T1	2		T7	132		T9	17
valid_sources[0x02]	29233	1			T1	2		T3	22		T7	213
valid_sources[0x03]	29657	1			T3	9		T7	78		T8	4
valid_sources[0x04]	29358	1			T2	2		T3	28		T7	255
valid_sources[0x05]	29695	1			T2	1		T3	11		T7	228
valid_sources[0x06]	29596	1			T1	2		T2	3		T3	48
valid_sources[0x07]	29179	1			T1	1		T7	110		T8	9
valid_sources[0x08]	29755	1			T1	2		T2	1		T3	7
valid_sources[0x09]	29119	1			T2	1		T3	16		T7	84
valid_sources[0x0a]	29122	1			T1	1		T2	2		T3	19
valid_sources[0x0b]	30328	1			T1	3		T3	25		T7	283
valid_sources[0x0c]	28865	1			T1	1		T2	2		T3	34
valid_sources[0x0d]	28769	1			T1	2		T2	1		T7	275
valid_sources[0x0e]	29456	1			T1	2		T7	186		T8	4
valid_sources[0x0f]	29195	1			T1	3		T2	1		T3	17
valid_sources[0x10]	28801	1			T1	2		T2	2		T7	113
valid_sources[0x11]	29329	1			T1	4		T3	22		T7	194
valid_sources[0x12]	29040	1			T1	2		T2	1		T7	125
valid_sources[0x13]	28733	1			T1	3		T3	32		T7	115
valid_sources[0x14]	29616	1			T1	4		T3	19		T7	147
valid_sources[0x15]	29244	1			T1	2		T3	23		T7	283
valid_sources[0x16]	29487	1			T1	1		T3	18		T7	92
valid_sources[0x17]	28962	1			T2	1		T3	18		T7	116
valid_sources[0x18]	29233	1			T1	2		T3	69		T7	49
valid_sources[0x19]	29161	1			T3	15		T7	182		T8	9
valid_sources[0x1a]	29643	1			T1	1		T2	1		T7	101
valid_sources[0x1b]	29446	1			T1	1		T2	1		T7	134
valid_sources[0x1c]	28702	1			T1	2		T2	1		T7	163
valid_sources[0x1d]	29538	1			T1	3		T2	1		T3	46
valid_sources[0x1e]	28982	1			T1	1		T2	1		T3	23
valid_sources[0x1f]	29789	1			T1	1		T2	1		T3	21
valid_sources[0x20]	29263	1			T1	1		T2	3		T3	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27850

1

T1

3

T2

4

T3

23

values[0x0]

all_enables

biggest_size

207490

1

T1

3

T3

136

T7

1125

values[0x1]

all_enables

biggest_size

27461

1

T1

3

T2

3

T3

16

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1602782	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

255560

1

T1

11

T2

3

T3

151

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	630779	1			T1	60		T2	17		T3	465
values[0x0]	597493	1			T1	11		T2	1		T3	392
values[0x1]	630070	1			T1	43		T2	17		T3	382

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1237892	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

620450

1

T1

45

T2

17

T3

374

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28537	1			T3	15		T7	129		T8	3
valid_sources[0x01]	29292	1			T1	4		T2	1		T7	194
valid_sources[0x02]	29678	1			T1	3		T3	40		T7	132
valid_sources[0x03]	29110	1			T2	1		T3	12		T7	121
valid_sources[0x04]	29725	1			T1	3		T2	1		T3	35
valid_sources[0x05]	29341	1			T1	7		T3	6		T7	175
valid_sources[0x06]	28810	1			T3	33		T7	121		T8	10
valid_sources[0x07]	28588	1			T7	126		T8	6		T9	7
valid_sources[0x08]	29443	1			T2	2		T3	9		T7	148
valid_sources[0x09]	28622	1			T2	1		T3	20		T7	115
valid_sources[0x0a]	29197	1			T1	5		T2	1		T3	17
valid_sources[0x0b]	29566	1			T1	1		T3	25		T7	202
valid_sources[0x0c]	28473	1			T1	1		T3	22		T7	133
valid_sources[0x0d]	28608	1			T1	4		T2	2		T7	170
valid_sources[0x0e]	28899	1			T2	3		T7	172		T8	2
valid_sources[0x0f]	29937	1			T3	16		T7	153		T8	7
valid_sources[0x10]	28127	1			T1	1		T7	120		T8	9
valid_sources[0x11]	28388	1			T1	1		T3	28		T7	168
valid_sources[0x12]	28154	1			T1	7		T2	2		T7	152
valid_sources[0x13]	28894	1			T1	6		T2	1		T3	41
valid_sources[0x14]	29445	1			T1	4		T3	8		T7	91
valid_sources[0x15]	28387	1			T2	1		T3	36		T7	214
valid_sources[0x16]	29417	1			T3	25		T7	186		T8	5
valid_sources[0x17]	28533	1			T1	2		T2	2		T3	18
valid_sources[0x18]	29579	1			T1	2		T3	41		T7	132
valid_sources[0x19]	29317	1			T1	2		T3	13		T7	192
valid_sources[0x1a]	29699	1			T1	4		T7	138		T8	10
valid_sources[0x1b]	28971	1			T7	149		T8	10		T9	9
valid_sources[0x1c]	29182	1			T7	153		T8	5		T9	21
valid_sources[0x1d]	29525	1			T1	4		T3	48		T7	177
valid_sources[0x1e]	29398	1			T1	3		T3	16		T7	146
valid_sources[0x1f]	30032	1			T1	4		T3	41		T7	163
valid_sources[0x20]	28453	1			T3	19		T7	179		T8	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26760

1

T1

5

T2

1

T3

19

values[0x0]

all_enables

biggest_size

201928

1

T1

4

T3

115

T7

1072

values[0x1]

all_enables

biggest_size

26872

1

T1

2

T2

2

T3

17