Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8170001	0	0
GntImpliesValid_A	2147483647	8170001	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8170001	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	456112856	0	0
ReadyAndValidImplyGrant_A	2147483647	8170001	0	0
ReqAndReadyImplyGrant_A	2147483647	8170001	0	0
ReqImpliesValid_A	2147483647	35385447	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	52947	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8170001	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	211272	210216	0	0
T2	161040	159240	0	0
T3	324672	322584	0	0
T7	5682936	5661552	0	0
T8	5545104	5544480	0	0
T9	14317536	14316648	0	0
T10	23016	22632	0	0
T11	12633576	12628896	0	0
T12	11543736	11543208	0	0
T13	1610280	1606848	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8170001	0	0
T1	211272	3431	0	0
T2	161040	2690	0	0
T3	324672	3690	0	0
T7	5682936	23425	0	0
T8	5545104	23012	0	0
T9	14317536	48556	0	0
T10	23016	533	0	0
T11	12633576	40477	0	0
T12	11543736	423	0	0
T13	1610280	31090	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8170001	0	0
T1	211272	3431	0	0
T2	161040	2690	0	0
T3	324672	3690	0	0
T7	5682936	23425	0	0
T8	5545104	23012	0	0
T9	14317536	48556	0	0
T10	23016	533	0	0
T11	12633576	40477	0	0
T12	11543736	423	0	0
T13	1610280	31090	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	211272	210216	0	0
T2	161040	159240	0	0
T3	324672	322584	0	0
T7	5682936	5661552	0	0
T8	5545104	5544480	0	0
T9	14317536	14316648	0	0
T10	23016	22632	0	0
T11	12633576	12628896	0	0
T12	11543736	11543208	0	0
T13	1610280	1606848	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	211272	210216	0	0
T2	161040	159240	0	0
T3	324672	322584	0	0
T7	5682936	5661552	0	0
T8	5545104	5544480	0	0
T9	14317536	14316648	0	0
T10	23016	22632	0	0
T11	12633576	12628896	0	0
T12	11543736	11543208	0	0
T13	1610280	1606848	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8170001	0	0
T1	211272	3431	0	0
T2	161040	2690	0	0
T3	324672	3690	0	0
T7	5682936	23425	0	0
T8	5545104	23012	0	0
T9	14317536	48556	0	0
T10	23016	533	0	0
T11	12633576	40477	0	0
T12	11543736	423	0	0
T13	1610280	31090	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	456112856	0	0
T1	211272	4615	0	0
T2	161040	4693	0	0
T3	324672	7777	0	0
T7	5682936	349712	0	0
T8	5545104	319269	0	0
T9	14317536	845486	0	0
T10	23016	608	0	0
T11	12633576	798466	0	0
T12	11543736	596721	0	0
T13	1610280	30476	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8170001	0	0
T1	211272	3431	0	0
T2	161040	2690	0	0
T3	324672	3690	0	0
T7	5682936	23425	0	0
T8	5545104	23012	0	0
T9	14317536	48556	0	0
T10	23016	533	0	0
T11	12633576	40477	0	0
T12	11543736	423	0	0
T13	1610280	31090	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8170001	0	0
T1	211272	3431	0	0
T2	161040	2690	0	0
T3	324672	3690	0	0
T7	5682936	23425	0	0
T8	5545104	23012	0	0
T9	14317536	48556	0	0
T10	23016	533	0	0
T11	12633576	40477	0	0
T12	11543736	423	0	0
T13	1610280	31090	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35385447	0	0
T1	211272	3922	0	0
T2	161040	3590	0	0
T3	324672	4015	0	0
T7	5682936	64384	0	0
T8	5545104	65478	0	0
T9	14317536	230602	0	0
T10	23016	628	0	0
T11	12633576	104768	0	0
T12	11543736	21239	0	0
T13	1610280	47844	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	52947	0	21600
T1	17606	8	0	2
T2	13420	6	0	2
T3	27056	15	0	2
T7	473578	3	0	2
T8	462092	4	0	2
T9	1193128	20	0	2
T10	1918	0	0	2
T11	1052798	6	0	2
T12	961978	0	0	2
T13	134190	50	0	2
T14	0	27	0	0
T15	0	1	0	0
T16	0	8	0	0
T17	0	12	0	0
T18	0	20	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	211272	210216	0	0
T2	161040	159240	0	0
T3	324672	322584	0	0
T7	5682936	5661552	0	0
T8	5545104	5544480	0	0
T9	14317536	14316648	0	0
T10	23016	22632	0	0
T11	12633576	12628896	0	0
T12	11543736	11543208	0	0
T13	1610280	1606848	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8170001	0	0
T1	211272	3431	0	0
T2	161040	2690	0	0
T3	324672	3690	0	0
T7	5682936	23425	0	0
T8	5545104	23012	0	0
T9	14317536	48556	0	0
T10	23016	533	0	0
T11	12633576	40477	0	0
T12	11543736	423	0	0
T13	1610280	31090	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	921689	0	0
GntImpliesValid_A	420655702	921689	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	921689	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	11924930	0	0
ReadyAndValidImplyGrant_A	420655702	921689	0	0
ReqAndReadyImplyGrant_A	420655702	921689	0	0
ReqImpliesValid_A	420655702	2590717	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	921689	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	921689	0	0
T1	8803	352	0	0
T2	6710	315	0	0
T3	13528	430	0	0
T7	236789	2825	0	0
T8	231046	2809	0	0
T9	596564	5101	0	0
T10	959	61	0	0
T11	526399	4230	0	0
T12	480989	49	0	0
T13	67095	3795	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	921689	0	0
T1	8803	352	0	0
T2	6710	315	0	0
T3	13528	430	0	0
T7	236789	2825	0	0
T8	231046	2809	0	0
T9	596564	5101	0	0
T10	959	61	0	0
T11	526399	4230	0	0
T12	480989	49	0	0
T13	67095	3795	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	921689	0	0
T1	8803	352	0	0
T2	6710	315	0	0
T3	13528	430	0	0
T7	236789	2825	0	0
T8	231046	2809	0	0
T9	596564	5101	0	0
T10	959	61	0	0
T11	526399	4230	0	0
T12	480989	49	0	0
T13	67095	3795	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	11924930	0	0
T1	8803	303	0	0
T2	6710	231	0	0
T3	13528	424	0	0
T7	236789	18141	0	0
T8	231046	18884	0	0
T9	596564	35275	0	0
T10	959	45	0	0
T11	526399	29693	0	0
T12	480989	14459	0	0
T13	67095	2583	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	921689	0	0
T1	8803	352	0	0
T2	6710	315	0	0
T3	13528	430	0	0
T7	236789	2825	0	0
T8	231046	2809	0	0
T9	596564	5101	0	0
T10	959	61	0	0
T11	526399	4230	0	0
T12	480989	49	0	0
T13	67095	3795	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	921689	0	0
T1	8803	352	0	0
T2	6710	315	0	0
T3	13528	430	0	0
T7	236789	2825	0	0
T8	231046	2809	0	0
T9	596564	5101	0	0
T10	959	61	0	0
T11	526399	4230	0	0
T12	480989	49	0	0
T13	67095	3795	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	2590717	0	0
T1	8803	402	0	0
T2	6710	400	0	0
T3	13528	437	0	0
T7	236789	5109	0	0
T8	231046	7550	0	0
T9	596564	11548	0	0
T10	959	78	0	0
T11	526399	6225	0	0
T12	480989	2674	0	0
T13	67095	5010	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	921689	0	0
T1	8803	352	0	0
T2	6710	315	0	0
T3	13528	430	0	0
T7	236789	2825	0	0
T8	231046	2809	0	0
T9	596564	5101	0	0
T10	959	61	0	0
T11	526399	4230	0	0
T12	480989	49	0	0
T13	67095	3795	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	898348	0	0
GntImpliesValid_A	420655702	898348	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	898348	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	12074059	0	0
ReadyAndValidImplyGrant_A	420655702	898348	0	0
ReqAndReadyImplyGrant_A	420655702	898348	0	0
ReqImpliesValid_A	420655702	2438616	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	898348	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	898348	0	0
T1	8803	351	0	0
T2	6710	304	0	0
T3	13528	402	0	0
T7	236789	2123	0	0
T8	231046	2150	0	0
T9	596564	6577	0	0
T10	959	53	0	0
T11	526399	4915	0	0
T12	480989	47	0	0
T13	67095	3514	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	898348	0	0
T1	8803	351	0	0
T2	6710	304	0	0
T3	13528	402	0	0
T7	236789	2123	0	0
T8	231046	2150	0	0
T9	596564	6577	0	0
T10	959	53	0	0
T11	526399	4915	0	0
T12	480989	47	0	0
T13	67095	3514	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	898348	0	0
T1	8803	351	0	0
T2	6710	304	0	0
T3	13528	402	0	0
T7	236789	2123	0	0
T8	231046	2150	0	0
T9	596564	6577	0	0
T10	959	53	0	0
T11	526399	4915	0	0
T12	480989	47	0	0
T13	67095	3514	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	12074059	0	0
T1	8803	292	0	0
T2	6710	212	0	0
T3	13528	395	0	0
T7	236789	16172	0	0
T8	231046	15658	0	0
T9	596564	40800	0	0
T10	959	41	0	0
T11	526399	34947	0	0
T12	480989	13888	0	0
T13	67095	2379	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	898348	0	0
T1	8803	351	0	0
T2	6710	304	0	0
T3	13528	402	0	0
T7	236789	2123	0	0
T8	231046	2150	0	0
T9	596564	6577	0	0
T10	959	53	0	0
T11	526399	4915	0	0
T12	480989	47	0	0
T13	67095	3514	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	898348	0	0
T1	8803	351	0	0
T2	6710	304	0	0
T3	13528	402	0	0
T7	236789	2123	0	0
T8	231046	2150	0	0
T9	596564	6577	0	0
T10	959	53	0	0
T11	526399	4915	0	0
T12	480989	47	0	0
T13	67095	3514	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	2438616	0	0
T1	8803	411	0	0
T2	6710	397	0	0
T3	13528	410	0	0
T7	236789	3179	0	0
T8	231046	3283	0	0
T9	596564	22837	0	0
T10	959	66	0	0
T11	526399	9102	0	0
T12	480989	2808	0	0
T13	67095	4652	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	898348	0	0
T1	8803	351	0	0
T2	6710	304	0	0
T3	13528	402	0	0
T7	236789	2123	0	0
T8	231046	2150	0	0
T9	596564	6577	0	0
T10	959	53	0	0
T11	526399	4915	0	0
T12	480989	47	0	0
T13	67095	3514	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	228209	0	0
GntImpliesValid_A	420655702	228209	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	228209	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	2978588	0	0
ReadyAndValidImplyGrant_A	420655702	228209	0	0
ReqAndReadyImplyGrant_A	420655702	228209	0	0
ReqImpliesValid_A	420655702	595087	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	228209	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	228209	0	0
T1	8803	96	0	0
T2	6710	87	0	0
T3	13528	102	0	0
T7	236789	717	0	0
T8	231046	331	0	0
T9	596564	1208	0	0
T10	959	13	0	0
T11	526399	911	0	0
T12	480989	13	0	0
T13	67095	448	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	228209	0	0
T1	8803	96	0	0
T2	6710	87	0	0
T3	13528	102	0	0
T7	236789	717	0	0
T8	231046	331	0	0
T9	596564	1208	0	0
T10	959	13	0	0
T11	526399	911	0	0
T12	480989	13	0	0
T13	67095	448	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	228209	0	0
T1	8803	96	0	0
T2	6710	87	0	0
T3	13528	102	0	0
T7	236789	717	0	0
T8	231046	331	0	0
T9	596564	1208	0	0
T10	959	13	0	0
T11	526399	911	0	0
T12	480989	13	0	0
T13	67095	448	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	2978588	0	0
T1	8803	91	0	0
T2	6710	83	0	0
T3	13528	103	0	0
T7	236789	4899	0	0
T8	231046	2443	0	0
T9	596564	7934	0	0
T10	959	13	0	0
T11	526399	6894	0	0
T12	480989	4193	0	0
T13	67095	442	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	228209	0	0
T1	8803	96	0	0
T2	6710	87	0	0
T3	13528	102	0	0
T7	236789	717	0	0
T8	231046	331	0	0
T9	596564	1208	0	0
T10	959	13	0	0
T11	526399	911	0	0
T12	480989	13	0	0
T13	67095	448	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	228209	0	0
T1	8803	96	0	0
T2	6710	87	0	0
T3	13528	102	0	0
T7	236789	717	0	0
T8	231046	331	0	0
T9	596564	1208	0	0
T10	959	13	0	0
T11	526399	911	0	0
T12	480989	13	0	0
T13	67095	448	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	595087	0	0
T1	8803	102	0	0
T2	6710	92	0	0
T3	13528	102	0	0
T7	236789	1215	0	0
T8	231046	399	0	0
T9	596564	3613	0	0
T10	959	14	0	0
T11	526399	1051	0	0
T12	480989	1019	0	0
T13	67095	457	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	228209	0	0
T1	8803	96	0	0
T2	6710	87	0	0
T3	13528	102	0	0
T7	236789	717	0	0
T8	231046	331	0	0
T9	596564	1208	0	0
T10	959	13	0	0
T11	526399	911	0	0
T12	480989	13	0	0
T13	67095	448	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	230124	0	0
GntImpliesValid_A	420655702	230124	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	230124	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	2979837	0	0
ReadyAndValidImplyGrant_A	420655702	230124	0	0
ReqAndReadyImplyGrant_A	420655702	230124	0	0
ReqImpliesValid_A	420655702	639204	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	230124	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230124	0	0
T1	8803	102	0	0
T2	6710	79	0	0
T3	13528	97	0	0
T7	236789	466	0	0
T8	231046	1388	0	0
T9	596564	1216	0	0
T10	959	15	0	0
T11	526399	848	0	0
T12	480989	12	0	0
T13	67095	447	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230124	0	0
T1	8803	102	0	0
T2	6710	79	0	0
T3	13528	97	0	0
T7	236789	466	0	0
T8	231046	1388	0	0
T9	596564	1216	0	0
T10	959	15	0	0
T11	526399	848	0	0
T12	480989	12	0	0
T13	67095	447	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230124	0	0
T1	8803	102	0	0
T2	6710	79	0	0
T3	13528	97	0	0
T7	236789	466	0	0
T8	231046	1388	0	0
T9	596564	1216	0	0
T10	959	15	0	0
T11	526399	848	0	0
T12	480989	12	0	0
T13	67095	447	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	2979837	0	0
T1	8803	98	0	0
T2	6710	72	0	0
T3	13528	97	0	0
T7	236789	3009	0	0
T8	231046	8473	0	0
T9	596564	6041	0	0
T10	959	15	0	0
T11	526399	6434	0	0
T12	480989	2629	0	0
T13	67095	445	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230124	0	0
T1	8803	102	0	0
T2	6710	79	0	0
T3	13528	97	0	0
T7	236789	466	0	0
T8	231046	1388	0	0
T9	596564	1216	0	0
T10	959	15	0	0
T11	526399	848	0	0
T12	480989	12	0	0
T13	67095	447	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230124	0	0
T1	8803	102	0	0
T2	6710	79	0	0
T3	13528	97	0	0
T7	236789	466	0	0
T8	231046	1388	0	0
T9	596564	1216	0	0
T10	959	15	0	0
T11	526399	848	0	0
T12	480989	12	0	0
T13	67095	447	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	639204	0	0
T1	8803	107	0	0
T2	6710	87	0	0
T3	13528	98	0	0
T7	236789	1319	0	0
T8	231046	2915	0	0
T9	596564	5684	0	0
T10	959	16	0	0
T11	526399	924	0	0
T12	480989	12	0	0
T13	67095	452	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230124	0	0
T1	8803	102	0	0
T2	6710	79	0	0
T3	13528	97	0	0
T7	236789	466	0	0
T8	231046	1388	0	0
T9	596564	1216	0	0
T10	959	15	0	0
T11	526399	848	0	0
T12	480989	12	0	0
T13	67095	447	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	217403	0	0
GntImpliesValid_A	420655702	217403	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	217403	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	4381172	0	0
ReadyAndValidImplyGrant_A	420655702	217403	0	0
ReqAndReadyImplyGrant_A	420655702	217403	0	0
ReqImpliesValid_A	420655702	1051376	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	217403	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	217403	0	0
T1	8803	103	0	0
T2	6710	80	0	0
T3	13528	104	0	0
T7	236789	789	0	0
T8	231046	835	0	0
T9	596564	1619	0	0
T10	959	15	0	0
T11	526399	888	0	0
T12	480989	19	0	0
T13	67095	467	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	217403	0	0
T1	8803	103	0	0
T2	6710	80	0	0
T3	13528	104	0	0
T7	236789	789	0	0
T8	231046	835	0	0
T9	596564	1619	0	0
T10	959	15	0	0
T11	526399	888	0	0
T12	480989	19	0	0
T13	67095	467	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	217403	0	0
T1	8803	103	0	0
T2	6710	80	0	0
T3	13528	104	0	0
T7	236789	789	0	0
T8	231046	835	0	0
T9	596564	1619	0	0
T10	959	15	0	0
T11	526399	888	0	0
T12	480989	19	0	0
T13	67095	467	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	4381172	0	0
T1	8803	641	0	0
T2	6710	1705	0	0
T3	13528	853	0	0
T7	236789	4705	0	0
T8	231046	3363	0	0
T9	596564	19275	0	0
T10	959	62	0	0
T11	526399	67942	0	0
T12	480989	18595	0	0
T13	67095	2172	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	217403	0	0
T1	8803	103	0	0
T2	6710	80	0	0
T3	13528	104	0	0
T7	236789	789	0	0
T8	231046	835	0	0
T9	596564	1619	0	0
T10	959	15	0	0
T11	526399	888	0	0
T12	480989	19	0	0
T13	67095	467	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	217403	0	0
T1	8803	103	0	0
T2	6710	80	0	0
T3	13528	104	0	0
T7	236789	789	0	0
T8	231046	835	0	0
T9	596564	1619	0	0
T10	959	15	0	0
T11	526399	888	0	0
T12	480989	19	0	0
T13	67095	467	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	1051376	0	0
T1	8803	171	0	0
T2	6710	552	0	0
T3	13528	110	0	0
T7	236789	1781	0	0
T8	231046	1784	0	0
T9	596564	16531	0	0
T10	959	17	0	0
T11	526399	5410	0	0
T12	480989	19	0	0
T13	67095	580	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	217403	0	0
T1	8803	103	0	0
T2	6710	80	0	0
T3	13528	104	0	0
T7	236789	789	0	0
T8	231046	835	0	0
T9	596564	1619	0	0
T10	959	15	0	0
T11	526399	888	0	0
T12	480989	19	0	0
T13	67095	467	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	224214	0	0
GntImpliesValid_A	420655702	224214	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	224214	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	5230844	0	0
ReadyAndValidImplyGrant_A	420655702	224214	0	0
ReqAndReadyImplyGrant_A	420655702	224214	0	0
ReqImpliesValid_A	420655702	1290519	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	224214	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	224214	0	0
T1	8803	97	0	0
T2	6710	70	0	0
T3	13528	108	0	0
T7	236789	1234	0	0
T8	231046	920	0	0
T9	596564	705	0	0
T10	959	18	0	0
T11	526399	1376	0	0
T12	480989	14	0	0
T13	67095	908	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	224214	0	0
T1	8803	97	0	0
T2	6710	70	0	0
T3	13528	108	0	0
T7	236789	1234	0	0
T8	231046	920	0	0
T9	596564	705	0	0
T10	959	18	0	0
T11	526399	1376	0	0
T12	480989	14	0	0
T13	67095	908	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	224214	0	0
T1	8803	97	0	0
T2	6710	70	0	0
T3	13528	108	0	0
T7	236789	1234	0	0
T8	231046	920	0	0
T9	596564	705	0	0
T10	959	18	0	0
T11	526399	1376	0	0
T12	480989	14	0	0
T13	67095	908	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	5230844	0	0
T1	8803	496	0	0
T2	6710	365	0	0
T3	13528	1471	0	0
T7	236789	14429	0	0
T8	231046	3273	0	0
T9	596564	4805	0	0
T10	959	55	0	0
T11	526399	30063	0	0
T12	480989	2460	0	0
T13	67095	4859	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	224214	0	0
T1	8803	97	0	0
T2	6710	70	0	0
T3	13528	108	0	0
T7	236789	1234	0	0
T8	231046	920	0	0
T9	596564	705	0	0
T10	959	18	0	0
T11	526399	1376	0	0
T12	480989	14	0	0
T13	67095	908	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	224214	0	0
T1	8803	97	0	0
T2	6710	70	0	0
T3	13528	108	0	0
T7	236789	1234	0	0
T8	231046	920	0	0
T9	596564	705	0	0
T10	959	18	0	0
T11	526399	1376	0	0
T12	480989	14	0	0
T13	67095	908	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	1290519	0	0
T1	8803	172	0	0
T2	6710	157	0	0
T3	13528	205	0	0
T7	236789	4578	0	0
T8	231046	1693	0	0
T9	596564	804	0	0
T10	959	27	0	0
T11	526399	7381	0	0
T12	480989	14	0	0
T13	67095	2405	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	224214	0	0
T1	8803	97	0	0
T2	6710	70	0	0
T3	13528	108	0	0
T7	236789	1234	0	0
T8	231046	920	0	0
T9	596564	705	0	0
T10	959	18	0	0
T11	526399	1376	0	0
T12	480989	14	0	0
T13	67095	908	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	224174	0	0
GntImpliesValid_A	420655702	224174	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	224174	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	5169037	0	0
ReadyAndValidImplyGrant_A	420655702	224174	0	0
ReqAndReadyImplyGrant_A	420655702	224174	0	0
ReqImpliesValid_A	420655702	1263285	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	224174	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	224174	0	0
T1	8803	96	0	0
T2	6710	81	0	0
T3	13528	105	0	0
T7	236789	269	0	0
T8	231046	376	0	0
T9	596564	2733	0	0
T10	959	20	0	0
T11	526399	838	0	0
T12	480989	13	0	0
T13	67095	1954	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	224174	0	0
T1	8803	96	0	0
T2	6710	81	0	0
T3	13528	105	0	0
T7	236789	269	0	0
T8	231046	376	0	0
T9	596564	2733	0	0
T10	959	20	0	0
T11	526399	838	0	0
T12	480989	13	0	0
T13	67095	1954	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	224174	0	0
T1	8803	96	0	0
T2	6710	81	0	0
T3	13528	105	0	0
T7	236789	269	0	0
T8	231046	376	0	0
T9	596564	2733	0	0
T10	959	20	0	0
T11	526399	838	0	0
T12	480989	13	0	0
T13	67095	1954	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	5169037	0	0
T1	8803	621	0	0
T2	6710	597	0	0
T3	13528	620	0	0
T7	236789	2414	0	0
T8	231046	2231	0	0
T9	596564	44835	0	0
T10	959	83	0	0
T11	526399	10182	0	0
T12	480989	3142	0	0
T13	67095	6062	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	224174	0	0
T1	8803	96	0	0
T2	6710	81	0	0
T3	13528	105	0	0
T7	236789	269	0	0
T8	231046	376	0	0
T9	596564	2733	0	0
T10	959	20	0	0
T11	526399	838	0	0
T12	480989	13	0	0
T13	67095	1954	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	224174	0	0
T1	8803	96	0	0
T2	6710	81	0	0
T3	13528	105	0	0
T7	236789	269	0	0
T8	231046	376	0	0
T9	596564	2733	0	0
T10	959	20	0	0
T11	526399	838	0	0
T12	480989	13	0	0
T13	67095	1954	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	1263285	0	0
T1	8803	180	0	0
T2	6710	120	0	0
T3	13528	124	0	0
T7	236789	281	0	0
T8	231046	408	0	0
T9	596564	48093	0	0
T10	959	39	0	0
T11	526399	1105	0	0
T12	480989	13	0	0
T13	67095	10605	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	224174	0	0
T1	8803	96	0	0
T2	6710	81	0	0
T3	13528	105	0	0
T7	236789	269	0	0
T8	231046	376	0	0
T9	596564	2733	0	0
T10	959	20	0	0
T11	526399	838	0	0
T12	480989	13	0	0
T13	67095	1954	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	222748	0	0
GntImpliesValid_A	420655702	222748	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	222748	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	5160031	0	0
ReadyAndValidImplyGrant_A	420655702	222748	0	0
ReqAndReadyImplyGrant_A	420655702	222748	0	0
ReqImpliesValid_A	420655702	1268751	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	222748	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	222748	0	0
T1	8803	89	0	0
T2	6710	84	0	0
T3	13528	111	0	0
T7	236789	844	0	0
T8	231046	388	0	0
T9	596564	1222	0	0
T10	959	18	0	0
T11	526399	1345	0	0
T12	480989	10	0	0
T13	67095	440	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	222748	0	0
T1	8803	89	0	0
T2	6710	84	0	0
T3	13528	111	0	0
T7	236789	844	0	0
T8	231046	388	0	0
T9	596564	1222	0	0
T10	959	18	0	0
T11	526399	1345	0	0
T12	480989	10	0	0
T13	67095	440	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	222748	0	0
T1	8803	89	0	0
T2	6710	84	0	0
T3	13528	111	0	0
T7	236789	844	0	0
T8	231046	388	0	0
T9	596564	1222	0	0
T10	959	18	0	0
T11	526399	1345	0	0
T12	480989	10	0	0
T13	67095	440	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	5160031	0	0
T1	8803	725	0	0
T2	6710	474	0	0
T3	13528	2383	0	0
T7	236789	6812	0	0
T8	231046	1795	0	0
T9	596564	32830	0	0
T10	959	62	0	0
T11	526399	23229	0	0
T12	480989	5872	0	0
T13	67095	2192	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	222748	0	0
T1	8803	89	0	0
T2	6710	84	0	0
T3	13528	111	0	0
T7	236789	844	0	0
T8	231046	388	0	0
T9	596564	1222	0	0
T10	959	18	0	0
T11	526399	1345	0	0
T12	480989	10	0	0
T13	67095	440	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	222748	0	0
T1	8803	89	0	0
T2	6710	84	0	0
T3	13528	111	0	0
T7	236789	844	0	0
T8	231046	388	0	0
T9	596564	1222	0	0
T10	959	18	0	0
T11	526399	1345	0	0
T12	480989	10	0	0
T13	67095	440	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	1268751	0	0
T1	8803	159	0	0
T2	6710	140	0	0
T3	13528	293	0	0
T7	236789	2299	0	0
T8	231046	400	0	0
T9	596564	20444	0	0
T10	959	28	0	0
T11	526399	4696	0	0
T12	480989	10	0	0
T13	67095	537	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	222748	0	0
T1	8803	89	0	0
T2	6710	84	0	0
T3	13528	111	0	0
T7	236789	844	0	0
T8	231046	388	0	0
T9	596564	1222	0	0
T10	959	18	0	0
T11	526399	1345	0	0
T12	480989	10	0	0
T13	67095	440	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	230622	0	0
GntImpliesValid_A	420655702	230622	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	230622	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	2980012	0	0
ReadyAndValidImplyGrant_A	420655702	230622	0	0
ReqAndReadyImplyGrant_A	420655702	230622	0	0
ReqImpliesValid_A	420655702	631840	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	230622	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230622	0	0
T1	8803	98	0	0
T2	6710	80	0	0
T3	13528	98	0	0
T7	236789	338	0	0
T8	231046	353	0	0
T9	596564	1063	0	0
T10	959	17	0	0
T11	526399	1342	0	0
T12	480989	14	0	0
T13	67095	1886	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230622	0	0
T1	8803	98	0	0
T2	6710	80	0	0
T3	13528	98	0	0
T7	236789	338	0	0
T8	231046	353	0	0
T9	596564	1063	0	0
T10	959	17	0	0
T11	526399	1342	0	0
T12	480989	14	0	0
T13	67095	1886	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230622	0	0
T1	8803	98	0	0
T2	6710	80	0	0
T3	13528	98	0	0
T7	236789	338	0	0
T8	231046	353	0	0
T9	596564	1063	0	0
T10	959	17	0	0
T11	526399	1342	0	0
T12	480989	14	0	0
T13	67095	1886	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	2980012	0	0
T1	8803	93	0	0
T2	6710	78	0	0
T3	13528	99	0	0
T7	236789	2643	0	0
T8	231046	2700	0	0
T9	596564	8027	0	0
T10	959	17	0	0
T11	526399	9389	0	0
T12	480989	3409	0	0
T13	67095	1066	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230622	0	0
T1	8803	98	0	0
T2	6710	80	0	0
T3	13528	98	0	0
T7	236789	338	0	0
T8	231046	353	0	0
T9	596564	1063	0	0
T10	959	17	0	0
T11	526399	1342	0	0
T12	480989	14	0	0
T13	67095	1886	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230622	0	0
T1	8803	98	0	0
T2	6710	80	0	0
T3	13528	98	0	0
T7	236789	338	0	0
T8	231046	353	0	0
T9	596564	1063	0	0
T10	959	17	0	0
T11	526399	1342	0	0
T12	480989	14	0	0
T13	67095	1886	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	631840	0	0
T1	8803	104	0	0
T2	6710	83	0	0
T3	13528	98	0	0
T7	236789	388	0	0
T8	231046	408	0	0
T9	596564	1646	0	0
T10	959	18	0	0
T11	526399	2691	0	0
T12	480989	126	0	0
T13	67095	2709	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230622	0	0
T1	8803	98	0	0
T2	6710	80	0	0
T3	13528	98	0	0
T7	236789	338	0	0
T8	231046	353	0	0
T9	596564	1063	0	0
T10	959	17	0	0
T11	526399	1342	0	0
T12	480989	14	0	0
T13	67095	1886	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	222485	0	0
GntImpliesValid_A	420655702	222485	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	222485	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	2860321	0	0
ReadyAndValidImplyGrant_A	420655702	222485	0	0
ReqAndReadyImplyGrant_A	420655702	222485	0	0
ReqImpliesValid_A	420655702	568767	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	222485	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	222485	0	0
T1	8803	107	0	0
T2	6710	76	0	0
T3	13528	97	0	0
T7	236789	856	0	0
T8	231046	841	0	0
T9	596564	721	0	0
T10	959	23	0	0
T11	526399	918	0	0
T12	480989	11	0	0
T13	67095	427	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	222485	0	0
T1	8803	107	0	0
T2	6710	76	0	0
T3	13528	97	0	0
T7	236789	856	0	0
T8	231046	841	0	0
T9	596564	721	0	0
T10	959	23	0	0
T11	526399	918	0	0
T12	480989	11	0	0
T13	67095	427	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	222485	0	0
T1	8803	107	0	0
T2	6710	76	0	0
T3	13528	97	0	0
T7	236789	856	0	0
T8	231046	841	0	0
T9	596564	721	0	0
T10	959	23	0	0
T11	526399	918	0	0
T12	480989	11	0	0
T13	67095	427	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	2860321	0	0
T1	8803	103	0	0
T2	6710	74	0	0
T3	13528	98	0	0
T7	236789	4473	0	0
T8	231046	3900	0	0
T9	596564	5406	0	0
T10	959	22	0	0
T11	526399	6934	0	0
T12	480989	4006	0	0
T13	67095	422	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	222485	0	0
T1	8803	107	0	0
T2	6710	76	0	0
T3	13528	97	0	0
T7	236789	856	0	0
T8	231046	841	0	0
T9	596564	721	0	0
T10	959	23	0	0
T11	526399	918	0	0
T12	480989	11	0	0
T13	67095	427	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	222485	0	0
T1	8803	107	0	0
T2	6710	76	0	0
T3	13528	97	0	0
T7	236789	856	0	0
T8	231046	841	0	0
T9	596564	721	0	0
T10	959	23	0	0
T11	526399	918	0	0
T12	480989	11	0	0
T13	67095	427	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	568767	0	0
T1	8803	112	0	0
T2	6710	79	0	0
T3	13528	97	0	0
T7	236789	2293	0	0
T8	231046	4685	0	0
T9	596564	838	0	0
T10	959	25	0	0
T11	526399	1042	0	0
T12	480989	121	0	0
T13	67095	435	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	222485	0	0
T1	8803	107	0	0
T2	6710	76	0	0
T3	13528	97	0	0
T7	236789	856	0	0
T8	231046	841	0	0
T9	596564	721	0	0
T10	959	23	0	0
T11	526399	918	0	0
T12	480989	11	0	0
T13	67095	427	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	223802	0	0
GntImpliesValid_A	420655702	223802	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	223802	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	3042037	0	0
ReadyAndValidImplyGrant_A	420655702	223802	0	0
ReqAndReadyImplyGrant_A	420655702	223802	0	0
ReqImpliesValid_A	420655702	574380	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	223802	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	223802	0	0
T1	8803	109	0	0
T2	6710	66	0	0
T3	13528	95	0	0
T7	236789	332	0	0
T8	231046	360	0	0
T9	596564	1194	0	0
T10	959	20	0	0
T11	526399	878	0	0
T12	480989	12	0	0
T13	67095	972	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	223802	0	0
T1	8803	109	0	0
T2	6710	66	0	0
T3	13528	95	0	0
T7	236789	332	0	0
T8	231046	360	0	0
T9	596564	1194	0	0
T10	959	20	0	0
T11	526399	878	0	0
T12	480989	12	0	0
T13	67095	972	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	223802	0	0
T1	8803	109	0	0
T2	6710	66	0	0
T3	13528	95	0	0
T7	236789	332	0	0
T8	231046	360	0	0
T9	596564	1194	0	0
T10	959	20	0	0
T11	526399	878	0	0
T12	480989	12	0	0
T13	67095	972	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	3042037	0	0
T1	8803	100	0	0
T2	6710	64	0	0
T3	13528	96	0	0
T7	236789	2475	0	0
T8	231046	2575	0	0
T9	596564	7736	0	0
T10	959	20	0	0
T11	526399	6644	0	0
T12	480989	3728	0	0
T13	67095	856	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	223802	0	0
T1	8803	109	0	0
T2	6710	66	0	0
T3	13528	95	0	0
T7	236789	332	0	0
T8	231046	360	0	0
T9	596564	1194	0	0
T10	959	20	0	0
T11	526399	878	0	0
T12	480989	12	0	0
T13	67095	972	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	223802	0	0
T1	8803	109	0	0
T2	6710	66	0	0
T3	13528	95	0	0
T7	236789	332	0	0
T8	231046	360	0	0
T9	596564	1194	0	0
T10	959	20	0	0
T11	526399	878	0	0
T12	480989	12	0	0
T13	67095	972	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	574380	0	0
T1	8803	119	0	0
T2	6710	69	0	0
T3	13528	95	0	0
T7	236789	418	0	0
T8	231046	428	0	0
T9	596564	2013	0	0
T10	959	21	0	0
T11	526399	1041	0	0
T12	480989	156	0	0
T13	67095	1091	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	223802	0	0
T1	8803	109	0	0
T2	6710	66	0	0
T3	13528	95	0	0
T7	236789	332	0	0
T8	231046	360	0	0
T9	596564	1194	0	0
T10	959	20	0	0
T11	526399	878	0	0
T12	480989	12	0	0
T13	67095	972	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	218538	0	0
GntImpliesValid_A	420655702	218538	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	218538	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	2987385	0	0
ReadyAndValidImplyGrant_A	420655702	218538	0	0
ReqAndReadyImplyGrant_A	420655702	218538	0	0
ReqImpliesValid_A	420655702	590805	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	218538	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	218538	0	0
T1	8803	100	0	0
T2	6710	60	0	0
T3	13528	99	0	0
T7	236789	321	0	0
T8	231046	882	0	0
T9	596564	1683	0	0
T10	959	12	0	0
T11	526399	1339	0	0
T12	480989	9	0	0
T13	67095	1516	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	218538	0	0
T1	8803	100	0	0
T2	6710	60	0	0
T3	13528	99	0	0
T7	236789	321	0	0
T8	231046	882	0	0
T9	596564	1683	0	0
T10	959	12	0	0
T11	526399	1339	0	0
T12	480989	9	0	0
T13	67095	1516	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	218538	0	0
T1	8803	100	0	0
T2	6710	60	0	0
T3	13528	99	0	0
T7	236789	321	0	0
T8	231046	882	0	0
T9	596564	1683	0	0
T10	959	12	0	0
T11	526399	1339	0	0
T12	480989	9	0	0
T13	67095	1516	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	2987385	0	0
T1	8803	96	0	0
T2	6710	57	0	0
T3	13528	100	0	0
T7	236789	2448	0	0
T8	231046	5313	0	0
T9	596564	8848	0	0
T10	959	13	0	0
T11	526399	9471	0	0
T12	480989	2474	0	0
T13	67095	1184	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	218538	0	0
T1	8803	100	0	0
T2	6710	60	0	0
T3	13528	99	0	0
T7	236789	321	0	0
T8	231046	882	0	0
T9	596564	1683	0	0
T10	959	12	0	0
T11	526399	1339	0	0
T12	480989	9	0	0
T13	67095	1516	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	218538	0	0
T1	8803	100	0	0
T2	6710	60	0	0
T3	13528	99	0	0
T7	236789	321	0	0
T8	231046	882	0	0
T9	596564	1683	0	0
T10	959	12	0	0
T11	526399	1339	0	0
T12	480989	9	0	0
T13	67095	1516	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	590805	0	0
T1	8803	105	0	0
T2	6710	64	0	0
T3	13528	99	0	0
T7	236789	355	0	0
T8	231046	1644	0	0
T9	596564	4261	0	0
T10	959	12	0	0
T11	526399	1750	0	0
T12	480989	9	0	0
T13	67095	1851	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	218538	0	0
T1	8803	100	0	0
T2	6710	60	0	0
T3	13528	99	0	0
T7	236789	321	0	0
T8	231046	882	0	0
T9	596564	1683	0	0
T10	959	12	0	0
T11	526399	1339	0	0
T12	480989	9	0	0
T13	67095	1516	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	231877	0	0
GntImpliesValid_A	420655702	231877	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	231877	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	2964095	0	0
ReadyAndValidImplyGrant_A	420655702	231877	0	0
ReqAndReadyImplyGrant_A	420655702	231877	0	0
ReqImpliesValid_A	420655702	666204	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	231877	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	231877	0	0
T1	8803	91	0	0
T2	6710	69	0	0
T3	13528	118	0	0
T7	236789	333	0	0
T8	231046	805	0	0
T9	596564	1028	0	0
T10	959	17	0	0
T11	526399	1428	0	0
T12	480989	13	0	0
T13	67095	459	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	231877	0	0
T1	8803	91	0	0
T2	6710	69	0	0
T3	13528	118	0	0
T7	236789	333	0	0
T8	231046	805	0	0
T9	596564	1028	0	0
T10	959	17	0	0
T11	526399	1428	0	0
T12	480989	13	0	0
T13	67095	459	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	231877	0	0
T1	8803	91	0	0
T2	6710	69	0	0
T3	13528	118	0	0
T7	236789	333	0	0
T8	231046	805	0	0
T9	596564	1028	0	0
T10	959	17	0	0
T11	526399	1428	0	0
T12	480989	13	0	0
T13	67095	459	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	2964095	0	0
T1	8803	89	0	0
T2	6710	61	0	0
T3	13528	118	0	0
T7	236789	2583	0	0
T8	231046	5312	0	0
T9	596564	5740	0	0
T10	959	18	0	0
T11	526399	10857	0	0
T12	480989	4641	0	0
T13	67095	449	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	231877	0	0
T1	8803	91	0	0
T2	6710	69	0	0
T3	13528	118	0	0
T7	236789	333	0	0
T8	231046	805	0	0
T9	596564	1028	0	0
T10	959	17	0	0
T11	526399	1428	0	0
T12	480989	13	0	0
T13	67095	459	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	231877	0	0
T1	8803	91	0	0
T2	6710	69	0	0
T3	13528	118	0	0
T7	236789	333	0	0
T8	231046	805	0	0
T9	596564	1028	0	0
T10	959	17	0	0
T11	526399	1428	0	0
T12	480989	13	0	0
T13	67095	459	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	666204	0	0
T1	8803	94	0	0
T2	6710	78	0	0
T3	13528	119	0	0
T7	236789	361	0	0
T8	231046	2947	0	0
T9	596564	4299	0	0
T10	959	17	0	0
T11	526399	2032	0	0
T12	480989	241	0	0
T13	67095	472	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	231877	0	0
T1	8803	91	0	0
T2	6710	69	0	0
T3	13528	118	0	0
T7	236789	333	0	0
T8	231046	805	0	0
T9	596564	1028	0	0
T10	959	17	0	0
T11	526399	1428	0	0
T12	480989	13	0	0
T13	67095	459	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	222761	0	0
GntImpliesValid_A	420655702	222761	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	222761	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	2948364	0	0
ReadyAndValidImplyGrant_A	420655702	222761	0	0
ReqAndReadyImplyGrant_A	420655702	222761	0	0
ReqImpliesValid_A	420655702	598213	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	222761	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	222761	0	0
T1	8803	104	0	0
T2	6710	62	0	0
T3	13528	103	0	0
T7	236789	761	0	0
T8	231046	373	0	0
T9	596564	1140	0	0
T10	959	28	0	0
T11	526399	862	0	0
T12	480989	6	0	0
T13	67095	926	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	222761	0	0
T1	8803	104	0	0
T2	6710	62	0	0
T3	13528	103	0	0
T7	236789	761	0	0
T8	231046	373	0	0
T9	596564	1140	0	0
T10	959	28	0	0
T11	526399	862	0	0
T12	480989	6	0	0
T13	67095	926	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	222761	0	0
T1	8803	104	0	0
T2	6710	62	0	0
T3	13528	103	0	0
T7	236789	761	0	0
T8	231046	373	0	0
T9	596564	1140	0	0
T10	959	28	0	0
T11	526399	862	0	0
T12	480989	6	0	0
T13	67095	926	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	2948364	0	0
T1	8803	102	0	0
T2	6710	62	0	0
T3	13528	103	0	0
T7	236789	4934	0	0
T8	231046	2633	0	0
T9	596564	6049	0	0
T10	959	26	0	0
T11	526399	6634	0	0
T12	480989	2635	0	0
T13	67095	705	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	222761	0	0
T1	8803	104	0	0
T2	6710	62	0	0
T3	13528	103	0	0
T7	236789	761	0	0
T8	231046	373	0	0
T9	596564	1140	0	0
T10	959	28	0	0
T11	526399	862	0	0
T12	480989	6	0	0
T13	67095	926	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	222761	0	0
T1	8803	104	0	0
T2	6710	62	0	0
T3	13528	103	0	0
T7	236789	761	0	0
T8	231046	373	0	0
T9	596564	1140	0	0
T10	959	28	0	0
T11	526399	862	0	0
T12	480989	6	0	0
T13	67095	926	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	598213	0	0
T1	8803	107	0	0
T2	6710	63	0	0
T3	13528	104	0	0
T7	236789	1456	0	0
T8	231046	474	0	0
T9	596564	5197	0	0
T10	959	31	0	0
T11	526399	971	0	0
T12	480989	6	0	0
T13	67095	1150	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	222761	0	0
T1	8803	104	0	0
T2	6710	62	0	0
T3	13528	103	0	0
T7	236789	761	0	0
T8	231046	373	0	0
T9	596564	1140	0	0
T10	959	28	0	0
T11	526399	862	0	0
T12	480989	6	0	0
T13	67095	926	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	230728	0	0
GntImpliesValid_A	420655702	230728	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	230728	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	3019768	0	0
ReadyAndValidImplyGrant_A	420655702	230728	0	0
ReqAndReadyImplyGrant_A	420655702	230728	0	0
ReqImpliesValid_A	420655702	615828	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	230728	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230728	0	0
T1	8803	81	0	0
T2	6710	73	0	0
T3	13528	126	0	0
T7	236789	346	0	0
T8	231046	878	0	0
T9	596564	1216	0	0
T10	959	20	0	0
T11	526399	1370	0	0
T12	480989	8	0	0
T13	67095	882	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230728	0	0
T1	8803	81	0	0
T2	6710	73	0	0
T3	13528	126	0	0
T7	236789	346	0	0
T8	231046	878	0	0
T9	596564	1216	0	0
T10	959	20	0	0
T11	526399	1370	0	0
T12	480989	8	0	0
T13	67095	882	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230728	0	0
T1	8803	81	0	0
T2	6710	73	0	0
T3	13528	126	0	0
T7	236789	346	0	0
T8	231046	878	0	0
T9	596564	1216	0	0
T10	959	20	0	0
T11	526399	1370	0	0
T12	480989	8	0	0
T13	67095	882	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	3019768	0	0
T1	8803	76	0	0
T2	6710	66	0	0
T3	13528	127	0	0
T7	236789	2697	0	0
T8	231046	5451	0	0
T9	596564	8044	0	0
T10	959	17	0	0
T11	526399	10458	0	0
T12	480989	2276	0	0
T13	67095	582	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230728	0	0
T1	8803	81	0	0
T2	6710	73	0	0
T3	13528	126	0	0
T7	236789	346	0	0
T8	231046	878	0	0
T9	596564	1216	0	0
T10	959	20	0	0
T11	526399	1370	0	0
T12	480989	8	0	0
T13	67095	882	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230728	0	0
T1	8803	81	0	0
T2	6710	73	0	0
T3	13528	126	0	0
T7	236789	346	0	0
T8	231046	878	0	0
T9	596564	1216	0	0
T10	959	20	0	0
T11	526399	1370	0	0
T12	480989	8	0	0
T13	67095	882	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	615828	0	0
T1	8803	87	0	0
T2	6710	81	0	0
T3	13528	126	0	0
T7	236789	406	0	0
T8	231046	3114	0	0
T9	596564	3293	0	0
T10	959	24	0	0
T11	526399	1790	0	0
T12	480989	361	0	0
T13	67095	1185	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230728	0	0
T1	8803	81	0	0
T2	6710	73	0	0
T3	13528	126	0	0
T7	236789	346	0	0
T8	231046	878	0	0
T9	596564	1216	0	0
T10	959	20	0	0
T11	526399	1370	0	0
T12	480989	8	0	0
T13	67095	882	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	209587	0	0
GntImpliesValid_A	420655702	209587	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	209587	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	2938246	0	0
ReadyAndValidImplyGrant_A	420655702	209587	0	0
ReqAndReadyImplyGrant_A	420655702	209587	0	0
ReqImpliesValid_A	420655702	538567	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	209587	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	209587	0	0
T1	8803	82	0	0
T2	6710	79	0	0
T3	13528	109	0	0
T7	236789	775	0	0
T8	231046	363	0	0
T9	596564	1151	0	0
T10	959	19	0	0
T11	526399	925	0	0
T12	480989	12	0	0
T13	67095	429	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	209587	0	0
T1	8803	82	0	0
T2	6710	79	0	0
T3	13528	109	0	0
T7	236789	775	0	0
T8	231046	363	0	0
T9	596564	1151	0	0
T10	959	19	0	0
T11	526399	925	0	0
T12	480989	12	0	0
T13	67095	429	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	209587	0	0
T1	8803	82	0	0
T2	6710	79	0	0
T3	13528	109	0	0
T7	236789	775	0	0
T8	231046	363	0	0
T9	596564	1151	0	0
T10	959	19	0	0
T11	526399	925	0	0
T12	480989	12	0	0
T13	67095	429	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	2938246	0	0
T1	8803	79	0	0
T2	6710	74	0	0
T3	13528	109	0	0
T7	236789	5556	0	0
T8	231046	2639	0	0
T9	596564	8117	0	0
T10	959	19	0	0
T11	526399	7179	0	0
T12	480989	2988	0	0
T13	67095	423	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	209587	0	0
T1	8803	82	0	0
T2	6710	79	0	0
T3	13528	109	0	0
T7	236789	775	0	0
T8	231046	363	0	0
T9	596564	1151	0	0
T10	959	19	0	0
T11	526399	925	0	0
T12	480989	12	0	0
T13	67095	429	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	209587	0	0
T1	8803	82	0	0
T2	6710	79	0	0
T3	13528	109	0	0
T7	236789	775	0	0
T8	231046	363	0	0
T9	596564	1151	0	0
T10	959	19	0	0
T11	526399	925	0	0
T12	480989	12	0	0
T13	67095	429	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	538567	0	0
T1	8803	86	0	0
T2	6710	85	0	0
T3	13528	110	0	0
T7	236789	1799	0	0
T8	231046	430	0	0
T9	596564	2336	0	0
T10	959	20	0	0
T11	526399	1006	0	0
T12	480989	12	0	0
T13	67095	438	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	209587	0	0
T1	8803	82	0	0
T2	6710	79	0	0
T3	13528	109	0	0
T7	236789	775	0	0
T8	231046	363	0	0
T9	596564	1151	0	0
T10	959	19	0	0
T11	526399	925	0	0
T12	480989	12	0	0
T13	67095	429	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	242477	0	0
GntImpliesValid_A	420655702	242477	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	242477	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	3017312	0	0
ReadyAndValidImplyGrant_A	420655702	242477	0	0
ReqAndReadyImplyGrant_A	420655702	242477	0	0
ReqImpliesValid_A	420655702	641787	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	242477	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	242477	0	0
T1	8803	163	0	0
T2	6710	63	0	0
T3	13528	103	0	0
T7	236789	958	0	0
T8	231046	1817	0	0
T9	596564	1721	0	0
T10	959	8	0	0
T11	526399	1007	0	0
T12	480989	11	0	0
T13	67095	1133	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	242477	0	0
T1	8803	163	0	0
T2	6710	63	0	0
T3	13528	103	0	0
T7	236789	958	0	0
T8	231046	1817	0	0
T9	596564	1721	0	0
T10	959	8	0	0
T11	526399	1007	0	0
T12	480989	11	0	0
T13	67095	1133	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	242477	0	0
T1	8803	163	0	0
T2	6710	63	0	0
T3	13528	103	0	0
T7	236789	958	0	0
T8	231046	1817	0	0
T9	596564	1721	0	0
T10	959	8	0	0
T11	526399	1007	0	0
T12	480989	11	0	0
T13	67095	1133	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	3017312	0	0
T1	8803	155	0	0
T2	6710	64	0	0
T3	13528	103	0	0
T7	236789	6278	0	0
T8	231046	10791	0	0
T9	596564	11541	0	0
T10	959	9	0	0
T11	526399	7812	0	0
T12	480989	3792	0	0
T13	67095	859	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	242477	0	0
T1	8803	163	0	0
T2	6710	63	0	0
T3	13528	103	0	0
T7	236789	958	0	0
T8	231046	1817	0	0
T9	596564	1721	0	0
T10	959	8	0	0
T11	526399	1007	0	0
T12	480989	11	0	0
T13	67095	1133	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	242477	0	0
T1	8803	163	0	0
T2	6710	63	0	0
T3	13528	103	0	0
T7	236789	958	0	0
T8	231046	1817	0	0
T9	596564	1721	0	0
T10	959	8	0	0
T11	526399	1007	0	0
T12	480989	11	0	0
T13	67095	1133	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	641787	0	0
T1	8803	172	0	0
T2	6710	63	0	0
T3	13528	104	0	0
T7	236789	2631	0	0
T8	231046	7208	0	0
T9	596564	4191	0	0
T10	959	8	0	0
T11	526399	1142	0	0
T12	480989	11	0	0
T13	67095	1410	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	242477	0	0
T1	8803	163	0	0
T2	6710	63	0	0
T3	13528	103	0	0
T7	236789	958	0	0
T8	231046	1817	0	0
T9	596564	1721	0	0
T10	959	8	0	0
T11	526399	1007	0	0
T12	480989	11	0	0
T13	67095	1133	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	229775	0	0
GntImpliesValid_A	420655702	229775	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	229775	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	3010379	0	0
ReadyAndValidImplyGrant_A	420655702	229775	0	0
ReqAndReadyImplyGrant_A	420655702	229775	0	0
ReqImpliesValid_A	420655702	598511	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	229775	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	229775	0	0
T1	8803	89	0	0
T2	6710	74	0	0
T3	13528	92	0	0
T7	236789	840	0	0
T8	231046	410	0	0
T9	596564	1188	0	0
T10	959	18	0	0
T11	526399	911	0	0
T12	480989	12	0	0
T13	67095	2025	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	229775	0	0
T1	8803	89	0	0
T2	6710	74	0	0
T3	13528	92	0	0
T7	236789	840	0	0
T8	231046	410	0	0
T9	596564	1188	0	0
T10	959	18	0	0
T11	526399	911	0	0
T12	480989	12	0	0
T13	67095	2025	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	229775	0	0
T1	8803	89	0	0
T2	6710	74	0	0
T3	13528	92	0	0
T7	236789	840	0	0
T8	231046	410	0	0
T9	596564	1188	0	0
T10	959	18	0	0
T11	526399	911	0	0
T12	480989	12	0	0
T13	67095	2025	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	3010379	0	0
T1	8803	87	0	0
T2	6710	71	0	0
T3	13528	93	0	0
T7	236789	5267	0	0
T8	231046	3080	0	0
T9	596564	6366	0	0
T10	959	12	0	0
T11	526399	6913	0	0
T12	480989	3318	0	0
T13	67095	1035	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	229775	0	0
T1	8803	89	0	0
T2	6710	74	0	0
T3	13528	92	0	0
T7	236789	840	0	0
T8	231046	410	0	0
T9	596564	1188	0	0
T10	959	18	0	0
T11	526399	911	0	0
T12	480989	12	0	0
T13	67095	2025	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	229775	0	0
T1	8803	89	0	0
T2	6710	74	0	0
T3	13528	92	0	0
T7	236789	840	0	0
T8	231046	410	0	0
T9	596564	1188	0	0
T10	959	18	0	0
T11	526399	911	0	0
T12	480989	12	0	0
T13	67095	2025	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	598511	0	0
T1	8803	92	0	0
T2	6710	78	0	0
T3	13528	92	0	0
T7	236789	2917	0	0
T8	231046	459	0	0
T9	596564	5444	0	0
T10	959	25	0	0
T11	526399	1042	0	0
T12	480989	128	0	0
T13	67095	3018	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	229775	0	0
T1	8803	89	0	0
T2	6710	74	0	0
T3	13528	92	0	0
T7	236789	840	0	0
T8	231046	410	0	0
T9	596564	1188	0	0
T10	959	18	0	0
T11	526399	911	0	0
T12	480989	12	0	0
T13	67095	2025	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	221109	0	0
GntImpliesValid_A	420655702	221109	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	221109	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	2956607	0	0
ReadyAndValidImplyGrant_A	420655702	221109	0	0
ReqAndReadyImplyGrant_A	420655702	221109	0	0
ReqImpliesValid_A	420655702	588005	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	221109	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	221109	0	0
T1	8803	103	0	0
T2	6710	78	0	0
T3	13528	95	0	0
T7	236789	803	0	0
T8	231046	895	0	0
T9	596564	650	0	0
T10	959	11	0	0
T11	526399	896	0	0
T12	480989	17	0	0
T13	67095	471	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	221109	0	0
T1	8803	103	0	0
T2	6710	78	0	0
T3	13528	95	0	0
T7	236789	803	0	0
T8	231046	895	0	0
T9	596564	650	0	0
T10	959	11	0	0
T11	526399	896	0	0
T12	480989	17	0	0
T13	67095	471	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	221109	0	0
T1	8803	103	0	0
T2	6710	78	0	0
T3	13528	95	0	0
T7	236789	803	0	0
T8	231046	895	0	0
T9	596564	650	0	0
T10	959	11	0	0
T11	526399	896	0	0
T12	480989	17	0	0
T13	67095	471	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	2956607	0	0
T1	8803	101	0	0
T2	6710	74	0	0
T3	13528	96	0	0
T7	236789	5017	0	0
T8	231046	4093	0	0
T9	596564	4913	0	0
T10	959	11	0	0
T11	526399	6898	0	0
T12	480989	6549	0	0
T13	67095	456	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	221109	0	0
T1	8803	103	0	0
T2	6710	78	0	0
T3	13528	95	0	0
T7	236789	803	0	0
T8	231046	895	0	0
T9	596564	650	0	0
T10	959	11	0	0
T11	526399	896	0	0
T12	480989	17	0	0
T13	67095	471	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	221109	0	0
T1	8803	103	0	0
T2	6710	78	0	0
T3	13528	95	0	0
T7	236789	803	0	0
T8	231046	895	0	0
T9	596564	650	0	0
T10	959	11	0	0
T11	526399	896	0	0
T12	480989	17	0	0
T13	67095	471	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	588005	0	0
T1	8803	106	0	0
T2	6710	83	0	0
T3	13528	95	0	0
T7	236789	1366	0	0
T8	231046	2513	0	0
T9	596564	736	0	0
T10	959	12	0	0
T11	526399	1016	0	0
T12	480989	84	0	0
T13	67095	489	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	221109	0	0
T1	8803	103	0	0
T2	6710	78	0	0
T3	13528	95	0	0
T7	236789	803	0	0
T8	231046	895	0	0
T9	596564	650	0	0
T10	959	11	0	0
T11	526399	896	0	0
T12	480989	17	0	0
T13	67095	471	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	225564	0	0
GntImpliesValid_A	420655702	225564	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	225564	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	2985866	0	0
ReadyAndValidImplyGrant_A	420655702	225564	0	0
ReqAndReadyImplyGrant_A	420655702	225564	0	0
ReqImpliesValid_A	420655702	609416	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	225564	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	225564	0	0
T1	8803	95	0	0
T2	6710	72	0	0
T3	13528	90	0	0
T7	236789	801	0	0
T8	231046	904	0	0
T9	596564	2173	0	0
T10	959	20	0	0
T11	526399	1488	0	0
T12	480989	13	0	0
T13	67095	837	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	225564	0	0
T1	8803	95	0	0
T2	6710	72	0	0
T3	13528	90	0	0
T7	236789	801	0	0
T8	231046	904	0	0
T9	596564	2173	0	0
T10	959	20	0	0
T11	526399	1488	0	0
T12	480989	13	0	0
T13	67095	837	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	225564	0	0
T1	8803	95	0	0
T2	6710	72	0	0
T3	13528	90	0	0
T7	236789	801	0	0
T8	231046	904	0	0
T9	596564	2173	0	0
T10	959	20	0	0
T11	526399	1488	0	0
T12	480989	13	0	0
T13	67095	837	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	2985866	0	0
T1	8803	91	0	0
T2	6710	71	0	0
T3	13528	90	0	0
T7	236789	5223	0	0
T8	231046	5829	0	0
T9	596564	13130	0	0
T10	959	19	0	0
T11	526399	10031	0	0
T12	480989	3728	0	0
T13	67095	421	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	225564	0	0
T1	8803	95	0	0
T2	6710	72	0	0
T3	13528	90	0	0
T7	236789	801	0	0
T8	231046	904	0	0
T9	596564	2173	0	0
T10	959	20	0	0
T11	526399	1488	0	0
T12	480989	13	0	0
T13	67095	837	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	225564	0	0
T1	8803	95	0	0
T2	6710	72	0	0
T3	13528	90	0	0
T7	236789	801	0	0
T8	231046	904	0	0
T9	596564	2173	0	0
T10	959	20	0	0
T11	526399	1488	0	0
T12	480989	13	0	0
T13	67095	837	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	609416	0	0
T1	8803	100	0	0
T2	6710	74	0	0
T3	13528	91	0	0
T7	236789	2458	0	0
T8	231046	2623	0	0
T9	596564	3873	0	0
T10	959	22	0	0
T11	526399	2328	0	0
T12	480989	13	0	0
T13	67095	1256	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	225564	0	0
T1	8803	95	0	0
T2	6710	72	0	0
T3	13528	90	0	0
T7	236789	801	0	0
T8	231046	904	0	0
T9	596564	2173	0	0
T10	959	20	0	0
T11	526399	1488	0	0
T12	480989	13	0	0
T13	67095	837	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	223153	0	0
GntImpliesValid_A	420655702	223153	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	223153	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	2930233	0	0
ReadyAndValidImplyGrant_A	420655702	223153	0	0
ReqAndReadyImplyGrant_A	420655702	223153	0	0
ReqImpliesValid_A	420655702	575830	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	223153	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	223153	0	0
T1	8803	89	0	0
T2	6710	80	0	0
T3	13528	99	0	0
T7	236789	859	0	0
T8	231046	349	0	0
T9	596564	1762	0	0
T10	959	14	0	0
T11	526399	848	0	0
T12	480989	18	0	0
T13	67095	438	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	223153	0	0
T1	8803	89	0	0
T2	6710	80	0	0
T3	13528	99	0	0
T7	236789	859	0	0
T8	231046	349	0	0
T9	596564	1762	0	0
T10	959	14	0	0
T11	526399	848	0	0
T12	480989	18	0	0
T13	67095	438	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	223153	0	0
T1	8803	89	0	0
T2	6710	80	0	0
T3	13528	99	0	0
T7	236789	859	0	0
T8	231046	349	0	0
T9	596564	1762	0	0
T10	959	14	0	0
T11	526399	848	0	0
T12	480989	18	0	0
T13	67095	438	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	2930233	0	0
T1	8803	88	0	0
T2	6710	79	0	0
T3	13528	100	0	0
T7	236789	5838	0	0
T8	231046	2750	0	0
T9	596564	9176	0	0
T10	959	14	0	0
T11	526399	6479	0	0
T12	480989	5626	0	0
T13	67095	432	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	223153	0	0
T1	8803	89	0	0
T2	6710	80	0	0
T3	13528	99	0	0
T7	236789	859	0	0
T8	231046	349	0	0
T9	596564	1762	0	0
T10	959	14	0	0
T11	526399	848	0	0
T12	480989	18	0	0
T13	67095	438	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	223153	0	0
T1	8803	89	0	0
T2	6710	80	0	0
T3	13528	99	0	0
T7	236789	859	0	0
T8	231046	349	0	0
T9	596564	1762	0	0
T10	959	14	0	0
T11	526399	848	0	0
T12	480989	18	0	0
T13	67095	438	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	575830	0	0
T1	8803	91	0	0
T2	6710	82	0	0
T3	13528	99	0	0
T7	236789	2464	0	0
T8	231046	381	0	0
T9	596564	4330	0	0
T10	959	15	0	0
T11	526399	966	0	0
T12	480989	688	0	0
T13	67095	447	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	223153	0	0
T1	8803	89	0	0
T2	6710	80	0	0
T3	13528	99	0	0
T7	236789	859	0	0
T8	231046	349	0	0
T9	596564	1762	0	0
T10	959	14	0	0
T11	526399	848	0	0
T12	480989	18	0	0
T13	67095	438	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	230236	0	0
GntImpliesValid_A	420655702	230236	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	230236	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	2958598	0	0
ReadyAndValidImplyGrant_A	420655702	230236	0	0
ReqAndReadyImplyGrant_A	420655702	230236	0	0
ReqImpliesValid_A	420655702	617079	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	0	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	230236	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230236	0	0
T1	8803	94	0	0
T2	6710	61	0	0
T3	13528	96	0	0
T7	236789	319	0	0
T8	231046	377	0	0
T9	596564	1173	0	0
T10	959	12	0	0
T11	526399	1909	0	0
T12	480989	12	0	0
T13	67095	924	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230236	0	0
T1	8803	94	0	0
T2	6710	61	0	0
T3	13528	96	0	0
T7	236789	319	0	0
T8	231046	377	0	0
T9	596564	1173	0	0
T10	959	12	0	0
T11	526399	1909	0	0
T12	480989	12	0	0
T13	67095	924	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230236	0	0
T1	8803	94	0	0
T2	6710	61	0	0
T3	13528	96	0	0
T7	236789	319	0	0
T8	231046	377	0	0
T9	596564	1173	0	0
T10	959	12	0	0
T11	526399	1909	0	0
T12	480989	12	0	0
T13	67095	924	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	2958598	0	0
T1	8803	86	0	0
T2	6710	57	0	0
T3	13528	97	0	0
T7	236789	2353	0	0
T8	231046	2949	0	0
T9	596564	5855	0	0
T10	959	13	0	0
T11	526399	14384	0	0
T12	480989	5296	0	0
T13	67095	448	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230236	0	0
T1	8803	94	0	0
T2	6710	61	0	0
T3	13528	96	0	0
T7	236789	319	0	0
T8	231046	377	0	0
T9	596564	1173	0	0
T10	959	12	0	0
T11	526399	1909	0	0
T12	480989	12	0	0
T13	67095	924	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230236	0	0
T1	8803	94	0	0
T2	6710	61	0	0
T3	13528	96	0	0
T7	236789	319	0	0
T8	231046	377	0	0
T9	596564	1173	0	0
T10	959	12	0	0
T11	526399	1909	0	0
T12	480989	12	0	0
T13	67095	924	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	617079	0	0
T1	8803	103	0	0
T2	6710	66	0	0
T3	13528	96	0	0
T7	236789	380	0	0
T8	231046	450	0	0
T9	596564	5389	0	0
T10	959	12	0	0
T11	526399	3340	0	0
T12	480989	252	0	0
T13	67095	1403	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	230236	0	0
T1	8803	94	0	0
T2	6710	61	0	0
T3	13528	96	0	0
T7	236789	319	0	0
T8	231046	377	0	0
T9	596564	1173	0	0
T10	959	12	0	0
T11	526399	1909	0	0
T12	480989	12	0	0
T13	67095	924	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	924657	0	0
GntImpliesValid_A	420655702	924657	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	924657	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	11354303	0	0
ReadyAndValidImplyGrant_A	420655702	924657	0	0
ReqAndReadyImplyGrant_A	420655702	924657	0	0
ReqImpliesValid_A	420655702	2378557	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	21398	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	924657	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	924657	0	0
T1	8803	372	0	0
T2	6710	285	0	0
T3	13528	405	0	0
T7	236789	3502	0	0
T8	231046	2173	0	0
T9	596564	5987	0	0
T10	959	37	0	0
T11	526399	4106	0	0
T12	480989	40	0	0
T13	67095	2949	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	924657	0	0
T1	8803	372	0	0
T2	6710	285	0	0
T3	13528	405	0	0
T7	236789	3502	0	0
T8	231046	2173	0	0
T9	596564	5987	0	0
T10	959	37	0	0
T11	526399	4106	0	0
T12	480989	40	0	0
T13	67095	2949	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	924657	0	0
T1	8803	372	0	0
T2	6710	285	0	0
T3	13528	405	0	0
T7	236789	3502	0	0
T8	231046	2173	0	0
T9	596564	5987	0	0
T10	959	37	0	0
T11	526399	4106	0	0
T12	480989	40	0	0
T13	67095	2949	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	11354303	0	0
T1	8803	1	0	0
T2	6710	1	0	0
T3	13528	1	0	0
T7	236789	20646	0	0
T8	231046	13220	0	0
T9	596564	34056	0	0
T10	959	1	0	0
T11	526399	26811	0	0
T12	480989	13323	0	0
T13	67095	3	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	924657	0	0
T1	8803	372	0	0
T2	6710	285	0	0
T3	13528	405	0	0
T7	236789	3502	0	0
T8	231046	2173	0	0
T9	596564	5987	0	0
T10	959	37	0	0
T11	526399	4106	0	0
T12	480989	40	0	0
T13	67095	2949	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	924657	0	0
T1	8803	372	0	0
T2	6710	285	0	0
T3	13528	405	0	0
T7	236789	3502	0	0
T8	231046	2173	0	0
T9	596564	5987	0	0
T10	959	37	0	0
T11	526399	4106	0	0
T12	480989	40	0	0
T13	67095	2949	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	2378557	0	0
T1	8803	372	0	0
T2	6710	285	0	0
T3	13528	405	0	0
T7	236789	9094	0	0
T8	231046	3209	0	0
T9	596564	17189	0	0
T10	959	37	0	0
T11	526399	5550	0	0
T12	480989	458	0	0
T13	67095	2949	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	21398	0	900
T1	8803	5	0	1
T2	6710	2	0	1
T3	13528	8	0	1
T7	236789	2	0	1
T8	231046	0	0	1
T9	596564	15	0	1
T10	959	0	0	1
T11	526399	0	0	1
T12	480989	0	0	1
T13	67095	25	0	1
T14	0	15	0	0
T16	0	8	0	0
T17	0	12	0	0
T18	0	20	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	924657	0	0
T1	8803	372	0	0
T2	6710	285	0	0
T3	13528	405	0	0
T7	236789	3502	0	0
T8	231046	2173	0	0
T9	596564	5987	0	0
T10	959	37	0	0
T11	526399	4106	0	0
T12	480989	40	0	0
T13	67095	2949	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420655702	420527990	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420655702	915721	0	0
GntImpliesValid_A	420655702	915721	0	0
GrantKnown_A	420655702	420527990	0	0
IdxKnown_A	420655702	420527990	0	0
IndexIsCorrect_A	420655702	915721	0	0
LockArbDecision_A	420655702	0	0	0
NoReadyValidNoGrant_A	420655702	353260832	0	0
ReadyAndValidImplyGrant_A	420655702	915721	0	0
ReqAndReadyImplyGrant_A	420655702	915721	0	0
ReqImpliesValid_A	420655702	13454103	0	0
ReqStaysHighUntilGranted0_M	420655702	0	0	0
RoundRobin_A	420655702	31549	0	900
ValidKnown_A	420655702	420527990	0	0
gen_data_port_assertion.DataFlow_A	420655702	915721	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	915721	0	0
T1	8803	368	0	0
T2	6710	312	0	0
T3	13528	406	0	0
T7	236789	2014	0	0
T8	231046	2035	0	0
T9	596564	4325	0	0
T10	959	44	0	0
T11	526399	4899	0	0
T12	480989	38	0	0
T13	67095	2843	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	915721	0	0
T1	8803	368	0	0
T2	6710	312	0	0
T3	13528	406	0	0
T7	236789	2014	0	0
T8	231046	2035	0	0
T9	596564	4325	0	0
T10	959	44	0	0
T11	526399	4899	0	0
T12	480989	38	0	0
T13	67095	2843	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	915721	0	0
T1	8803	368	0	0
T2	6710	312	0	0
T3	13528	406	0	0
T7	236789	2014	0	0
T8	231046	2035	0	0
T9	596564	4325	0	0
T10	959	44	0	0
T11	526399	4899	0	0
T12	480989	38	0	0
T13	67095	2843	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	353260832	0	0
T1	8803	1	0	0
T2	6710	1	0	0
T3	13528	1	0	0
T7	236789	200700	0	0
T8	231046	189914	0	0
T9	596564	510687	0	0
T10	959	1	0	0
T11	526399	442188	0	0
T12	480989	463694	0	0
T13	67095	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	915721	0	0
T1	8803	368	0	0
T2	6710	312	0	0
T3	13528	406	0	0
T7	236789	2014	0	0
T8	231046	2035	0	0
T9	596564	4325	0	0
T10	959	44	0	0
T11	526399	4899	0	0
T12	480989	38	0	0
T13	67095	2843	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	915721	0	0
T1	8803	368	0	0
T2	6710	312	0	0
T3	13528	406	0	0
T7	236789	2014	0	0
T8	231046	2035	0	0
T9	596564	4325	0	0
T10	959	44	0	0
T11	526399	4899	0	0
T12	480989	38	0	0
T13	67095	2843	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	13454103	0	0
T1	8803	368	0	0
T2	6710	312	0	0
T3	13528	406	0	0
T7	236789	15837	0	0
T8	231046	16073	0	0
T9	596564	36013	0	0
T10	959	44	0	0
T11	526399	41167	0	0
T12	480989	12004	0	0
T13	67095	2843	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	31549	0	900
T1	8803	3	0	1
T2	6710	4	0	1
T3	13528	7	0	1
T7	236789	1	0	1
T8	231046	4	0	1
T9	596564	5	0	1
T10	959	0	0	1
T11	526399	6	0	1
T12	480989	0	0	1
T13	67095	25	0	1
T14	0	12	0	0
T15	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	420527990	0	0
T1	8803	8759	0	0
T2	6710	6635	0	0
T3	13528	13441	0	0
T7	236789	235898	0	0
T8	231046	231020	0	0
T9	596564	596527	0	0
T10	959	943	0	0
T11	526399	526204	0	0
T12	480989	480967	0	0
T13	67095	66952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420655702	915721	0	0
T1	8803	368	0	0
T2	6710	312	0	0
T3	13528	406	0	0
T7	236789	2014	0	0
T8	231046	2035	0	0
T9	596564	4325	0	0
T10	959	44	0	0
T11	526399	4899	0	0
T12	480989	38	0	0
T13	67095	2843	0	0